AT49BV163T - Atmel Corporation

Features

•Single Voltage Read/Write Operation: 2.65V to 3.6V

•Access Time – 70 ns

•Sector Erase Architecture

– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout

– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

•Fast Word Program Time – 12 µs

•Fast Sector Erase Time – 300 ms

•Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase

of a Different Sector

– Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending

Programming of Any Other Byte/Word

•Low-power Operation

– 12 mA Active

– 13 µA Standby

•Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

•VPP Pin for Write Protection

•RESET Input for Device Initialization

•Sector Lockdown Support

•TSOP and CBGA Package Options

•Top or Bottom Boot Block Configuration Available

•128-bit Protection Register

•Minimum 100,000 Erase Cycles

•Common Flash Interface (CFI)

Description

The AT49BV162A(T)/163A(T) is a 2.7-volt 16-megabit Flash memory organized as

1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data

appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided

into 71 sectors for erase operations. The device is offered in a 48-lead TSOP and a

48-ball CBGA package. The device has CE and OE control signals to avoid any bus

contention. This device can be read or reprogrammed using a single power supply,

making it ideally suited for in-system programming.

Note: 1. The VPP pin is not available for the AT49BV163A(T).

Pin Configurations

Pin Name Function

A0 - A19 Addresses

CE Chip Enable

OE Output Enable

WE Write Enable

RESET Reset

RDY/BUSY READY/BUSY Output

VPP(1) Write Protection

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1) I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

BYTE Selects Byte or Word Mode

NC No Connect

16-megabit

(1M x 16/2M x 8)

3-volt Only

Flash Memory

AT49BV162A

AT49BV162AT

AT49BV163A

AT49BV163AT

3349G–FLASH–7/04

2AT49BV162/163A(T)

3349G–FLASH–7/04

AT49BV162A(T)

TSOP Top View

Type 1

A15

A14

A13

A12

A11

A10

A19

RESET

VPP

RDY/BUSY

A18

A17

A16

BYTE

GND

I/O15/A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

AT49BV162A(T)

CBGA Top View

(Ball Down)

123456

RDY/BUSY

VPP

A18

I/O2

I/O10

I/O11

I/O3

VSS

A17

I/O0

I/O8

I/O9

I/O1

RST

A19

I/O5

I/O12

VCC

I/O4

A10

A11

I/O7

I/O14

I/O13

I/O6

A13

A12

A14

A15

A16

BYTE

I/015/A-1

VSS

The device powers on in the read mode. Command sequences are used to place the device

in other operation modes such as program and erase. The device has the capability to protect

the data in any sector (see “Sector Lockdown” section).

To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend

feature. This feature will put the erase or program on hold for any amount of time and let the

user read data from or program data to any of the remaining sectors within the memory. The

end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by

the toggle bit.

The VPP pin provides data protection. When the VPP input is below 0.4V, the program and

erase functions are inhibited. When VPP is at 0.9V or above, normal program and erase oper-

ations can be performed.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the require-

ment of entering the three-byte program sequence is offered to further improve programming

time. After entering the six-byte code, only single pulses on the write control lines are required

for writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering

down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing

it back to VCC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands

will not work while in this mode; if entered they will result in data being programmed into the

device. It is not recommended that the six-byte code reside in the software of the final product

but only exist in external programming code.

The BYTE pin controls whether the device data I/O pins operate in the byte or word configura-

tion. If the BYTE pin is set at logic “1”, the device is in word configuration, I/O0 - I/O15 are

active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins

I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-

stated, and the I/O15 pin is used as an input for the LSB (A-1) address function.

AT49BV163A(T)

TSOP Top View

Type 1

A15

A14

A13

A12

A11

A10

A19

RESET

RDY/BUSY

A18

A17

A16

BYTE

GND

I/O15/A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

AT49BV162/163A(T)

3349G–FLASH–7/04

Block Diagram

IDENTIFIER

STATUS

DATA

COMPARATOR

OUTPUT

MULTIPLEXER

OUTPUT

BUFFER

INPUT

BUFFER

COMMAND

DATA

Y-GATING

WRITE STATE

MACHINE PROGRAM/ERASE

VOLTAGE SWITCH

RESET

BYTE

RDY/BUSY

VPP

VCC

GND

Y-DECODER

X-DECODER

INPUT

BUFFER

ADDRESS

LATCH

I/O0 - I/O15/A-1

A0 - A19

MAIN

MEMORY

4AT49BV162/163A(T)

3349G–FLASH–7/04

Device

Operation

READ: The AT49BV162A(T)/163A(T) is accessed like an EPROM. When CE and OE are low

and WE is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the “Command Definition in Hex” table on page 12 (I/O8 - I/O15 are

don’t care inputs for the command codes). The command sequences are written by applying a

low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address

is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the

first rising edge of CE or WE. Standard microprocessor write timings are used. The address

locations used in the command sequences are not affected by entering the command

sequences.

RESET: A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is tEC.

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sec-

tors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while

the 30H data input command is latched on the rising edge of WE. The sector erase starts after

the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a sector is tSEC. When the sec-

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector

Erase command). An attempt to erase a sector that has been protected will result in the oper-

ation terminating immediately.

BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-

cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the

internal device command register and is a four-bus cycle operation. The device will automati-

cally generate the required internal program pulses.

AT49BV162/163A(T)

3349G–FLASH–7/04

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle

time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the

erase or program operation was performed successfully.

VPP PIN: The circuitry of the AT49BV162A(T) is designed so that the device cannot be pro-

grammed or erased if the VPP voltage is less that 0.4V. When VPP is at 0.9V or above, normal

program and erase operations can be performed. The VPP pin cannot be left floating.

PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a

program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11

and the following four sections describe the function of these bits. To provide greater flexibility

for system designers, the AT49BV162A(T)/163A(T) contains a programmable configuration

figuration register can be set to one of two different values, “00” or “01”. If the configuration

gram or erase operation. If the configuration register is set to a “01”, a Product ID Exit

command must be given after a successful program or erase operation before the part will

return to the read mode. It is important to note that whether the configuration register is set to

a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID

Exit command to return the device to read mode. The default value (after power-up) for the

configuration register is “00”. Using the four-bus cycle Set Configuration Register command as

shown in the “Command Definition in Hex” table on page 12, the value of the configuration

figuration register. The value of the configuration register will affect the operation of the I/O7

status bit as described below.

DATA POLLING: The AT49BV162A(T)/163A(T) features Data Polling to indicate the end of a

program cycle. If the status configuration register is set to a “00”, during a program cycle an

attempted read of the last byte/word loaded will result in the complement of the loaded data on

I/O7. Once the program cycle has been completed, true data is valid on all outputs and the

next cycle may begin. During a chip or sector erase operation, an attempt to read the device

will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read

from the device. Data Polling may begin at any time during the program cycle. Please see

“Status Bit Table” on page 11 for more details.

If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the

device is actively programming or erasing data. I/O7 will go high when the device has com-

pleted a program or erase operation. Once I/O7 has gone high, status information on the other

pins can be checked.

The Data Polling status bit must be used in conjunction with the erase/program and VPP status

bit as shown in the algorithm in Figures 1 and 2 on page 9.

6AT49BV162/163A(T)

3349G–FLASH–7/04

TOGGLE BIT: In addition to Data Polling the AT49BV162A(T)/163A(T) provides another

method for determining the end of a program or erase cycle. During a program or erase oper-

ation, successive attempts to read data from the memory will result in I/O6 toggling between

one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data

will be read. Examining the toggle bit may begin at any time during a program cycle. Please

see “Status Bit Table” on page 11 for more details.

The toggle bit status bit should be used in conjunction with the erase/program and VPP status

bit as shown in the algorithm in Figures 3 and 4 on page 10.

ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates

whether the program or erase operation has exceeded a specified internal pulse count limit. If

the status bit is a “1”, the device is unable to verify that an erase or a byte/word program oper-

ation has been successfully performed. If a program (Sector Erase) command is issued to a

protected sector, the protected sector will not be programmed (erased). The device will go to a

status read mode and the I/O5 status bit will be set high, indicating the program (erase) opera-

tion did not complete as requested. Once the erase/program status bit has been set to a “1”,

the system must write the Product ID Exit command to return to the read mode. The

erase/program status bit is a “0” while the erase or program operation is still in progress.

Please see “Status Bit Table” on page 11 for more details.

VPP STATUS BIT: The AT49BV162A(T) provides a status bit on I/O3, which provides informa-

tion regarding the voltage level of the VPP pin. During a program or erase operation, if the

voltage on the VPP pin is not high enough to perform the desired operation successfully, the

I/O3 status bit will be a “1”. Once the VPP status bit has been set to a “1”, the system must

write the Product ID Exit command to return to the read mode. On the other hand, if the volt-

age level is high enough to perform a program or erase operation successfully, the VPP status

bit will output a “0”. Please see “Status Bit Table” on page 11 for more details.

SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre-

vents programming of data in the designated sectors once the feature has been enabled.

These sectors can contain secure code that is used to bring up the system. Enabling the lock-

down feature will allow the boot code to stay in the device while data in the rest of the device is

updated. This feature does not have to be activated; any sector’s usage as a write-protected

region is optional to the user.

At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector,

the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked

down, the contents of the sector is read-only and cannot be erased or programmed.

SECTOR LOCKDOWN DETECTION: A software method is available to determine if program-

ming of a sector is locked down. When the device is in the software product identification

mode (see “Software Product Identification Entry/Exit” sections on page 23), a read from

address location 00002H within a sector will show if programming the sector is locked down. If

the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program

lockdown feature has been enabled and the sector cannot be programmed. The software

product identification exit code should be used to return to standard operation.

AT49BV162/163A(T)

3349G–FLASH–7/04

SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is

through reset or power-up cycles. After power-up or reset, the content of a sector that is

locked down can be erased and reprogrammed.

ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to

interrupt a sector or chip erase operation and then program or read data from a different sector

within the memory. After the Erase Suspend command is given, the device requires a maxi-

mum time of 15 µs to suspend the erase operation. After the erase operation has been

suspended, the system can then read data or program data to any other sector within the

device. An address is not required during the Erase Suspend command. During a sector erase

suspend, another sector cannot be erased. To resume the sector erase operation, the system

must write the Erase Resume command. The Erase Resume command is a one-bus cycle

command. The device also supports an erase suspend during a complete chip erase. While

the chip erase is suspended, the user can read from any sector within the memory that is pro-

tected. The command sequence for a chip erase suspend and a sector erase suspend are the

same.

PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the

system to interrupt a programming operation and then read data from a different byte/word

within the memory. After the Program Suspend command is given, the device requires a max-

imum of 20 µs to suspend the programming operation. After the programming operation has

been suspended, the system can then read data from any other byte/word that is not con-

tained in the sector in which the programming operation was suspended. An address is not

required during the program suspend operation. To resume the programming operation, the

system must write the Program Resume command. The program suspend and resume are

one-bus cycle commands. The command sequence for the erase suspend and program sus-

pend are the same, and the command sequence for the erase resume and program resume

are the same.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-

ufacturer as Atmel. It is accessed using a software operation.

For details, see “Operating Modes” on page 16 or “Software Product Identification Entry/Exit”

sections on page 23.

128-BIT PROTECTION REGISTER: The AT49BV162A(T)/163A(T) contains a 128-bit register

that can be used for security purposes in system design. The protection register is divided into

two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A

is non-changeable and is programmed at the factory with a unique number. The data in block

B is programmed by the user and can be locked out such that data in the block cannot be

reprogrammed. To program block B in the protection register, the four-bus cycle Program Pro-

tection Register command must be used as shown in the “Command Definition in Hex” table

on page 12. To lock out block B, the four-bus cycle Lock Protection Register command must

be used as shown in the “Command Definition in Hex” table. Data bit D1 must be zero during

the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To deter-

mine whether block B is locked out, the Product ID Entry command is given followed by a read

operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block

B can be reprogrammed. Please see the “Protection Register Addressing Table” on page 13

for the address locations in the protection register. To read the protection register, the Product

ID Entry command is given followed by a normal read operation from an address within the

protection register. After determining whether block B is protected or not, or reading the pro-

tection register, the Product ID Exit command must be given prior to performing any other

operation.

RDY/BUSY: An open-drain READY/BUSY output pin provides another method of detecting

the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal

program and erase cycles and is released at the completion of the cycle. The open-drain con-

8AT49BV162/163A(T)

3349G–FLASH–7/04

nection allows for OR-tying of several devices to the same RDY/BUSY line. Please see

“Status Bit Table” on page 11 for more details.

CFI: Common Flash Interface (CFI) is a published, standardized data structure that may be

read from a flash device. CFI allows system software to query the installed device to deter-

mine the configurations, various electrical and timing parameters, and functions supported by

the device. CFI is used to allow the system to learn how to interface to the flash device most

optimally. The two primary benefits of using CFI are ease of upgrading and second source

availability. The command to enter the CFI Query mode is a one-bus cycle command which

requires writing data 98h to address 55h. The CFI Query command can be written when the

device is ready to read data or can also be written when the part is in the product ID mode.

Once in the CFI Query mode, the system can read CFI data at the addresses given in Table 1

on page 24. To exit the CFI Query mode, the product ID exit command must be given.

HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against

inadvertent programs to the AT49BV162A(T)/163A(T) in the following ways: (a) VCC sense: if

VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once

VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical)

before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high

inhibits program cycles. (d) Program inhibit: VPP is less than VILPP. (e) VPP power-on delay:

once VPP has reached 1.65V, program and erase operations are inhibited for 100 ns.

INPUT LEVELS: While operating with a 2.65V to 3.6V power supply, the address inputs and

control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the

operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.

AT49BV162/163A(T)

3349G–FLASH–7/04

Figure 1. Data Polling Algorithm

(Configuration Register = 00)

Notes: 1. VA = Valid address for programming. During a sec-

tor erase operation, a valid address is any sector

address within the sector being erased. During

chip erase, a valid address is any non-protected

sector address.

2. I/O7 should be rechecked even if I/O5 = “1”

because I/O7 may change simultaneously with

I/O5.

START

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

YES

Program/Erase

Operation

Successful,

Device in

Read Mode

Figure 2. Data Polling Algorithm

(Configuration Register = 01)

Notes: 1. VA = Valid address for programming. During a sec-

tor erase operation, a valid address is any sector

address within the sector being erased. During

chip erase, a valid address is any non-protected

sector address.

2. I/O7 should be rechecked even if I/O5 = “1”

because I/O7 may change simultaneously with

I/O5.

START

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

YES

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

10 AT49BV162/163A(T)

3349G–FLASH–7/04

Figure 3. Toggle Bit Algorithm

(Configuration Register = 00)

Note: 1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling

as I/O5 changes to “1”.

START

Read I/O7 - I/O0

Toggle Bit =

Toggle?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Program/Erase

Operation

Successful,

Device in

Read Mode

YES

Figure 4. Toggle Bit Algorithm

(Configuration Register = 01)

Note: 1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling

as I/O5 changes to “1”.

START

Read I/O7 - I/O0

Toggle Bit =

Toggle?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

YES

AT49BV162/163A(T)

3349G–FLASH–7/04

Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or

sector erase operation is performed on a protected sector.

2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations. This

status bit is not available for the AT49BV163A(T).

Status Bit Table

Status Bit

I/O7 I/O7 I/O6 I/O5(1) I/O3(2) I/O2 RDY/BUSY

Configuration Register 00 01 00/01 00/01 00/01 00/01 00/01

Programming I/O7 0TOGGLE0010

Erasing 0 0 TOGGLE 0 0 TOGGLE 0

Erase Suspended & Read

Erasing Sector 11100TOGGLE1

Erase Suspended & Read

Non-erasing Sector DATA DATA DATA DATA DATA DATA 1

Erase Suspended &

Program Non-erasing Sector I/O7 0 TOGGLE 0 0 TOGGLE 0

Erase Suspended &

Program Suspended and

Reading from Non-

suspended Sectors

DATA DATA DATA DATA DATA DATA 1

Program Suspended & Read

Programming Sector I/O7 1 1 0 0 TOGGLE 1

Program Suspended & Read

Non-programming Sector DATA DATA DATA DATA DATA DATA 1

12 AT49BV162/163A(T)

3349G–FLASH–7/04

Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8

are don’t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are don’t care in

the word mode. Address A19 through A11 and A-1 are don’t care in the byte mode.

2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 14 - 18 for details).

4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled.

5. Either one of the Product ID Exit commands can be used.

6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.

7. The default state (after power-up) of the configuration register is “00”.

8. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.

9. This fast programming option enables the user to program two words in parallel only when VPP = 12V. The Addresses, Addr1 and Addr2, of

the two words, DIN1 and DIN2, must only differ in address A0. This command should be used during manufacturing purposes only.

Command Definition in Hex(1)

Command

Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr DOUT

Chip Erase 6 555 AA AAA(2) 55 555 80 555 AA AAA 55 555 10

Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA(3)(4) 30

Byte/Word Program 4 555 AA AAA 55 555 A0 Addr DIN

Dual Byte/Word

Program(9) 5 555 AA AAA 55 555 E0 Addr1 DIN1 Addr2 DIN2

Enter Single Pulse

Program Mode 6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0

Single Pulse

Byte/Word Program 1 Addr DIN

Sector Lockdown 6 555 AA AAA(2) 55 555 80 555 AA AAA 55 SA(3)(4) 60

Erase/Program

Suspend 1 XXX B0

Erase/Program

Resume 1 XXX 30

Product ID Entry 3 555 AA AAA 55 555 90

Product ID Exit(5) 3 555 AA AAA 55 555 F0(8)

Product ID Exit(5) 1 XXX F0(8)

Program Protection

Lock Protection

Status of Block B

Protection 4 555 AA AAA 55 555 90 80 DOUT(6)

Set Configuration

CFI Query 1 X55 98

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to VCC + 0.6V

Voltage on VPP

with Respect to Ground ...................................-0.6V to +13.0V

AT49BV162/163A(T)

3349G–FLASH–7/04

Note: All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.

Protection Register Addressing Table

Word Use Block A7 A6 A5 A4 A3 A2 A1 A0

0 Factory A 10000001

1 Factory A 10000010

2 Factory A 10000011

3 Factory A 10000100

4 User B 10000101

5 User B 10000110

6 User B 10000111

7 User B 10001000

14 AT49BV162/163A(T)

3349G–FLASH–7/04

AT49BV162A/163A – Sector Address Table

Sector Size (Bytes/Words)

Address Range (A19 - A-1)

x16

Address Range (A19 - A0)

SA0 8K/4K 000000 - 001FFF 00000 - 00FFF

SA1 8K/4K 002000 - 003FFF 01000 - 01FFF

SA2 8K/4K 004000 - 005FFF 02000 - 02FFF

SA3 8K/4K 006000 - 007FFF 03000 - 03FFF

SA4 8K/4K 008000 - 009FFF 04000 - 04FFF

SA5 8K/4K 00A000 - 00BFFF 05000 - 05FFF

SA6 8K/4K 00C000 - 00DFFF 06000 - 06FFF

SA7 8K/4K 00E000 - 00FFFF 07000 - 07FFF

SA8 64K/32K 010000 - 01FFFF 08000 - 0FFFF

SA9 64K/32K 020000 - 02FFFF 10000 - 17FFF

SA10 64K/32K 030000 - 03FFFF 18000 - 1FFFF

SA11 64K/32K 040000 - 04FFFF 20000 - 27FFF

SA12 64K/32K 050000 - 05FFFF 28000 - 2FFFF

SA13 64K/32K 060000 - 06FFFF 30000 - 37FFF

SA14 64K/32K 070000 - 07FFFF 38000 - 3FFFF

SA15 64K/32K 080000 - 08FFFF 40000 - 47FFF

SA16 64K/32K 090000 - 09FFFF 48000 - 4FFFF

SA17 64K/32K 0A0000 - 0AFFFF 50000 - 57FFF

SA18 64K/32K 0B0000 - 0BFFFF 58000 - 5FFFF

SA19 64K/32K 0C0000 - 0CFFFF 60000 - 67FFF

SA20 64K/32K 0D0000 - 0DFFFF 68000 - 6FFFF

SA21 64K/32K 0E0000 - 0EFFFF 70000 - 77FFF

SA22 64K/32K 0F0000 - 0FFFFF 78000 - 7FFFF

SA23 64K/32K 100000 - 10FFFF 80000 - 87FFF

SA24 64K/32K 110000 - 11FFFF 88000 - 8FFFF

SA25 64K/32K 120000 - 12FFFF 90000 - 97FFF

SA26 64K/32K 130000 - 13FFFF 98000 - 9FFFF

SA27 64K/32K 140000 - 14FFFF A0000 - A7FFF

SA28 64K/32K 150000 - 15FFFF A8000 - AFFFF

SA29 64K/32K 160000 - 16FFFF B0000 - B7FFF

SA30 64K/32K 170000 - 17FFFF B8000 - BFFFF

SA31 64K/32K 180000 - 18FFFF C0000 - C7FFF

SA32 64K/32K 190000 - 19FFFF C8000 - CFFFF

SA33 64K/32K 1A0000 - 1AFFFF D0000 - D7FFF

SA34 64K/32K 1B0000 - 1BFFFF D8000 - DFFFF

SA35 64K/32K 1C0000 - 1CFFFF E0000 - E7FFF

SA36 64K/32K 1D0000 - 1DFFFF E8000 - EFFFF

SA37 64K/32K 1E0000 - 1EFFFF F0000 - F7FFF

SA38 64K/32K 1F0000 - 1FFFFF F8000 - FFFFF

AT49BV162/163A(T)

3349G–FLASH–7/04

AT49BV162AT/163AT – Sector Address Table

Sector Size (Bytes/Words)

Address Range (A19 - A-1)

x16

Address Range (A19 - A0)

SA0 64K/32K 000000 - 00FFFF 00000 - 07FFF

SA1 64K/32K 010000 - 01FFFF 08000 - 0FFFF

SA2 64K/32K 020000 - 02FFFF 10000 - 17FFF

SA3 64K/32K 030000 - 03FFFF 18000 - 1FFFF

SA4 64K/32K 040000 - 04FFFF 20000 - 27FFF

SA5 64K/32K 050000 - 05FFFF 28000 - 2FFFF

SA6 64K/32K 060000 - 06FFFF 30000 - 37FFF

SA7 64K/32K 070000 - 07FFFF 38000 - 3FFFF

SA8 64K/32K 080000 - 08FFFF 40000 - 47FFF

SA9 64K/32K 090000 - 09FFFF 48000 - 4FFFF

SA10 64K/32K 0A0000 - 0AFFFF 50000 - 57FFF

SA11 64K/32K 0B0000 - 0BFFFF 58000 - 5FFFF

SA12 64K/32K 0C0000 - 0CFFFF 60000 - 67FFF

SA13 64K/32K 0D0000 - 0DFFFF 68000 - 6FFFF

SA14 64K/32K 0E0000 - 0EFFFF 70000 - 77FFF

SA15 64K/32K 0F0000 - 0FFFFF 78000 - 7FFFF

SA16 64K/32K 100000 - 10FFFF 80000 - 87FFF

SA17 64K/32K 110000 - 11FFFF 88000 - 8FFFF

SA18 64K/32K 120000 - 12FFFF 90000 - 97FFF

SA19 64K/32K 130000 - 13FFFF 98000 - 9FFFF

SA20 64K/32K 140000 - 14FFFF A0000 - A7FFF

SA21 64K/32K 150000 - 15FFFF A8000 - AFFFF

SA22 64K/32K 160000 - 16FFFF B0000 - B7FFF

SA23 64K/32K 170000 - 17FFFF B8000 - BFFFF

SA24 64K/32K 180000 - 18FFFF C0000 - C7FFF

SA25 64K/32K 190000 - 19FFFF C8000 - CFFFF

SA26 64K/32K 1A0000 - 1AFFFF D0000 - D7FFF

SA27 64K/32K 1B0000 - 1BFFFF D8000 - DFFFF

SA28 64K/32K 1C0000 - 1CFFFF E0000 - E7FFF

SA29 64K/32K 1D0000 - 1DFFFF E8000 - EFFFF

SA30 64K/32K 1E0000 - 1EFFFF F0000 - F7FFF

SA31 8K/4K 1F0000 - 1F1FFF F8000 - F8FFF

SA32 8K/4K 1F2000 - 1F3FFF F9000 - F9FFF

SA33 8K/4K 1F4000 - 1F5FFF FA000 - FAFFF

SA34 8K/4K 1F6000 - 1F7FFF FB000 - FBFFF

SA35 8K/4K 1F8000 - 1F9FFF FC000 - FCFFF

SA36 8K/4K 1FA000 - 1FBFFF FD000 - FDFFF

SA37 8K/4K 1FC000 - 1FDFFF FE000 - FEFFF

SA38 8K/4K 1FE000 - 1FFFFF FF000 - FFFFF

16 AT49BV162/163A(T)

3349G–FLASH–7/04

Notes: 1. X can be VIL or VIH.

2. Refer to AC programming waveforms on page 21.

3. VH = 12.0V ± 0.5V.

4. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C0H (x8)-AT49BV162A/163A; 00C0H (x16)-AT49BV162A/163A;

C2H (x8)-AT49BV162AT/163AT; 00C2H (x16)-AT49BV162AT/163AT.

5. See details under “Software Product Identification Entry/Exit” on page 23.

6. VIHPP (min) = 0.9V; VIHPP (max) = 3.6V.

7. VILPP (max) = 0.4V.

8. VPP is not available for the AT49BV163A(T).

DC and AC Operating Range

AT49BV162A(T)/163A(T)-70

Operating

Temperature (Case) Ind. -40°C - 85°C

VCC Power Supply 2.65V to 3.6V

Operating Modes

Mode CE OE WE RESET VPP(8) Ai I/O

Read VIL VIL VIH VIH XAiD

OUT

Program/Erase(2) VIL VIH VIL VIH VIHPP(6) Ai DIN

Standby/Program Inhibit VIH X(1) XV

IH X X High-Z

Program Inhibit

XXV

IH VIH X

IL XV

IH X

XXX V

IH VILPP(7)

Output Disable X VIH XV

IH X High-Z

Reset X X X VIL X X High-Z

Product Identification Software(5) VIH

A0 = VIL, A1 - A19 = VIL Manufacturer Code(4)

A0 = VIH, A1 - A19 = VIL Device Code(4)

AT49BV162/163A(T)

3349G–FLASH–7/04

Note: 1. In the erase mode, ICC is 45 mA.

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

ILI Input Load Current VIN = 0V to VCC 2µA

ILO Output Leakage Current VI/O = 0V to VCC 10 µA

ISB VCC Standby Current CMOS CE = VCC - 0.3V to

VCC

13 25 µA

ICC (1) VCC Active Read Current f = 5 MHz; IOUT = 0

mA 12 25 mA

ICC1 VCC Programming Current 40 mA

IPP1 VPP Input Load Current 5µA

VIL Input Low Voltage 0.6 V

VIH Input High Voltage 2.0 V

VOL1 Output Low Voltage IOL = 2.1 mA 0.45 V

VOL2 Output Low Voltage IOL = 1.0 mA 0.20 V

VOH1 Output High Voltage IOH = -400 µA 2.4 V

VOH2 Output High Voltage IOH = -100 µA 2.5 V

18 AT49BV162/163A(T)

3349G–FLASH–7/04

AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change

without impact on tACC.

3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

AC Read Characteristics

Symbol Parameter

AT49BV162A(T)/163A(T)-70

UnitsMin Max

tRC Read Cycle Time 70 ns

tACC Address to Output Delay 70 ns

tCE(1) CE to Output Delay 70 ns

tOE(2) OE to Output Delay 0 20 ns

tDF(3)(4) CE or OE to Output Float 0 25 ns

tOH

Output Hold from OE, CE or Address,

whichever occurred first 0ns

tRO RESET to Output Delay 100 ns

OUTPUT

VALID

OUTPUT HIGH Z

RESET

OE tOE

tCE

ADDRESS VALID

tDF

tOH

tACC

tRO

ADDRESS

tRC

AT49BV162/163A(T)

3349G–FLASH–7/04

Input Test Waveforms and Measurement Level

tR, tF < 5 ns

Output Test Load

Note: This parameter is characterized and is not 100% tested.

Pin Capacitance

f = 1 MHz, T = 25°C(1)

Symbol Typ Max Units Conditions

CIN 46pFV

IN = 0V

COUT 812pFV

OUT = 0V

20 AT49BV162/163A(T)

3349G–FLASH–7/04

AC Byte/Word Load Waveforms

WE Controlled

CE Controlled

AC Byte/Word Load Characteristics

Symbol Parameter Min Max Units

tAS, tOES Address, OE Setup Time 0 ns

tAH Address Hold Time 35 ns

tCS Chip Select Setup Time 0 ns

tCH Chip Select Hold Time 0 ns

tWP Write Pulse Width (WE or CE)35ns

tDS Data Setup Time 35 ns

tDH, tOEH Data, OE Hold Time 0 ns

tWPH Write Pulse Width High 35 ns

AT49BV162/163A(T)

3349G–FLASH–7/04

Program Cycle Waveforms

Sector or Chip Erase Cycle Waveforms

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.

(See note 3 under “Command Definitions in Hex” on page 12.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units

tBP Byte/Word Programming Time 12 200 µs

tBPD Byte/Word Programming Time in Dual Programming Mode 6 100 µs

tAS Address Setup Time 0ns

tAH Address Hold Time 35 ns

tDS Data Setup Time 35 ns

tDH Data Hold Time 0ns

tWP Write Pulse Width 35 ns

tWPH Write Pulse Width High 35 ns

tWC Write Cycle Time 70 ns

tRP Reset Pulse Width 500 ns

tEC Chip Erase Cycle Time 25 seconds

tSEC1 Sector Erase Cycle Time (4K Word Sectors) 0.3 3.0 seconds

tSEC2 Sector Erase Cycle Time (32K Word Sectors) 1.0 5.0 seconds

tES Erase Suspend Time 15 µs

tPS Program Suspend Time 10 µs

PROGRAM CYCLE

INPUT

DATA

ADDRESS

555 555

AAA

WPH

A0 - A19

DATA

555

(1)

80 Note 3

55 55

555 555 Note 2

WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5

AAA AAA

WPH

A0-A19

DATA

555

22 AT49BV162/163A(T)

3349G–FLASH–7/04

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in “AC Read Characteristics” on page 18.

Data Polling Waveforms

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in “AC Read Characteristics” on page 18.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tWR Write Recovery Time 0 ns

A0-A19

I/O7

tDH

tOEH

tOE HIGH Z

An An An An An

tWR

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tOEHP OE High Pulse 50 ns

tWR Write Recovery Time 0 ns

AT49BV162/163A(T)

3349G–FLASH–7/04

Software Product Identification Entry(1)

Software Product Identification Exit(1)(6)

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don’t

Care).

2. A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL;

Device Code is read for A0 = VIH.

3. The device does not remain in identification mode if powered

down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH(x8); 001FH(x16)

Device Code: C0H (x8) - AT49BV162A/163A;

00C0H (x16) - AT49BV162A/163A;

C2H (x8) - AT49BV162AT/163AT;

00C2H (x16) - AT49BV162AT/163AT.

6. Either one of the Product ID Exit commands can be used.

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 90

ADDRESS 555

ENTER PRODUCT

IDENTIFICATION

MODE(2)(3)(5)

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA F0

ADDRESS 555

EXIT PRODUCT

IDENTIFICATION

MODE(4)

OR LOAD DATA F0

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

MODE(4)

Sector Lockdown Enable Algorithm(1)

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), A-1, and A11 - A19

(Don’t Care).

2. Sector Lockdown feature enabled.

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 80

ADDRESS 555

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 60

SECTOR ADDRESS

PAUSE 200 µs(2)

24 AT49BV162/163A(T)

3349G–FLASH–7/04

Table 1. Common Flash Interface Definition for AT49BV162A(T)/163A(T)

Address

[x16 Mode]

Address

[x8 Mode] Data Comments

10h 20h 0051h “Q”

11h 22h 0052h “R”

12h 24h 0059h “Y”

13h 26h 0002h

14h 28h 0000h

15h 2Ah 0041h

16h 2Ch 0000h

17h 2Eh 0000h

18h 30h 0000h

19h 32h 0000h

1Ah 34h 0000h

1Bh 36h 0027h VCC min write/erase

1Ch 38h 0036h VCC max write/erase

1Dh 3Ah 00B5h VPP min voltage

1Eh 3Ch 00C5h VPP max voltage

1Fh 3Eh 0004h Typ word write – 12 µs

20h 40h 0000h

21h 42h 000Ah Typ block erase: 1,000 ms

22h 44h 0010h Typ chip erase: 25,000 ms

23h 46h 0004h Max word write/typ time

24h 48h 0000h N/A

25h 4Ah 0002h Max block erase/typ block erase

26h 4Ch 0002h Max chip erase/typ chip erase

27h 4Eh 0015h Device size

28h 50h 0002h x8/x16 device

29h 52h 0000h x8/x16 device

2Ah 54h 0000h Multiple byte write not supported

2Bh 56h 0000h Multiple byte write not supported

2Ch 58h 0002h 2 regions, X = 2

2Dh 5Ah 001Eh 64K bytes, Y = 30

2Eh 5Ch 0000h 64K bytes, Y = 30

2Fh 5Eh 0000h 64K bytes, Z = 256

30h 60h 0001h 64K bytes, Z = 256

31h 62h 0007h 8K bytes, Y = 7

32h 64h 0000h 8K bytes, Y = 7

33h 66h 0020h 8K bytes, Z = 32

34h 68h 0000h 8K bytes, Z = 32

AT49BV162/163A(T)

3349G–FLASH–7/04

Vendor Specific Extended Query

41h 82h 0050h “P”

42h 84h 0052h “R”

43h 86h 0049h “I”

44h 88h 0031h Major version number, ASCII

45h 8Ah 0030h Minor version number, ASCII

46h 8Ch 0087h Bit 0 – chip erase supported, 0 – no, 1 – yes

Bit 1 – erase suspend supported, 0 – no, 1 – yes

Bit 2 – program suspend supported, 0 – no, 1 – yes

Bit 3 – simultaneous operations supported,

0 – no, 1 – yes

Bit 4 – burst mode read supported, 0 – no, 1 – yes

Bit 5 – page mode read supported, 0 – no, 1 – yes

Bit 6 – queued erase supported, 0 – no, 1 – yes

Bit 7 – protection bits supported, 0 – no, 1 – yes

47h 8Eh 0000h (top) or

0001h (bottom)

Bit 8 – top (“0”) or bottom (“1”) boot block device undefined bits

are “0”

48h 90h 0000h Bit 0 – 4-word linear burst with wrap around,

0 – no, 1 – yes

Bit 1 – 8-word linear burst with wrap around,

0 – no, 1 – yes

Bit 2 – continuos burst, 0 – no, 1 – yes

Undefined bits are “0”

49h 92h 0000h Bit 0 – 4-word page, 0 – no, 1 – yes

Bit 1 – 8-word page, 0 – no, 1 – yes

Undefined bits are “0”

4Ah 94h 0080h Location of protection register lock byte, the section’s first byte

4Bh 96h 0003h # of bytes in the factory prog section

of prot register – 2*n

4Ch 98h 0003h # of bytes in the user prog section of prot

Table 1. Common Flash Interface Definition for AT49BV162A(T)/163A(T) (Continued)

Address

[x16 Mode]

Address

[x8 Mode] Data Comments

26 AT49BV162/163A(T)

3349G–FLASH–7/04

AT49BV162A(T) Ordering Information

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

70 25 0.025 AT49BV162A-70CI

AT49BV162A-70TI

48C19

48T

Industrial

(-40° to 85°C)

70 25 0.025 AT49BV162AT-70CI

AT 4 9 B V 1 6 2 AT- 7 0 T I

48C19

48T

Industrial

(-40° to 85°C)

AT49BV163A(T) Ordering Information

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

70 25 0.025 AT49BV163A-70TI 48T Industrial

(-40° to 85°C)

70 25 0.025 AT49BV163AT-70TI 48T Industrial

(-40° to 85°C)

Package Type

48C19 48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA)

48T 48-lead, Plastic Thin Small Outline Package (TSOP)

AT49BV162/163A(T)

3349G–FLASH–7/04

Packaging Information

48C19 – CBGA

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

48C19, 48-ball (6 x 8 Array), 0.80 mm Pitch,

6.0 x 8.0 x 1.0 mm Chip-scale Ball Grid Array Package (CBGA) A

48C19

7/2/03

Top View

Bottom View

Side View

1.0 REF

1.20 REF

A1 Ball ID

6 54321

A1 Ball Corner

Øb

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

E 5.90 6.00 6.10

E1 4.0 TYP

D 7.90 8.00 8.10

D1 5.6 TYP

A – – 1.0

A1 0.22 – –

e 0.80 BSC

Øb 0.40 TYP

28 AT49BV162/163A(T)

3349G–FLASH–7/04

48T – TSOP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP) B

48T

10/18/01

PIN 1 0º ~ 8º

D1 D

Pin 1 Identifier

GAGE PLANE

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD.

2. Dimensions D1 and E do not include mold protrusion. Allowable

protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 19.80 20.00 20.20

D1 18.30 18.40 18.50 Note 2

E 11.90 12.00 12.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.50 BASIC

Printed on recycled paper.

3349G–FLASH–7/04 /xM

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

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