CY14B108L
CY14B108N
8-Mbit (1024 K × 8/512 K × 16) nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-45523 Rev. *L Revised August 10, 2012
8-Mbit ( 1024 K × 8/ 512 K × 16) nvSRAM
Features
■20 ns, 25 ns, and 45 ns access times
■Internally organized as 1024 K × 8 (CY14B108L) or 512 K ×16
(CY14B108N)
■Hands off automatic STORE on power-down with only a small
capacitor
■STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
■RECALL to SRAM initiated by software or power-up
■Infinite Read, Write, and RECALL cycles
■1 million STORE cycles to QuantumTrap
■20 year data retention
■Single 3 V +20, –10 operation
■Industrial temperature
■Packages
❐44-/54-pin thin small outline package (TSOP) Type II
❐48-ball fine-pitch ball grid array (FBGA)
■Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B108L/CY14B108N is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 1024 Kbytes of 8 bits each or 512 K
words of 16 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
STATIC RAM
ARRAY
2048 X 2048 X 2
R
O
W
D
E
C
O
D
E
R
COLUMN I/O
COLUMN DEC
I
N
P
U
T
B
U
F
F
E
R
S
POWER
CONTROL
STORE/RECALL
CONTROL
Quatrum Trap
2048 X 2048 X 2
STORE
RECALL
V
CC
V
CAP
HSB
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
SOFTWARE
DETECT A
14
- A
2
OE
CE
WE
BHE
BLE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
A
18
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
A
19
Logic Block Diagram [1, 2, 3]
Notes
1. Address A0–A19 for × 8 configuration and Address A0–A18 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 2 of 26
Contents
Pinouts ..............................................................................3
Pin Definitions .................................................................. 4
Device Operation .............................................................. 5
SRAM Read ................................................................5
SRAM Write ................................................................. 5
AutoStore Operation ....................................................5
Hardware STORE Operation .......................................5
Hardware RECALL (Power-Up) ..................................6
Software STORE .........................................................6
Software RECALL .......................................................6
Preventing AutoStore ..................................................8
Data Protection ............................................................8
Maximum Ratings .............................................................9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................10
AC Test Loads ................................................................11
AC Test Conditions ........................................................11
AC Switching Characteristics ....................................... 12
Switching Waveforms .................................................... 12
AutoStore/Power-Up RECALL ....................................... 15
Switching Waveforms .................................................... 15
Software Controlled STORE/RECALL Cycle ................ 16
Switching Waveforms .................................................... 16
Hardware STORE Cycle ................................................. 17
Switching Waveforms .................................................... 17
Truth Table For SRAM Operations ................................ 18
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC Solutions ......................................................... 26
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 3 of 26
Pinouts
Figure 1. Pin Diagram – 48-ball FBGA
Figure 2. Pin Diagram – 44/54-pin TSOP II
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
NC
DQ
0
A
4
A
5
NC
DQ
2
DQ
3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC
NC
NC
A
17
A
2
A
1
NC
V
CC
DQ
4
NC
DQ
5
DQ
6
NC DQ
7
NC
A
15
A
14
A
13
A
12
HSB
3
26
5
4
1
D
E
B
A
C
F
G
H
A
16
A
18
A
19
DQ
1
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
DQ
10
DQ
8
DQ
9
A
4
A
5
DQ
13
DQ
12
DQ
14
DQ
15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ
0
BHE
NC
A
17
A
2
A
1
BLE
V
CC
DQ
2
DQ
1
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
15
A
14
A
13
A
12
HSB
3
26
5
4
1
D
E
B
A
C
F
G
H
A
16
A
18
NC
DQ
11
(not to scale)
Top View
(
×
16)
(not to scale)
Top View
(
×
8)
NC
A
8
NC
NC
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
A
17
A
18
A
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Top View
(not to scale)
A
10
NC
WE
DQ
7
HSB
NC
V
SS
V
CC
V
CAP
NC
[4]
54-pin TSOP II
(× 16)
44-pin TSOP II
(× 8)
A
17
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
DQ
3
DQ
2
DQ
1
DQ
0
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CAP
WE
A
8
A
10
A
11
A
12
A
13
A
14
A
15
A
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Top View
(not to scale)
OE
CE
V
CC
NC
V
SS
NC
A
9
NC
NC
A
18
NC
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
[4]
Note
4. Address expansion for 16-Mbit. NC pin not connected to die.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 4 of 26
Pin Definitions
Pin Name I/O Type Description
A0–A19 Input Address inputs. Used to select one of the 1,048,576 bytes of the nvSRAM for × 8 configuration.
A0–A18 Address inputs. Used to select one of the 524,288 words of the nvSRAM for × 16 configuration.
DQ0–DQ7Input/Output Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
DQ0–DQ15 Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation.
WE Input Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
BHE Input Byte High Enable, Active LOW. Controls DQ15–DQ8.
BLE Input Byte Low Enable, Active LOW. Controls DQ7–DQ0.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VCC Power supply Power supply inputs to the device.
HSB Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor
connection optional).
VCAP Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC No connect No connect. This pin is not connected to the die.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 5 of 26
Device Operation
The CY14B108L/CY14B108N nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B108L/CY14B108N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See Truth Table For SRAM Operations on page 18
for a complete description of read and write modes.
SRAM Read
The CY14B108L/CY14B108N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0–19 or A0–18 determines which of the
1,048,576 data bytes or 524,288 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
delay of tAA (read cycle 1). If the read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (read
cycle 2). The data output repeatedly responds to address
changes within the tAA access time without the need for
transitions on any control input pins. This remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B108L/CY14B108N stores data to the nvSRAM using
one of the following three storage operations: Hardware STORE
activated by the HSB; Software STORE activated by an address
sequence; AutoStore on device power-down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B108L/CY14B108N.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 8. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 9 for the size of VCAP
. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 3. AutoStore Mode
Hardware STORE Operation
The CY14B108L/CY14B108N provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B108L/CY14B108N conditionally initiates a
STORE operation after tDELAY
. An actual STORE cycle only
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is inter-
nally driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
0.1 uF
VCC
10 kOhm
VCAP
WE VCAP
VSS
VCC
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 6 of 26
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B108L/CY14B108N. But any SRAM read and
write cycles are inhibited until HSB is returned HIGH by MPU or
other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B108L/CY14B108N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC<V
SWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on power-up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B108L/CY14B108N
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared; then, the nonvolatile information is transferred
into the SRAM cells. After the tRECALL cycle time, the SRAM is
again ready for read and write operations. The RECALL
operation does not alter the data in the nonvolatile elements.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 7 of 26
Table 1. Mode Selection
CE WE OE BHE, BLE[5] A15–A0[6] Mode I/O Power
H X X X X Not Selected Output High Z Standby
L H L L X Read SRAM Output data Active
L L X L X Write SRAM Input data Active
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output data
Output data
Output data
Output data
Output data
Output data
Active[7]
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output data
Output data
Output data
Output data
Output data
Output data
Active[7]
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output data
Output data
Output data
Output data
Output data
Output High Z
Active ICC2[7]
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output data
Output data
Output data
Output data
Output data
Output High Z
Active[7]
Notes
5. BHE and BLE are applicable for × 16 configuration only.
6. While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A14–A2) are used to control software modes.
Rest of the address lines are don’t care.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 8 of 26
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power-down
cycles. The part comes from the factory with AutoStore enabled
and 0x00 written in all cells.
Data Protection
The CY14B108L/CY14B108N protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14B108L/CY14B108N
is in a write mode (both CE and WE are LOW) at power-up, after
a RECALL or STORE, the write is inhibited until the SRAM is
enabled after tLZHSB (HSB to output active). This protects against
inadvertent writes during power-up or brown out conditions.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 9 of 26
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
At 150 C ambient temperature ...................... 1000 h
At 85 C ambient temperature ..................... 20 Years
Maximum junction temperature .................................. 150 C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VCC + 0.5 V
Input voltage ........................................–0.5 V to Vcc + 0.5 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 Seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch up current .................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40 C to +85 C 2.7 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [8] Max Unit
VCC Power supply 2.7 3.0 3.6 V
ICC1 Average VCC current tRC = 20 ns
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads
(IOUT = 0 mA)
––75
75
57
mA
mA
mA
ICC2 Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
––20mA
ICC3 Average VCC current at
tRC= 200 ns, VCC(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
–40–mA
ICC4 Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current
for duration tSTORE
––10mA
ISB VCC standby current CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after
nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
––10mA
IIX[9] Input leakage current (except
HSB)
VCC = Max, VSS < VIN < VCC –2 – +2 A
Input leakage current (for HSB)V
CC = Max, VSS < VIN < VCC –200 – +2 A
IOZ Off-state output leakage current VCC = Max, VSS < VOUT < VCC,
CE or OE > VIH or
BHE/BLE > VIH or WE < VIL
–2 – +2 A
VIH Input HIGH voltage 2.0 – VCC + 0.5 V
VIL Input LOW voltage Vss – 0.5 – 0.8 V
VOH Output HIGH voltage IOUT = –2 mA 2.4 – – V
VOL Output LOW voltage IOUT = 4 mA – – 0.4 V
Notes
8. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested.
9. The HSB pin has IOUT = –2 µA for VOH of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
CY14B108L
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Document Number: 001-45523 Rev. *L Page 10 of 26
VCAP[10] Storage capacitor Between VCAP pin and VSS 122 150 360 F
VVCAP[11, 12] Maximum voltage driven on VCAP
pin by the device
VCC = Max – – VCC V
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter Description Test Conditions Min Typ [8] Max Unit
Data Retention and Endurance
Over the Operating Range
Parameter Description Min Unit
DATARData retention 20 Years
NVCNonvolatile STORE operations 1,000 K
Capacitance
Parameter [12] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = VCC(Typ) 14 pF
COUT Output capacitance 14 pF
Thermal Resistance
Parameter [12] Description Test Conditions 48-ball FBGA 44-pin TSOP II 54-pin TSOP II Unit
JA Thermal resistance
(Junction to ambient)
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, in
accordance with
EIA/JESD51.
42.2 45.3 44.22 C/W
JC Thermal resistance
(Junction to case)
6.3 5.2 8.26 C/W
Notes
10. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on
VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options.
11. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating
temperature range should be higher than the VVCAP voltage.
12. These parameters are guaranteed by design and are not tested.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 11 of 26
AC Test Conditions
Input pulse levels ..................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels ...................... 1.5 V
AC Test Loads
Figure 4. AC Test Loads
3.0 V
OUTPUT
5 pF
R1
R2
789
3.0 V
OUTPUT
30 pF
R1
R2
789
for tristate specs
577 577
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 12 of 26
AC Switching Characteristics
Over the Operating Range
Parameters [13]
Description
20 ns 25 ns 45 ns
Unit
Cypress
Parameter Alt Parameter Min Max Min Max Min Max
SRAM Read Cycle
tACE tACS Chip enable access time –20–25–45ns
tRC[14] tRC Read cycle time 20 – 25 – 45 – ns
tAA[15] tAA Address access time – 20 – 25 – 45 ns
tDOE tOE Output enable to data valid – 10 – 12 – 20 ns
tOHA[15] tOH Output hold after address change 3–3–3–ns
tLZCE[16, 17] tLZ Chip enable to output active 3–3–3–ns
tHZCE[16, 17] tHZ Chip disable to output inactive – 8 – 10 – 15 ns
tLZOE[16, 17] tOLZ Output enable to output active 0–0–0–ns
tHZOE[16, 17] tOHZ Output disable to output inactive – 8 – 10 – 15 ns
tPU[16] tPA Chip enable to power active 0–0–0–ns
tPD[16] tPS Chip disable to power standby – 20 – 25 – 45 ns
tDBE – Byte enable to data valid – 10 – 12 – 20 ns
tLZBE[16] – Byte enable to output active 0–0–0–ns
tHZBE[16] – Byte disable to output inactive – 8 – 10 – 15 ns
SRAM Write Cycle
tWC tWC Write cycle time 20–25–45–ns
tPWE tWP Write pulse width 15–20–30–ns
tSCE tCW Chip enable to end of write 15 – 20 – 30 – ns
tSD tDW Data setup to end of write 8 –10–15–ns
tHD tDH Data hold after end of write 0–0–0–ns
tAW tAW Address setup to end of write 15 – 20 – 30 – ns
tSA tAS Address setup to start of write 0–0–0–ns
tHA tWR Address hold after end of write 0–0–0–ns
tHZWE[16, 17, 18] tWZ Write enable to output disable – 8 10 – 15 ns
tLZWE[16, 17] tOW Output active after end of write 3–3–3–ns
tBW – Byte enable to end of write 15 – 20 – 30 – ns
Switching Waveforms
Figure 5. SRAM Read Cycle #1 (Address Controlled) [14, 15, 19]
Address
Data Output
Address Valid
Previous Data Valid Output Data Valid
tRC
tAA
tOHA
Notes
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 4 on page 11.
14. WE must be HIGH during SRAM read cycles.
15. Device is continuously selected with CE, OE and BHE / BLE LOW.
16. These parameters are guaranteed by design but not tested.
17. Measured ±200 mV from steady state output voltage.
18. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
19. HSB must remain HIGH during READ and WRITE cycles.
CY14B108L
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Document Number: 001-45523 Rev. *L Page 13 of 26
Figure 6. SRAM Read Cycle #2 (CE and OE Controlled) [20, 21, 22]
Figure 7. SRAM Write Cycle #1 (WE Controlled) [20, 22, 23, 24]
Switching Waveforms (continued)
Address ValidAddress
Data Output Output Data Valid
Standby Active
High Impedance
CE
OE
BHE, BLE
ICC
tHZCE
tRC
tACE
tAA
tLZCE
tDOE
tLZOE
tDBE
tLZBE
tPU tPD
tHZBE
tHZOE
Data Output
Data Input Input Data Valid
High Impedance
Address ValidAddress
Previous Data
tWC
tSCE tHA
tBW
tAW
tPWE
tSA
tSD tHD
tHZWE tLZWE
WE
BHE, BLE
CE
Notes
20. BHE and BLE are applicable for × 16 configuration only.
21. WE must be HIGH during SRAM read cycles.
22. HSB must remain HIGH during READ and WRITE cycles.
23. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
24. CE or WE must be >VIH during address transitions.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 14 of 26
Figure 8. SRAM Write Cycle #2 (CE Controlled) [25, 26, 27, 28]
Figure 9. SRAM Write Cycle #3 (BHE and BLE Controlled) [25, 26, 27, 28]
Switching Waveforms (continued)
Data Output
Data Input Input Data Valid
High Impedance
Address Valid
Address
tWC
tSD tHD
BHE, BLE
WE
CE
tSA tSCE tHA
tBW
tPWE
Data Output
Data Input Input Data Valid
High Impedance
Address ValidAddress
tWC
tSD tHD
BHE, BLE
WE
CE
tSCE
tSA tBW tHA
tAW
tPWE
Notes
25. BHE and BLE are applicable for × 16 configuration only.
26. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
27. HSB must remain HIGH during READ and WRITE cycles.
28. CE or WE must be >VIH during address transitions.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 15 of 26
AutoStore/Power-Up RECALL
Over the Operating Range
Parameter Description 20 ns 25 ns 45 ns Unit
Min Max Min Max Min Max
tHRECALL[29] Power-Up RECALL duration – 20 – 20 – 20 ms
tSTORE [30] STORE cycle duration – 8 – 8 – 8 ms
tDELAY [31] Time allowed to complete SRAM
write cycle
–20–25–25ns
VSWITCH Low voltage trigger level – 2.65 – 2.65 – 2.65 V
tVCCRISE[32] VCC rise time 150 – 150 – 150 – s
VHDIS[32] HSB output disable voltage – 1.9 – 1.9 – 1.9 V
tLZHSB[32] HSB to output active time – 5 – 5 – 5 s
tHHHD[32] HSB high active time – 500 – 500 – 500 ns
Switching Waveforms
Figure 10. AutoStore or Power-Up RECALL [33]
VSWITCH
VHDIS
tVCCRISE tSTORE tSTORE
tHHHD
tHHHD
tDELAY
tDELAY
tLZHSB tLZHSB
tHRECALL
tHRECALL
HSB OUT
AutoStore
POWER-
UP
RECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write POWER
DOWN
AutoStore
Note Note
Note
Note
VCC
30 30
34
34
Notes
29. tHRECALL starts from the time VCC rises above VSWITCH.
30. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
31. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY
.
32. These parameters are guaranteed by design but not tested.
33. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
34. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 16 of 26
Software Controlled STORE/RECALL Cycle
Over the Operating Range
Parameter [35, 36] Description 20 ns 25 ns 45 ns Unit
Min Max Min Max Min Max
tRC STORE/RECALL initiation cycle time 20 – 25 – 45 – ns
tSA Address setup time 0 – 0 – 0 – ns
tCW Clock pulse width 15–20–30–ns
tHA Address hold time 0 – 0 – 0 – ns
tRECALL RECALL duration – 200 – 200 – 200 s
Switching Waveforms
Figure 11. CE and OE Controlled Software STORE/RECALL Cycle [36]
Figure 12. Autostore Enable/Disable Cycle [36]
tRC tRC
tSA tCW
tCW
tSA
tHA
tLZCE
tHZCE
tHA
tHA
tHA
tSTORE/tRECALL
tHHHD
tLZHSB
High Impedance
Address #1 Address #6Address
CE
OE
HSB (STORE only)
DQ (DATA)
RWI
tDELAY Note
37
tRC tRC
tSA tCW
tCW
tSA
tHA
tLZCE
tHZCE
tHA
tHA
tHA
tDELAY
Address #1 Address #6Address
CE
OE
DQ (DATA)
tSS
Note
RWI
37
Notes
35. The software sequence is clocked with CE controlled or OE controlled reads.
36. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles.
37. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 17 of 26
Hardware STORE Cycle
Over the Operating Range
Parameter Description 20 ns 25 ns 45 ns Unit
Min Max Min Max Min Max
tDHSB HSB to output active time when
write latch not set
–20–25–25ns
tPHSB Hardware STORE pulse width 15 – 15 – 15 – ns
tSS [38, 39] Soft sequence processing time – 100 – 100 – 100 s
Switching Waveforms
Figure 13. Hardware STORE Cycle [40]
Figure 14. Soft Sequence Processing [38, 39]
tPHSB
tPHSB
tDELAY tDHSB
tDELAY
tSTORE
tHHHD
tLZHSB
Write latch set
Write latch not set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
HSB (IN)
HSB (OUT)
RWI
HSB pin is driven high to VCC
only by Internal
SRAM is disabled as long as HSB (IN) is driven low
.
HSB driver is disabled
tDHSB
100 kOhm resistor,
Address #1 Address #6 Address #1 Address #6
Soft Sequence
Command
tSS tSS
CE
Address
VCC
tSA tCW
Soft Sequence
Command
tCW
Notes
38. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
39. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
40. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
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Document Number: 001-45523 Rev. *L Page 18 of 26
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
Table 2. Truth Table for × 8 Configuration
CE WE OE Inputs/Outputs[41] Mode Power
H X X High Z Deselect/Power-down Standby
L H L Data out (DQ0–DQ7); Read Active
L H H High Z Output disabled Active
L L X Data in (DQ0–DQ7); Write Active
Table 3. Truth Table for × 16 Configuration
CE WE OE BHE[42] BLE[42] Inputs/Outputs[41] Mode Power
H X X X X High Z Deselect/Power-down Standby
L X X H H High Z Output disabled Active
LHLLLData out (DQ
0–DQ15) Read Active
L H L H L Data out (DQ0–DQ7);
DQ8–DQ15 in High Z
Read Active
L H L L H Data out (DQ8–DQ15);
DQ0–DQ7 in High Z
Read Active
L H H L L High Z Output disabled Active
L H H H L High Z Output disabled Active
L H H L H High Z Output disabled Active
LLXLLData in (DQ
0–DQ15) Write Active
LLXHLData in (DQ
0–DQ7);
DQ8–DQ15 in High Z
Write Active
LLXLHData in (DQ
8–DQ15);
DQ0–DQ7 in High Z
Write Active
Notes
41. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
42. BHE and BLE are applicable for × 16 configuration only.
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 19 of 26
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
20 CY14B108L-ZS20XIT 51-85087 44-pin TSOP II Industrial
CY14B108L-ZS20XI 51-85087 44-pin TSOP II
25 CY14B108L-ZS25XIT 51-85087 44-pin TSOP II
CY14B108L-ZS25XI 51-85087 44-pin TSOP II
CY14B108L-BA25XIT 51-85128 48-ball FBGA
CY14B108L-BA25XI 51-85128 48-ball FBGA
CY14B108N-BA25XIT 51-85128 48-ball FBGA
CY14B108N-BA25XI 51-85128 48-ball FBGA
CY14B108N-ZSP25XIT 51-85160 54-pin TSOP II
CY14B108N-ZSP25XI 51-85160 54-pin TSOP II
45 CY14B108L-ZS45XIT 51-85087 44-pin TSOP II
CY14B108L-ZS45XI 51-85087 44-pin TSOP II
CY14B108L-BA45XIT 51-85128 48-ball FBGA
CY14B108L-BA45XI 51-85128 48-ball FBGA
CY14B108N-BA45XIT 51-85128 48-ball FBGA
CY14B108N-BA45XI 51-85128 48-ball FBGA
CY14B108N-ZSP45XIT 51-85160 54-pin TSOP II
CY14B108N-ZSP45XI 51-85160 54-pin TSOP II
All the above parts are Pb-free.
Option:
T - Tape & Reel
Blank - Std.
Speed:
20 - 20 ns
25 - 25 ns
Data Bus:
L - × 8
N - × 16 Density:
108 - 8 Mb
Voltage:
B - 3.0 V
Cypress
CY 14 B 108 L - ZS 20 X I T
NVSRAM14 -
Temperature:
I - Industrial (–40 to 85 °C)
Pb-Free
Package:
BA - 48-ball FBGA
ZS - 44-pin TSOP II
45 - 45 ns
ZSP - 54-pin TSOP II
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 20 of 26
Package Diagrams
Figure 15. 44-pin TSOP II Package Outline, 51-85087
51-85087 *D
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 21 of 26
Figure 16. 48-ball FBGA (6 × 10 × 1.2 mm) Package Outline, 51-85128
Package Diagrams (continued)
51-85128 *F
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 22 of 26
Figure 17. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Package Outline, 51-85160
Package Diagrams (continued)
51-85160 *D
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 23 of 26
Acronyms Document Conventions
Units of Measure
Acronym Description
CMOS complementary metal oxide semiconductor
BHE byte high enable
BLE byte low enable
CE chip enable
EIA electronic industries alliance
FBGA fine-pitch ball grid array
HSB hardware store busy
I/O input/output
nvSRAM non-volatile static random access memory
OE output enable
RoHS restriction of hazardous substances
RWI read and write inhibited
SRAM static random access memory
TSOP thin small outline package
WE write enable
Symbol Unit of Measure
°C degree Celsius
kkilohm
kHz kilohertz
MHz megahertz
Amicroampere
Fmicrofarad
smicrosecond
mA milliampere
ms millisecond
ns nanosecond
ohm
%percent
pF picofarad
ssecond
Vvolt
Wwatt
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 24 of 26
Document History Page
Document Title: CY14B108L/CY14B108N, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM
Document Number: 001-45523
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 2428826 GVCH See ECN New Data Sheet
*A 2520023 GVCH /
PYRS
06/23/08 Updated ICC1 for tRC=20ns, 25ns and 45ns access speed for both industrial
and Commercial temperature Grade
Updated Thermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP II
packages
Changed tCW value from 16ns to 15ns
*B 2676670 GVCH /
PYRS
03/20/2009 Added maximum accumulated storage time for 150C and 85C Temperature
Added best practices
Changed ICC2 from 12mA to 20mA
Changed ICC3 from 38mA to 40mA
Changed ICC4 from 12mA to 10mA
Changed ISB from 6mA to 10mA
Changed VCAP from 164uF to 360uF
Changed Input Rise and Fall Times from 5ns to 3ns
Updated ICC1, ICC3, ISBand IOZ Test conditions
Changed tDELAY to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively
Changed tSTORE from 15ms to 8ms
Added VHDIS, tHHHD and tLZHSB parameters
Software controlled STORE/RECALL cycle table: Changed tAS to tSA
Changed tGHAX to tHA
Added tDHSB parameter
Changed tHLHX to tPHSB
Updated tSS from 70us to 100us
Added Truth table for SRAM operations
Updated ordering information
*C 2712462 GVCH /
PYRS
05/29/2009 Moved data sheet status from Preliminary to Final
Updated AutoStore operation
Updated ISB test condition
Updated footnote 7
Referenced footnote 9 to VCCRISE, tHHHD and tLZHSB parameters
Updated VHDIS parameter description
*D 2746310 GVCH 07/29/2009 Page 4: Updated Hardware STORE (HSB) operation description
page 5: Updated Software STORE description
Updated tDELAY parameter description
Updated footnote 18 and added footnote 23
Referenced footnote 23 to Figure 11 and Figure 12
*E 2759948 GVCH 09/04/2009 Removed commercial temperature related specs
*F 2828257 GVCH 12/15/2009 Changed STORE cycles to QuantumTrap from 200K to 1 Million
Added Contents on page 2
*G 2894560 GVCH 03/18/2010 Removed part numbers CY14B108N-ZSP20XIT and CY14B108N-ZSP20XI
from ordering information table.
Updated Package diagrams 51-85160 and 51-85087.
Updated Sales, Solution, and Legal Information Section.
Updated copyright section.
Updated table of contents.
*H 2923475 GVCH /
AESA
04/27/2010 Table 1: Added more clarity on HSB pin operation
Hardware STORE Operation: Added more clarity on HSB pin operation
Table 1: Added more clarity on BHE/BLE pin operation
Updated HSB pin operation in Figure 10
Updated footnote 34
CY14B108L
CY14B108N
Document Number: 001-45523 Rev. *L Page 25 of 26
*I 3143765 GVCH 01/17/2011 48-ball FBGA package: 16 Mb address expansion is not supported
Updated thermal resistance values for all packages
Added Acronyms table and Document Conventions table
*J 3311413 GVCH 07/13/2011 Updated DC Electrical Characteristics (Added Note 9 and referred the same
note in VCAP parameter).
Updated AC Switching Characteristics (Added Note 13 and referred the same
note in Parameters).
Updated Package Diagrams.
*K 3580269 GVCH 04/12/2012 Updated Package Diagrams.
*L 3658005 GVCH 08/10/2012 Updated Maximum Ratings (Changed “Ambient temperature with power
applied” to “Maximum junction temperature”).
Updated DC Electrical Characteristics (Added VVCAP parameter and its
details, added Note 11 and referred the same note in VVCAP parameter, also
referred Note 12 in VVCAP parameter).
Updated Package Diagrams (spec 51-85160 (Changed revision from *C to
*D)).
Document History Page (continued)
Document Title: CY14B108L/CY14B108N, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM
Document Number: 001-45523
Revision ECN Orig. of
Change
Submission
Date Description of Change
Document Number: 001-45523 Rev. *L Revised August 10, 2012 Page 26 of 26
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY14B108L
CY14B108N
© Cypress Semiconductor Corporation, 2008-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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