LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs Check for Samples: LMK04000, LMK04001, LMK04002, LMK04010, LMK04011, LMK04031, LMK04033 FEATURES 1 * 23 * * Cascaded PLLatinumTM PLL Architecture - PLL1 - Phase Detector Rate of up to 40 MHz - Integrated Low-Noise Crystal Oscillator Circuit - Dual Redundant Input Reference Clock with LOS - PLL2 - Normalized [1 Hz] PLL Noise Floor of 224 dBc/Hz - Phase Detector Rate up to 100 MHz - Input Frequency-Doubler - Integrated Low-Noise VCO Ultra-Low RMS Jitter Performance - 150 fs RMS Jitter (12 kHz - 20 MHz) - 200 fs RMS Jitter (100 Hz - 20 MHz) LVPECL/2VPECL, LVDS, and LVCMOS outputs * * * * * * * Support Clock Rates up to 1080 MHz Default Clock Output (CLKout2) at power up Five Dedicated Channel Divider and Delay Blocks Pin Compatible Family of Clocking Devices Industrial Temperature Range: -40 to 85 C 3.15 V to 3.45 V Operation Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm) APPLICATIONS * * * * * * * Data Converter Clocking Wireless Infrastructure Networking, SONET/SDH, DSLAM Medical Military / Aerospace Test and Measurement Video DESCRIPTION The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinumTM architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance. The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a lownoise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1. The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PLLatinum is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2011, Texas Instruments Incorporated LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Crystal or VCXO Recovered GLUW\ FORFN RU clean clock CLKin0 CLKin1 CLKout0 Serializer/ Deserializer LMK040xx CLKout1 Precision Clock Conditioner CLKout2A LMX2531 CLKout4 PLL+VCO FPGA Fout Backup Reference Clock > 1 Gsps ADC 0XOWLSOH FOHDQ FORFNV DW different frequencies DAC Table 1. Device Configuration Information 2 NSID PROCESS 2VPECL / LVPECL OUTPUTS LMK04000BISQ BiCMOS LMK04001BISQ BiCMOS LMK04002BISQ LMK04010BISQ LVDS OUTPUTS LVCMOS OUTPUTS VCO 3 4 1185 to 1296 MHz 3 4 1430 to 1570 MHz BiCMOS 3 4 1600 to 1750 MHz BiCMOS 5 LMK04011BISQ BiCMOS 5 LMK04031BISQ BiCMOS 2 2 2 1430 to 1570 MHz LMK04033BISQ BiCMOS 2 2 2 1840 to 2160 MHz 1185 to 1296 MHz 1430 to 1570 MHz NSID CLKout0 CLKout1 CLKout2 CLKout3 CLKout4 LMK04000BISQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL LMK04001BISQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL LMK04002BISQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL LMK04010BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL LMK04011BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL LMK04031BISQ LVDS 2VPECL / LVPECL LVCMOS x 2 2VPECL / LVPECL LVDS LMK04033BISQ LVDS 2VPECL / LVPECL LVCMOS x 2 2VPECL / LVPECL LVDS Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 CPout1 Functional Block Diagram LOS CLKin0 CLKin0* Mux CLKin1 CLKin1* R1 Divider Phase Detector PLL1 N1 Divider CPout2 LOS0 LOS LOS1 2X Mux OSCin OSCin* R2 Divider N2 Divider Partially Integrated Loop Filter Internal VCO Phase Detector PLL2 Fout VCO Divider Distribution Path Divider Mux Delay GOE Device Control SYNC* LD CLKout4* CLKout3B Divider Mux Delay CLKout3A CLKout2B CLK DATA CLKout4 PWire Port Divider Control Registers Mux Delay CLKout2A LE CLKout1 Divider Mux Delay CLKout1* CLKout0 Divider Mux Delay CLKout0* Clock Buffers Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 3 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com CLKout4* CLKout4 Vcc14 CLKout3* CLKout3 Vcc13 CLKout2* CLKout2 Vcc12 CLKout1* CLKout1 Vcc11 Connection Diagram 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 36 Bias Fout 2 35 CLKin1_LOS Vcc1 3 34 CLKin0_LOS CLKuWire 4 33 Vcc10 DATAuWire 5 32 CPout2 LEuWire 6 31 Vcc9 NC 7 30 Vcc8 Vcc2 8 29 OSCin* LDObyp1 9 28 OSCin LDObyp2 10 27 SYNC* 26 CLKin1* 25 CLKin1 20 21 22 23 24 Vcc7 19 CPout1 18 Vcc6 17 CLKin0* 16 CLKin0 15 Vcc5 14 Vcc4 Vcc3 13 GND 12 DLD_BYP LD CLKout0* 11 CLKout0 GOE DAP Figure 1. 48-Pin WQFN Package Top View PIN DESCRIPTIONS 4 Pin Number Name(s) 1 GND 2 Fout I/O Type Description GND Ground (For Fout Buffer) O ANLG VCO Frequency Output Port PWR Power Supply for VCO Output Buffer 3 VCC1 4 CLKuWire I CMOS Microwire Clock Input 5 DATAuWire I CMOS Microwire Data Input 6 LEuWire I CMOS Microwire Latch Enable Input 7 NC 8 VCC2 PWR Power Supply for VCO No Connection 9 LDObyp1 ANLG LDO Bypass, bypassed to ground with a 10 F capacitor 10 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1 F capacitor 11 GOE I CMOS Global Output Enable 12 LD O CMOS Lock Detect and PLL multiplexer Output 13 VCC3 14 CLKout0 O LVDS/LVPECL Clock Channel 0 Output 15 CLKout0* O LVDS/LVPECL Clock Channel 0* Output 16 DLD_BYP ANLG DLD Bypass, bypassed to ground with a 0.47 F capacitor 17 GND GND Ground (Digital) 18 VCC4 PWR Power Supply for Digital Submit Documentation Feedback PWR Power Supply for CLKout0 Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 PIN DESCRIPTIONS (continued) (1) Pin Number Name(s) 19 VCC5 20 CLKin0 21 CLKin0* 22 VCC6 23 CPout1 I/O Type Description PWR Power Supply for CLKin buffers and PLL1 R-divider I ANLG Reference Clock Input Port for PLL1 - AC or DC Coupled (1) I ANLG Reference Clock Input Port for PLL1 (complimentary) AC or DC Coupled (1) PWR Power Supply for PLL1 Phase Detector and Charge Pump O ANLG Charge Pump1 Output 24 VCC7 PWR Power Supply for PLL1 N-Divider 25 CLKin1 I ANLG Reference Clock Input Port for PLL1 - AC or DC Coupled (1) 26 CLKin1* I ANLG Reference Clock Input Port for PLL1 (complimentary) AC or DC Coupled (1) 27 SYNC* I CMOS Global Clock Output Synchronization 28 OSCin I ANLG Reference oscillator Input for PLL2 - AC Coupled 29 OSCin* I ANLG Reference oscillator Input for PLL2 - AC Coupled 30 VCC8 PWR Power Supply for OSCin Buffer and PLL2 R-Divider 31 VCC9 PWR Power Supply for PLL2 Phase Detector and Charge Pump 32 CPout2 ANLG Charge Pump2 Output 33 VCC10 PWR Power Supply for VCO Divider and PLL2 N-Divider 34 CLKin0_LOS O LVCMOS Status of CLKin0 reference clock input 35 CLKin1_LOS O LVCMOS Status of CLKin1 reference clock input 36 Bias I ANLG Bias Bypass. AC coupled with 1 F capacitor to Vcc1 37 VCC11 PWR Power Supply for CLKout1 O 38 CLKout1 O LVPECL/LVCMOS Clock Channel 1 Output 39 CLKout1* O LVPECL/LVCMOS Clock Channel 1* Output 40 VCC12 PWR Power Supply for CLKout2 41 CLKout2 O LVPECL/LVCMOS Clock Channel 2 Output 42 CLKout2* O LVPECL/LVCMOS Clock Channel 2* Output 43 VCC13 44 CLKout3 O LVPECL Clock Channel 3 Output 45 CLKout3* O LVPECL Clock Channel 3* Output 46 VCC14 47 CLKout4 O LVDS/LVPECL Clock Channel 4 Output 48 CLKout4* O LVDS/LVPECL Clock Channel 4* Output DAP DAP PWR PWR Power Supply for CLKout3 Power Supply for CLKout4 DIE ATTACH PAD, connect to GND The reference clock inputs may be either AC or DC coupled. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 5 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Absolute Maximum Ratings (1) (2) (3) (4) Parameter Symbol Ratings Units VCC -0.3 to 3.6 V VIN -0.3 to (VCC + 0.3) V TSTG -65 to 150 C Lead Temperature (solder 4 sec) TL +260 C Differential Input Current (CLKinX/X*, OSCin/OSCin*) IIN 5 mA Supply Voltage (5) Input Voltage Storage Temperature Range (1) (2) (3) (4) (5) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only to the test conditions listed. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. This device is a high performance RF integrated circuit with an ESD rating up to 8 KV Human Body Model, up to 300 V Machine Model and up to 1,250 V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations. Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Never to exceed 3.6 V. Package Thermal Resistance JA J-PAD (Thermal Pad) 27.4 C/W 5.8 C/W Package 48-Lead WQFN (1) (1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in the board layout. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Symbol Condition Min Typical Max Unit TA VCC = 3.3 V -40 25 85 C 3.15 3.3 3.45 V VCC Electrical Characteristics (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Conditions Min Typ Max Units 1 mA Current Consumption ICC_PD Power Down Supply Current LMK04000, LMK04001, LMK04002 (2) ICC_CLKS Supply Current with all clocks enabled, all delay bypassed, Fout disabled. (1) LMK04010, LMK04011 (2) LMK04031, LMK04033 (2) 380 435 378 435 335 385 mA CLKin0/0* and CLKin1/1* Input Clock Specifications fCLKin (1) (2) (3) 6 Clock Input Frequency (3) Manual Select mode 0.001 400 Auto-Switching mode 1 400 MHz Load conditions for output clocks: LVPECL: 50 to VCC-2 V. 2VPECL: 50 to VCC-2.36 V. LVDS: 100 differential. LVCMOS: 10 pF. Additional test conditions for ICC limits: All clock delays disabled, CLKoutX_DIV = 510, PLL1 and PLL2 locked. (See Table 33 for more information) CLKin0 and CLKin1 maximum of 400 MHz is guaranteed by characterization, production tested at 200 MHz. Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Slew Rate on CLKin SLEWCLKin VCLKin (Bipolar input buffer mode) VCLKin-offset (Bipolar input buffer mode) VCLKin (MOS input buffer mode) VCLKin-VIH (MOS input buffer mode) Min Typ 0.5 Max Units (4) 20% to 80% 0.15 Input Voltage Swing, single-ended input AC coupled to CLKinX; CLKinX* AC coupled to Ground (CLKinX_TYPE=0) 0.25 2.0 Vpp Input Voltage Swing, differential input CLKinX and CLKinX* are both driven, AC coupled. (CLKinX_TYPE=0) 0.5 3.1 Vpp DC offset voltage between CLKinX/CLKinX* |CLKinX-CLKinX*| Each pin AC coupled (CLKinX_TYPE=0) Input Voltage Swing, singleended input AC coupled to CLKinX; CLKinX* AC coupled to Ground (CLKinX_TYPE=1) 0.25 2.0 Vpp Input Voltage Swing, differential input CLKinX and CLKinX* are both driven, AC coupled. (CLKinX_TYPE=1) 0.5 3.1 Vpp Maximum input voltage DC coupled to CLKinX; CLKinX* AC coupled to Ground (CLKinX_TYPE=1) 2.0 VCC V DC coupled to CLKinX; CLKinX* AC coupled to Ground (CLKinX_TYPE=1) 0.0 0.4 V VCLKin-VIL (MOS input buffer mode) VCLKin-offset (MOS input buffer mode) Conditions DC offset voltage between CLKinX/CLKinX* |CLKinX-CLKinX*| Each pin AC coupled (CLKinX_TYPE=1) V/ns 44 mV 294 mV PLL1 Specifications PLL1 Phase Detector Frequency fPD ICPout1 SOURCE (4) (5) PLL1 Charge Pump Source Current (5) 40 VCPout1 = VCC/2, PLL1_CP_GAIN = 100b 25 VCPout1 = VCC/2, PLL1_CP_GAIN = 101b 50 VCPout1 = VCC/2, PLL1_CP_GAIN = 110b 100 VCPout1 = VCC/2, PLL1_CP_GAIN = 111b 400 PLL1_CP_GAIN = 000b NA PLL1_CP_GAIN = 001b NA VCPout1=VCC/2, PLL1_CP_GAIN = 010b 20 VCPout1=VCC/2, PLL1_CP_GAIN = 011b 80 MHz A In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs. This parameter is programmable Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 7 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Conditions PLL1 Charge Pump Sink Current (5) ICPout1 SINK Min Typ VCPout1=VCC/2, PLL1_CP_GAIN = 100b -25 VCPout1=VCC/2, PLL1_CP_GAIN = 101b -50 VCPout1=VCC/2, PLL1_CP_GAIN = 110b -100 VCPout1=VCC/2, PLL1_CP_GAIN = 111b -400 PLL1_CP_GAIN = 000b NA PLL1_CP_GAIN = 001b NA VCPout1=VCC/2, PLL1_CP_GAIN = 010b -20 VCPout1=VCC/2, PLL1_CP_GAIN = 011b -80 Max Units A ICPout1 %MIS Charge Pump Sink / Source Mismatch VCPout1 = VCC/2, T = 25 C 3 ICPout1VTUNE Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 C 4 % ICPout1 %TEMP Charge Pump Current vs. Temperature Variation 4 % PLL1 ICPout1 TRI Charge Pump TRI-STATE Leakage Current 10 0.5 V < VCPout < VCC - 0.5 V 5 % nA PLL2 Reference Input (OSCin) Specifications EN_PLL2_REF 2X = 0 PLL2 Reference Input fOSCin 250 (7) (6) EN_PLL2_REF 2X = 1 MHz 50 SLEWOSCin PLL2 Reference Clock minimum slew rate on OSCin 20% to 80% 0.15 VOSCin (Single-ended) Input Voltage for OSCin or OSCin* AC coupled; Single-ended (Unused pin AC coupled to GND) 0.2 2.0 Vpp VOSCin (Differential) Differential voltage swing AC coupled 0.4 3.1 Vpp 6 20 MHz 100 Ohms 0.5 V/ns Crystal Oscillator Mode Specifications fXTAL Crystal Frequency Range ESR Crystal Effective Series Resistance PXTAL Crystal Power Dissipation CIN Input Capacitance of LMK040xx OSCin port fPD Phase Detector Frequency 6 MHz < FXTAL < 20 MHz (8) Vectron VXB1 crystal, 12.288 MHz, RESR < 40 -40 to +85 C 200 W 6 pF PLL2 Phase Detector and Charge Pump Specifications (6) (7) (8) 8 100 MHz FOSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz. The EN_PLL2_REF2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path. See Application Section discussion of Crystal Power Dissipation. Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol ICPoutSOURCE ICPoutSINK Parameter Conditions PLL2 Charge Pump Source Current (9) PLL2 Charge Pump Sink Current (9) Min Typ VCPout2=VCC/2, PLL2_CP_GAIN = 00b 100 VCPout2=VCC/2, PLL2_CP_GAIN = 01b 400 VCPout2=VCC/2, PLL2_CP_GAIN = 10b 1600 VCPout2=VCC/2, PLL2_CP_GAIN = 11b 3200 VCPout2=VCC/2, PLL2_CP_GAIN = 00b -100 VCPout2=VCC/2, PLL2_CP_GAIN = 01b -400 VCPout2=VCC/2, PLL2_CP_GAIN = 10b -1600 VCPout2=VCC/2, PLL2_CP_GAIN = 11b -3200 Max Units A A ICPout2%MIS Charge Pump Sink/Source Mismatch VCPout2=VCC/2, TA = 25 C 3 ICPout2VTUNE Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation 0.5 V < VCPout2 < VCC - 0.5 V TA = 25 C 4 % ICPout2%TEMP Charge Pump Current vs. Temperature Variation 4 % ICPout2TRI Charge Pump Leakage PN10kHz PLL 1/f Noise at 10 kHz offset PLL2_CP_GAIN = 400 A (10) . Normalized to PLL2_CP_GAIN = 3200 A 1 GHz Output Frequency PN1Hz Normalized Phase Noise Contribution (11) 0.5 V < VCPout2 < VCC - 0.5 V 10 % 10 nA -117 dBc/Hz -122 PLL2_CP_GAIN = 400 A -219 PLL2_CP_GAIN = 3200 A -224 dBc/Hz Internal VCO Specifications fVCO PVCO VCO Tuning Range VCO Output power to a 50 load driven by Fout LMK040x0 1185 1296 LMK040x1 1430 1570 LMK040x2 1600 1750 LMK040x3 1840 2160 LMK040x0, TA = 25 C, singleended 3 LMK040x1, TA = 25 C, singleended 3 LMK040x2, TA = 25 C, singleended 2 LMK040x3, TA = 25 C, singleended 1840 MHz 0 LMK040x3, TA = 25 C, singleended 2160 MHz -5 MHz dBm (9) This parameter is programmable (10) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f). (11) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f)-20log(N)-10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 9 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol KVCO |TCL| Parameter Fine Tuning Sensitivity (The range displayed in the typical column indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range). Allowable Temperature Drift for Continuous Lock (12) Conditions Min Typ LMK040x0 7 to 9 LMK040x1 8 to 11 LMK040x2 9 to 14 Max Units MHz/V LMK040x3 14 to 26 After programming R15 for lock, no changes to output configuration are permitted to guarantee continuous lock 125 C Internal VCO Open Loop Phase Noise and Jitter LMK040x0 fVCO = 1185 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout LMK040x0 fVCO = 1296 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout L(f)Fout LMK040x1 fVCO = 1440 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout LMK040x1 fVCO = 1560 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout Offset = 1 kHz -66 Offset = 10 kHz -94 Offset = 100 kHz -119 Offset = 1 MHz -139 Offset = 10 MHz -158 Offset = 20 MHz -163 Offset = 1 kHz -64 Offset = 10 kHz -91 Offset = 100 kHz -117 Offset = 1 MHz -138 Offset = 10 MHz -157 Offset = 20 MHz -161 Offset = 1 kHz -61 Offset = 10 kHz -91 Offset = 100 kHz -117 Offset = 1 MHz -138 Offset = 10 MHz -158 Offset = 20 MHz -160 Offset = 1 kHz -58 Offset = 10 kHz -89 Offset = 100 kHz -115 Offset = 1 MHz -137 Offset = 10 MHz -157 Offset = 20 MHz -162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz (12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of -40 C to 85 C without violating specifications. 10 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Conditions Offset = 1 kHz LMK040x2 fVCO = 1600 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout LMK040x2 fVCO = 1750 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout L(f)Fout LMK040x3 fVCO = 1840 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout LMK040x3 fVCO = 2160 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout Copyright (c) 2008-2011, Texas Instruments Incorporated Min Typ Max Units -63 Offset = 10 kHz -91 Offset = 100 kHz -115 Offset = 1 MHz -137 Offset = 10 MHz -156 Offset = 20 MHz -161 Offset = 1 kHz -61 Offset = 10 kHz -90 Offset = 100 kHz -114 Offset = 1 MHz -136 Offset = 10 MHz -155 Offset = 20 MHz -160 Offset = 1 kHz -58 Offset = 10 kHz -88 Offset = 100 kHz -113 Offset = 1 MHz -135 Offset = 10 MHz -155 Offset = 20 MHz -158 Offset = 1 kHz -54 Offset = 10 kHz -84 Offset = 100 kHz -110 Offset = 1 MHz -132 Offset = 10 MHz -154 Offset = 20 MHz -157 dBc/Hz dBc/Hz dBc/Hz dBc/Hz Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 11 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Conditions Min Typ Max Units Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO LMK040x0 (13) fVCO = 1200 MHz SSB Phase Noise PLL2 = Closed Loop Measured at Fout LMK040x1 (14) fVCO = 1500 MHz SSB Phase Noise PLL2 = Closed Loop Measured at Fout L(f)Fout LMK040x2 (15) fVCO = 1600 MHz SSB Phase Noise PLL2 = Closed Loop Measured at Fout LMK040x3 (16) fVCO = 2000 MHz SSB Phase Noise PLL2 = Closed Loop Measured at Fout Offset = 1 kHz -111 Offset = 10kHz -119 Offset = 100 kHz -121 Offset = 1 MHz -133 Offset = 10 MHz -157 Offset = 20 MHz -162 Offset = 40 MHz -165 Offset = 1 kHz -110 Offset = 10 kHz -117 Offset = 100 kHz -120 Offset = 1 MHz -132 Offset = 10 MHz -156 Offset = 20 MHz -160 Offset = 40 MHz -163 Offset = 1 kHz -111 Offset = 10 kHz -118 Offset = 100 kHz -120 Offset = 1 MHz -132 Offset = 10 MHz -156 Offset = 20 MHz -162 Offset = 40 MHz -165 Offset = 1 kHz -107 Offset = 10 kHz -114 Offset = 100 kHz -117 Offset = 1 MHz -126 Offset = 10 MHz -152 Offset = 20 MHz -156 Offset = 40 MHz -160 dBc/Hz dBc/Hz dBc/Hz dBc/Hz (13) For LMK040x0, fVCO = 1200 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 268 kHz, PM = 75. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. (14) For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 268 kHz, PM = 75. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. (15) For LMK040x2, fVCO = 1600 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 8, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 252 kHz, PM = 76. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. (16) For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 434 kHz, PM = 69. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. 12 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter LMK040x0 (13) fVCO = 1200 MHz Integrated RMS Jitter (14) LMK040x1 fVCO = 1500 MHz Integrated RMS Jitter JFout (15) LMK040x2 fVCO = 1600 MHz Integrated RMS Jitter (16) LMK040x3 fVCO = 2000 MHz Integrated RMS Jitter Conditions Min Typ BW = 12 kHz to 20 MHz 105 BW = 100 Hz to 20 MHz 110 BW = 12 kHz to 20 MHz 100 BW = 100 Hz to 20 MHz 105 BW = 12 kHz to 20 MHz 95 BW = 100 Hz to 20 MHz 100 BW = 12 kHz to 20 MHz 105 BW = 100 Hz to 20 MHz 110 Max Units fs CLKout's Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO Offset = 1 kHz -125 Offset = 10 kHz -130 Offset = 100 kHz -132 Offset = 1 MHz -148 Offset = 10 MHz -157 LMK040x1 fCLKout = 250 MHz SSB Phase Noise Measured at Clock Outputs Value is average for all output types Offset = 1 kHz -126 Offset = 10 kHz -133 Offset = 100 kHz -136 Offset = 1 MHz -147 Offset = 10 MHz -156 LMK040x2 (19) fCLKout = 250 MHz SSB Phase Noise Measured at Clock Outputs Value is average for all output types Offset = 1 kHz -127 Offset = 10 kHz -133 Offset = 100 kHz -134 Offset = 1 MHz -145 Offset = 10 MHz -157 Offset = 1 kHz -125 Offset = 10 kHz -132 Offset = 100 kHz -135 Offset = 1 MHz -145 Offset = 10 MHz -156 LMK040x0 (17) fCLKout = 250 MHz SSB Phase Noise Measured at Clock Outputs Value is average for all output types (18) L(f)CLKout (20) LMK040x3 fCLKout = 250 MHz SSB Phase Noise Measured at Clock Outputs Value Is average for all output types dBc/Hz (17) For LMK040x0, fVCO = 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 251 kHz, PM = 76. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF. (18) For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 268 kHz, PM = 75. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 2. CLKout_DLY = OFF. (19) For LMK040x2, fVCO = 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 354 kHz, PM = 73. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF. (20) For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 434 kHz, PM = 69. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 4. CLKout_DLY = OFF. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 13 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter LMK040x0 (21) fCLKout = 250 MHz Integrated RMS Jitter Typ BW = 100 Hz to 20 MHz 135 BW = 12 kHz to 20 MHz 115 BW = 100 Hz to 20 MHz 120 BW = 12 kHz to 20 MHz 130 BW = 100 Hz to 20 MHz 135 LMK040x3 fCLKout = 250 MHz Integrated RMS Jitter BW = 12 kHz to 20 MHz 125 BW = 100 Hz to 20 MHz 130 LMK040x0 (21) fCLKout = 250 MHz Integrated RMS Jitter BW = 12 kHz to 20 MHz 140 BW = 100 Hz to 20 MHz 145 BW = 12 kHz to 20 MHz 110 BW = 100 Hz to 20 MHz 115 BW = 12 kHz to 20 MHz 130 BW = 100 Hz to 20 MHz 135 BW = 12 kHz to 20 MHz 120 BW = 100 Hz to 20 MHz 125 LMK040x1 fCLKout = 250 MHz Integrated RMS Jitter (23) LMK040x2 fCLKout = 250 MHz Integrated RMS Jitter (24) (22) JCLKout LVCMOS Min 130 (22) JCLKout LVPECL/2VPECL/LVDS Conditions BW = 12 kHz to 20 MHz LMK040x1 fCLKout = 250 MHz Integrated RMS Jitter (23) LMK040x2 fCLKout = 250 MHz Integrated RMS Jitter (24) LMK040x3 fCLKout = 250 MHz Integrated RMS Jitter Max Units fs fs CLKout's Internal VCO Closed Loop Jitter Specifications using a Commercial Quality VCXO (21) For LMK040x0, fVCO = 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 251 kHz, PM = 76. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF. (22) For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 268 kHz, PM = 75. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 2. CLKout_DLY = OFF. (23) For LMK040x2, fVCO = 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 354 kHz, PM = 73. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF. (24) For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 k, LBW = 434 kHz, PM = 69. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 4. CLKout_DLY = OFF. 14 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Typ Max BW = 12 kHz to 20 MHz 140 200 BW = 100 Hz to 20 MHz 185 BW = 12 kHz to 20 MHz 130 BW = 100 Hz to 20 MHz 190 BW = 12 kHz to 20 MHz 150 BW = 100 Hz to 20 MHz 190 LMK040x3 fCLKout = 250 MHz Integrated RMS Jitter BW = 12 kHz to 20 MHz 145 BW = 100 Hz to 20 MHz 200 LMK040x1 (30) fCLKout = 250 MHz Integrated RMS Jitter BW = 12 kHz to 20 MHz 130 BW = 100 Hz to 20 MHz 190 BW = 12 kHz to 20 MHz 145 BW = 100 Hz to 20 MHz 200 LMK040x0 (25) (26) fCLKout = 250 MHz Integrated RMS Jitter (27) (26) JCLKout LVPECL/2VPECL LMK040x1 fCLKout = 250 MHz Integrated RMS Jitter (28) (26) LMK040x2 fCLKout = 250 MHz Integrated RMS Jitter (29) (26) JCLKout LVDS (31) LMK040x3 fCLKout = 250 MHz Integrated RMS Jitter Conditions Min Units 200 200 fs 200 fs (25) For LMK040x0, FVCO = 1250 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, LBW = 254 kHz, PM = 81. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. (26) Max jitter specification applies to CH3 (LVPECL) output and guaranteed by test in production. (27) For LMK040x1, FVCO = 1500 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, LBW = 271 kHz, PM = 80. CLKDIST parameters: CLKoutX_DIV = 2, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. (28) For LMK040x2, FVCO = 1750 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, LBW = 360 kHz, PM = 79. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. (29) For LMK040x3, FVCO = 2000 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, LBW = 445 kHz, PM = 76. CLKDIST parameters: CLKoutX_DIV = 4, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: 100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. (30) For LMK040x1, FVCO = 1500 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, LBW = 271 kHz, PM = 80. CLKDIST parameters: CLKoutX_DIV = 2, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. (31) For LMK040x3, FVCO = 2000 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, LBW = 445 kHz, PM = 76. CLKDIST parameters: CLKoutX_DIV = 4, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: 100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 15 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter LMK040x0 (32) fCLKout = 250 MHz Integrated RMS Jitter (30) LMK040x1 fCLKout = 250 MHz Integrated RMS Jitter JCLKout LVCMOS (33) LMK040x2 fCLKout = 250 MHz Integrated RMS Jitter (31) LMK040x3 fCLKout = 250 MHz Integrated RMS Jitter Conditions Min Typ BW = 12 kHz to 20 MHz 150 BW = 100 Hz to 20 MHz 190 BW = 12 kHz to 20 MHz 125 BW = 100 Hz to 20 MHz 185 BW = 12 kHz to 20 MHz 150 BW = 100 Hz to 20 MHz 190 BW = 12 kHz to 20 MHz 145 BW = 100 Hz to 20 MHz 195 Max Units fs CLKout's Internal VCO Closed Loop Jitter Specifications using the Integrated Low Noise Crystal Oscillator Circuit LMK040x0 (34) fCLKout = 245.76 MHz Integrated RMS Jitter BW = 12 kHz to 20 MHz 190 BW = 100 Hz to 20 MHz 230 LMK040x1 fCLKout = 245.76 MHz Integrated RMS Jitter BW = 12 kHz to 20 MHz 200 BW = 100 Hz to 20 MHz 230 LMK040x2 (36) fCLKout = 245.76 MHz Integrated RMS Jitter BW = 12 kHz to 20 MHz 195 BW = 100 Hz to 20 MHz 230 BW = 12 kHz to 20 MHz 245 BW = 100 Hz to 20 MHz 260 (35) JCLKout LVPECL/2VPECL/LVDS (37) LMK040x3 fCLKout = 245.76 MHz Integrated RMS Jitter fs (32) For LMK040x0, FVCO = 1250 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, LBW = 254 kHz, PM = 81. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. (33) For LMK040x2, FVCO = 1750 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, LBW = 360 kHz, PM = 79. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. (34) For LMK040x0, FVCO = 1228.8 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 12.288 MHz Vectron crystal (model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 5, N2 = 10, EN_PLL2_REF2X = 1, FDET = 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, R3 = 600 , R4 = 10 k, C3 = 150 pF, C4 = 60 pF, LBW = 109 kHz, PM = 43, CLKoutX_DIV = 2, CLKout_DLY = OFF. (35) For LMK040x1, FVCO = 1474.56 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 12.288 MHz Ecliptek crystal (model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 3, N2 = 20, EN_PLL2_REF2X = 1, FDET = 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, R3 = 600 , R4 = 10 k, C3 = 150 pF, C4 = 60 pF, LBW = 103 kHz, PM = 44, CLKoutX_DIV = 2, CLKout_DLY = OFF. (36) For LMK040x2, FVCO = 1720.32 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 12.288 MHz Vectron crystal (model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 7, N2 = 10, EN_PLL2_REF2X = 1, FDET = 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, R3 = 600 , R4 = 10 k, C3 = 150 pF, C4 = 60 pF, LBW = 120 kHz, PM = 40, CLKoutX_DIV = 2, CLKout_DLY = OFF. (37) For LMK040x3, FVCO = 1966.08 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 12.288 MHz Ecliptek crystal (model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 4, N2 = 20, EN_PLL2_REF2X = 1, FDET = 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 k, R3 = 600 , R4 = 10 k, C3 = 150 pF, C4 = 60 pF, LBW = 91 kHz, PM = 47, CLKoutX_DIV = 2, CLKout_DLY = OFF. 16 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Conditions LMK040x0 (34) fCLKout = 245.76 MHz Integrated RMS Jitter (35) JCLKout LVCMOS LMK040x1 fCLKout = 245.76 MHz Integrated RMS Jitter (36) LMK040x2 fCLKout = 245.76 MHz Integrated RMS Jitter (37) LMK040x3 fCLKout = 245.76 MHz Integrated RMS Jitter Min Typ BW = 12 kHz to 20 MHz 195 BW = 100 Hz to 20 MHz 230 BW = 12 kHz to 20 MHz 195 BW = 100 Hz to 20 MHz 220 BW = 12 kHz to 20 MHz 195 BW = 100 Hz to 20 MHz 230 BW = 12 kHz to 20 MHz 240 BW = 100 Hz to 20 MHz 260 Max Units fs Digital Inputs (CLKuWire, DATAuWire, LEuWire) VIH High-Level Input Voltage VIL Low-Level Input Voltage 1.6 IIH High-Level Input Current VIH = VCC IIL Low-Level Input Current VIL = 0 VCC V 0.4 V -5 25 A -5.0 5.0 A 1.6 VCC V Digital Inputs (GOE, SYNC*) VIH High-Level Input Voltage VIL Low-Level Input Voltage 0.4 V IIH High-Level Input Current VIH = VCC -5.0 5.0 A IIL Low-Level Input Current VIL = 0 -40.0 5.0 A Digital Outputs (CLKinX_LOS, LD) VOH High-Level Output Voltage IOH = -500 A VOL Low-Level Output Voltage IOL = 500 A VCC - 0.4 V 0.4 V Default Power On Reset Clock Output Frequency fCLKout-startup CLKout2, LM040x0 50 Default output clock frequency CLKout2, LM040x1 at device power on CLKout2, LM040x2 62 CLKout2, LM040x3 81 MHz 68 LVDS Clock Outputs (CLKoutX) fCLKout TSKEW Maximum Frequency (38) RL = 100 CLKoutX to CLKoutY LVDS-LVDS, T = 25 C, FCLK = 800 MHz, RL= 100 (39) 1080 250 MHz ps 450 mV 50 mV 1.375 V 35 |mV| VOD Differential Output Voltage VOD Change in Magnitude of VOD for complementary output states VOS Output Offset Voltage VOS Change in VOS for complementary output states ISA ISB Output short circuit current single ended Single-ended output shorted to GND, T = 25 C -24 24 mA ISAB Output short circuit current differential Complimentary outputs tied together -12 12 mA R = 100 differential termination, AC coupled to receiver input, FCLK = 800 MHz, T = 25 C LVPECL Clock Outputs (CLKoutX) 350 30 -50 1.125 1.25 (40) (38) For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to 1/2 of a period, or, 0.5/FCLKoutX. (39) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for delay mode. (40) LVPECL/2VPECL is programmable for all NSIDs. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 17 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Conditions Min Maximum Frequency fCLKout (42) 40 Output High Voltage VOL Output Low Voltage VOD Output Voltage FCLK = 100 MHz, T = 25 C Termination = 50 to VCC - 2 V 660 Units MHz LVPECL-to-LVPECL, T = 25 C, FCLK = 800 MHz, each output terminated with 120 to GND. CLKoutX to CLKoutY VOH Max 1080 (41) TSKEW Typ ps VCC 0.93 V VCC 1.82 V 890 965 mV 2VPECL Clock Outputs (CLKoutX) Maximum Frequency fCLKout 1080 (41) 2VPECL-2VPECL, T=25 C, FCLK = 800 MHz, each output terminated with 120 to GND. CLKoutX to CLKoutY TSKEW (42) VOH 40 Output High Voltage VOL Output Low Voltage VOD Output Voltage MHz FCLK = 100 MHz, T = 25 C Termination = 50 to VCC - 2 V 800 ps VCC 0.95 V VCC 1.98 V 1030 1200 mV LVCMOS Clock Outputs (CLKoutX) fCLKout Maximum Frequency 5 pF Load 250 VOH Output High Voltage 1 mA Load VCC - 0.1 MHz VOL Output Low Voltage 1 mA Load IOH Output High Current (Source) VCC = 3.3 V, VO = 1.65 V 28 mA IOL Output Low Current (Sink) VCC = 3.3 V, VO = 1.65 V 28 mA TSKEW Skew between any two LVCMOS outputs, same channel or different channel RL = 50 , CL = 10 pF, T = 25 C, FCLK = 100 MHz. DUTYCLK Output Duty Cycle VCC/2 to VCC/2, FCLK = 100 MHz, T = 25 C (44) TR Output Rise Time 20% to 80%, RL = 50 , CL = 5 pF 400 ps TF Output Fall Time 80% to 20%, RL = 50 , CL = 5 pF 400 ps V 0.1 (43) 45 50 V 100 ps 55 % Mixed Clock Skew TSKEW ChanX - ChanY LVPECL to LVDS skew Same device, T = 25 C, 250 MHz -230 ps LVDS to LVCMOS skew Same device, T = 25 C, 250 MHz 770 ps LVCMOS to LVPECL skew Same device, T = 25 C, 250 MHz -540 ps Microwire Interface Timing TCS Data to Clock Set Up Time See Microwire Input Timing 25 ns TCH Data to Clock Hold Time See Microwire Input Timing 8 ns (41) For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to 1/2 of a period, or, 0.5/FCLKoutX. (42) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for delay mode. (43) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for delay mode. (44) Guaranteed by characterization. 18 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Electrical Characteristics (continued) (3.15 V VCC 3.45 V, -40 C TA 85 C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol Parameter Conditions Min Typ Max Units TCWH Clock Pulse Width High See Microwire Input Timing 25 ns TCWL Clock Pulse Width Low See Microwire Input Timing 25 ns TES Clock to Latch Enable Set Up Time See Microwire Input Timing 25 ns TCES Clock to Enable Setup Time See Microwire Input Timing 25 ns TEW Load Enable Pulse Width See Microwire Input Timing 25 ns Serial Data Timing Diagram MSB DATAuWire D27 LSB D26 D25 D24 D23 D0 A3 A2 A1 A0 CLKuWire tCES tCS tCH tCWH tCWL tES LEuWire tEWH Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/s is recommended for these signals. After programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. If the CLKuWire or DATAuWire lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this programming. Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current at VCPout = VCC - V I2 = Charge Pump Sink Current at VCPout = VCC/2 Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 19 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com I3 = Charge Pump Sink Current at VCPout = V I4 = Charge Pump Source Current at VCPout = VCC - V I5 = Charge Pump Source Current at VCPout = VCC/2 I6 = Charge Pump Source Current at VCPout = V V = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device. Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch Charge Pump Output Current Magnitude Variation vs. Temperature 20 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Typical Performance Characteristics Clock Output AC Characteristics LVDS VOD vs. Frequency LVPECL VOD vs. Frequency 1.0 2.5 DIFFERENTIAL P-P VOLTAGE (V) DIFFERENTIAL P-P VOLTAGE (V) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 300 600 900 1.2k 1.5k 2.0 LV2PECL Mode 1.5 1.0 NORMAL Mode 0.5 0.0 0 1.8k 400 5 1.6k 2k Figure 3. LVCMOS Vpp vs. Frequency Typical Dynamic ICC, LVCMOS Driver, VCC = 3.3 V, Temp = 25 C, CL= 5 pF No Load 10 pF Load 22 pF Load 3 2 47 pF Load 40 35 30 25 20 15 10 5 0 100 pF Load 0 0 100 200 300 400 500 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Figure 5. Clock Channel Delay Noise Floor vs. Frequency Clock Output Noise Floor vs. Frequency Delay = 2100 ps -130 -135 -140 -145 -150 -155 -160 -165 -170 NOISE FLOOR (dBc/Hz) NOISE FLOOR (dBc/Hz) 1.2k Figure 2. 4 1 800 FREQUENCY (MHz) ICC (mA) SINGLE-ENDED P-P VOLTAGE (V) FREQUENCY (MHz) Delay = 1800 ps Delay = 450 ps Delay = 0 ps -130 -135 -140 LVPECL (differential) -145 -150 LVDS (differential) -155 -160 -165 -170 Delay = 900 ps 10 LVCMOS 100 FREQUENCY (MHz) Figure 6. 1000 10 100 1000 FREQUENCY (MHz) Figure 7. To estimate this noise, only the output frequency is required. Divide value and input frequency are not relevant. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 21 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Typical Performance Characteristics (continued) The noise of the delay block is independent of output type and only applies if the delay is enabled. The noise floor, due to the distribution section accounting for the delay noise, can be calculated as: Total Output Noise = 10 x log(10Output Buffer Noise/10 + 10Delay Noise Floor/10). Typical LVDS Phase Noise, FCLK = 250 MHz, RMS Jitter = 192 fs (100 Hz to 20 MHz) -80 -90 -100 dBc -110 -120 -130 -140 -150 -160 -170 100 1000 10000 100000 1000000 10000000 100000000 OFFSET (Hz) Figure 8. Typical LVPECL Phase Noise, FCLK = 250 MHz, RMS Jitter = 196 fs (100 Hz to 20 MHz) -80 -90 -100 dBc -110 -120 -130 -140 -150 -160 -170 100 1000 10000 100000 1000000 10000000 100000000 OFFSET (Hz) Figure 9. Reference clock = 10 MHz, PLL1_R = 10, PLL1_N = 100, PLL1_CP_GAIN = 100 A, PLL1 Loop BW = 20 Hz, VCXO = 100 MHz Crystek CVPD-920-100, PLL2_R = 2, PLL2_N = 10, PLL2_CP_GAIN = 1600 A, PLL2 Loop BW = 137 kHz, fVCO = 1500 MHz, VCO_DIV = 3, CLKoutX_DIV = 2, CLK_DLY = OFF. 22 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Typical Performance Characteristics (continued) Typical LVCMOS Phase Noise, FCLK = 250 MHz, RMS Jitter = 188 fs (100 Hz to 20 MHz) -80 -90 -100 dBc -110 -120 -130 -140 -150 -160 -170 100 1000 10000 100000 1000000 10000000 100000000 OFFSET (Hz) Figure 10. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 23 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com FEATURES System Architecture The cascaded PLL architecture of the LMK040xx was chosen to provide the lowest jitter performance over the widest range of output frequencies and phase noise offset frequencies. The first stage PLL (PLL1) is used in conjunction with an external reference clock and an external VCXO to provide a frequency accurate, low phase noise reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated along its path or from other circuits. The "cleaned" reference clock frequency accuracy is combined with the low phase noise of an external VCXO to provide the reference input to PLL2. The low phase noise reference provided to PLL2 allows it to use wider loop bandwidths (50 kHz to 200 kHz). The chosen loop bandwidth for PLL2 should take best advantage of the superior high offset frequency phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO for PLL2. Ultra low jitter is achieved by allowing the external VCXO's phase noise to dominate the final output phase noise at low offset frequencies and the internal VCO's phase noise to dominate the final output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance. Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*) The LMK040xx has two LVDS/LVPECL/LVCMOS compatible reference clock inputs for PLL1, CLKin0 and CLKin1. The selection of the preferred input may be fixed to either CLKin0 or CLKin1, or may be configured to employ one of two automatic switching modes when redundant clock signals are present. The PLL1 reference clock input buffers may also be individually configured as either a CMOS buffered input or a bipolar buffered input. PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS) When either of the two auto-switching modes is selected for the reference clock input mode, the signal status of the selected reference clock input is indicated by the state of the CLKinX_LOS (loss-of-signal) output. These outputs may be configured as either CMOS (active HIGH on loss-of-signal), NMOS open-drain or PMOS opendrain. If PLL1 was originally locked and then both reference clocks go away, then the frequency accuracy of the LMK04000 device will be set by the absolute tuning range of the VCXO used on PLL1. The absolute tuning range of the VCXO can be determined by multiplying its' tuning constant by the charge pump voltage. Integrated Loop Filter Poles The LMK040xx features programmable 3rd and 4th order loop filter poles for PLL2. When enabled, internal resistors and capacitor values may be selected from a fixed range of values to achieve either 3rd or 4th order loop filter response. These programmable components compliment external components mounted near the chip. Clock Distribution The LMK040xx features a clock distribution block with a minimum of five outputs that are a mixture of LVPECL, 2VPECL, LVDS, and LVCMOS. The exact combination is determined by the part number. The 2VPECL is a National Semiconductor proprietary configuration that produces a 2 Vpp differential swing for compatibility with many data converters. More than five outputs may be available for device versions that offer dual LVCMOS outputs. CLKout Divide (CLKoutX_DIV, X = 0 to 4) Each individual clock distribution channel includes a channel divider. The range of divide values is 2 to 510, in steps of 2. "Bypass" mode operates as a divide-by-1. CLKout Delay (CLKoutX_DLY, X = 0 to 4) Each individual clock distribution channel includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a nominal 150 ps step size and range from 0 to 2250 ps of total delay. 24 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Global Clock Output Synchronization (Sync*) The SYNC* input is used to synchronize the active clock outputs. When SYNC* is held in a logic low state, the outputs are also held in a logic low state. When SYNC* goes high, the clock outputs are activated and will transition to a high state simultaneously with one another. SYNC* must be held low for greater than one clock cycle of the Clock Distribution Path. After this low event has been registered, the outputs will not reflect the low state for four more cycles. Similarly after SYNC* becomes high, the outputs will simultaneously transition high after four Clock Distribution Path cycles have passed. See Figure 11 for further detail. Distribution Path SYNC* CLKout0 CLKout1 CLKout2 Figure 11. Clock Output synchronization using the SYNC* pin Global Output Enable and Lock Detect Each Clock Output Channel may be either enabled or put into a high impedance state via the Clock Output Enable control bit (one for each channel). Each output enable control bit is gated with the Global Output Enable input pin (GOE). The GOE pin provides an internal pull-up so that if it is un-terminated externally, then the clock output states are determined by the Clock Channel Output Enable Register bits. All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal. Table 2. Clock Output Control CLKoutX _EN bit EN_CLKout _Global bit GOE pin CLKoutX Output State 1 1 Low Low Don't care 0 Don't care Off 0 Don't care Don't care Off 1 1 High / No Connect Enabled The Lock Detect (LD) signal can be connected to the GOE pin in which case all outputs are disabled automatically if the synthesizer is not locked. See EN_CLKoutX: Clock Channel Output Enable and also System Level Diagram for actual implementation details. The Lock Detect (LD) pin can be programmed to output a `High' when both PLL1 and PLL2 are locked, or only when PLL1 is locked or only when PLL2 is locked. FUNCTIONAL DESCRIPTION Architectural Overview The LMK040xx chip consists of two high performance synthesizer blocks (Phase Locked Loop, internal VCO/VCO Divider, and loop filter), source selection, distribution system, and independent clock output channels. The Phase Frequency Detector in PLL1 compares the divided (R Divider 1) system clock signal from the selected CLKinX and CLKinX* input with the divided (N Divider 1) output of the external VCXO attached to the PLL2 OSCin port. The external loop filter for PLL1 should be narrow to provide an ultra clean reference clock from the external VCXO to the OSCin/OSCin* pins for PLL2. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 25 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com The Phase Frequency Detector in PLL2 then compares the divided (R Divider 2) reference signal from the PLL2 OSCin port with the divided (N Divider 2 and VCO Divider) output of the internal VCO. The bandwidth of the external loop filter for PLL2 should be designed to be wide enough to take advantage of the low in-band phase noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is passed through a common VCO divider block and placed on a distribution path for the clock distribution section. It is also routed to the PLL2_N counter. Each clock output channel allows the user to select a path with a programmable divider block, a phase synchronization circuit, a programmable delay, and LVDS/LVPECL/2VPECL/LVCMOS compatible output buffers. Phase Detector 1 (PD1) Phase Detector 1 in PLL1 (PD1) can operate up to 40 MHz. Since a narrow loop bandwidth should be used for PLL1, the need to operate at high phase detector rate to lower the in-band phase noise becomes unnecessary. Phase Detector 2 (PD2) Phase Detector 2 in PLL2 (PD2) supports a maximum comparison rate of 100 MHz, though the actual maximum frequency at the input port (PLL2 OSCin/OSCin*) is 250 MHz. Operating at highest possible phase detector rate will ensure low in-band phase noise for PLL2 which in turn produces lower total jitter, as the in-band phase noise from the reference input and PLL are proportional to N2. PLL2 Frequency Doubler The PLL2 reference input at the OSCin port may be optionally routed through a frequency doubler function rather than through the PLL2_R counter. The maximum phase comparison frequency of the PLL2 phase detector is 100 MHz, so the input to the frequency doubler is limited to a maximum of 50 MHz. The frequency doubler feature allows the phase comparison frequency to be increased when a relative low frequency oscillator is driving the OSCin port. By doubling the PLL2 phase comparison frequency, the in-band PLL2 noise is reduced by about 3 dB. Inputs / Outputs PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*) The reference clock inputs for PLL1 may be selected from either CLKin0 and CLKin1. The user has the capability to manually select one of the two inputs or to configure an automatic switching mode operation. A detailed description of this function is described in the uWire programming section of this data sheet. PLL2 OSCin / OSCin* Port The feedback from the external oscillator being locked with PLL1 is injected to the PLL2 OSCin/OSCin* pins. This input may be driven with either a single- ended or differential signal. If operated in single ended mode, the unused input should be tied to GND with a 0.1 F capacitor. Either AC or DC coupling is acceptable. Internal to the chip, this signal is routed to the PLL1_N Counter and to the reference input for PLL2. The internal circuitry of the OSCin port also supports the optional implementation of a crystal based oscillator circuit. A crystal, varactor diode and a small number of other external components may be used to implement the oscillator. The internal oscillator circuit is enabled by setting the EN_PLL2_XTAL bit. CPout1 / CPout2 The CPout1 pin provides the charge pump current output to drive the loop filter for PLL1. This loop filter should be configured so that the total loop bandwidth for PLL1 is less than 200 Hz. When combined with an external oscillator that has low phase noise at offsets close to the carrier, PLL1 generates a reference for PLL2 that is frequency locked to the PLL1 reference clock but has the phase noise performance of the oscillator. The CPout2 pin provides the charge pump current output to drive the loop filter for PLL2. This loop filter should be configured so that the total loop bandwidth for PLL2 is in the range of 50 kHz to 200 kHz. See the section on uWire device control for a description of the charge pump current gain control. 26 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Fout The buffered output of the internal VCO is available at the Fout pin. This is a single-ended output (sinusoid). Each time the PLL2_N counter value is updated via the uWire interface, an internal algorithm is triggered that optimizes the VCO performance. Digital Lock Detect 1 Bypass The VCO coarse tuning algorithm requires a stable OSCin clock (reference clock to PLL2) to frequency calibrate the internal VCO correctly. In order to ensure a stable OSCin clock, the first PLL must achieve lock status. A digital lock detect is used in PLL1 to monitor its lock status. After lock is achieved by PLL1, the coarse tuning circuitry is enabled and frequency calibration for the internal VCO begins. The (DLD_BYP) pin is provided to allow an external bypass cap to be connected to the digital lock detect 1. This capacitor will eliminate potential glitches at initial startup of PLL1 due to unknown phase relationships between the Ncntr1 and Rcntr1. Bias Proper bypassing of this pin by a 1 F capacitor connected to VCC is important for low noise performance. General Programming Information LMK040xx devices are programmed using several 32-bit registers. Each register consists of a 4-bit address field and 28-bit data field. The address field is formed by bits 0 through 3 (LSBs) and the data field is formed by bits 4 through 31 (MSBs). The contents of each register are clocked in MSB first (bit 31), and the LSB (bit 0) last. During programming, the LE signal should be held LOW. The serial data is clocked in on the rising edge of the CLK signal. After the LSB (bit 0) is clocked in the LE signal should be toggled LOW-to-HIGH-to-LOW to latch the contents into the register selected in the address field. Registers R0-R4, R7, and R8-R15 must be programmed in order to achieve proper device operation. Figure 12 illustrates the serial data timing sequence. MSB DATAuWire D27 LSB D26 D25 D24 D23 D0 A3 A2 A1 A0 CLKuWire tCES tCS tCH tCWH tCWL tES LEuWire tEWH Figure 12. uWire Timing Diagram To achieve proper frequency calibration, the OSCin port must be driven with a valid signal before programming Register 15. Changes to PLL2_R Counter or the OSCin port signal require Register 15 to be reloaded in order to activate the frequency calibration process. Recommended Programming Sequence The recommended programming sequence involves programming R7 with the reset bit set to 1 (Reg. 7, bit 4) to ensure the device is in a default state. If R7 is programmed again, the reset bit should be set to 0. Registers are programmed in order with R15 being the last register programmed. An example programming sequence is shown below: * Program R7 with the RESET bit = 1 (b4 = 1). This ensures that the device is configured with default settings. When RESET = 1, all other R7 bits are ignored. - - If R7 is programmed again during the initial configuration of the device, the RESET bit should be cleared (b4 = 0) * Program R0 through R4 as necessary to configure the clock outputs as desired. These registers configure clock channel functions such as the channel multiplexer output selection, divide value, delay value, and enable/disable bit. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 27 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 * * * * * * www.ti.com Program R5 and R6 with the default values shown in the register map on the following pages. Program R7 with RESET = 0. Program R8 through R10 with the default values shown in the register map on the following pages. Program R11 to configure the reference clock inputs (CLKin0 and CLKin1). - - type, LOS timeout, LOS type, and mode (manual or auto-switching) Program R12 to configure PLL1. - - Charge pump gain, polarity, R counter and N counter Program R13 through R15 to configure PLL2 parameters, crystal mode options, and certain globally asserted functions. The following table provides the register map for device programming: 28 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Table 3. Register Map 31-16 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 CLKout0_MUX EN_CLK out0 Data [31:16] R0 0 0 0 0 0 0 0 1 CLKout0 _PECL_ LVL R1 0 0 0 0 0 0 0 1 CLKout1 _PECL_ LVL CLKout1B_STATE [1:0] CLKout1A_STATE [1:0] CLKout1_MUX [1:0] EN_CLK out1 R2 0 0 0 0 0 0 0 1 CLKout2 _PECL_ LVL CLKout2B_STATE [1:0] CLKout2A_STATE [1:0] CLKout2_MUX [1:0] EN_CLK out2 R3 0 0 0 0 0 0 0 1 CLKout3 _PECL_ LVL CLKout3B_STATE [1:0] CLKout3A_STATE [1:0] CLKout3_MUX [1:0] EN_CLK out3 R4 0 0 0 0 0 0 0 1 CLKout4 _PECL_ LVL 0 0 0 0 CLKout4_MUX [1:0] EN_CLK out4 R5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 R7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R9 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 RC_DLD 1_Start 0 0 0 0 1 0 1 0 1 0 0 0 0 R11 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 R12 PLL1_C P_POL R13 0 0 0 EN_Fout 0 EN_CLK out_Glob al, default=1 POWER DOWN, default = 0 EN_PLL 2_REF2 X R14 0 0 0 R10 R15 0 PLL1_CP_GAIN [2:0] 0 0 PLL1_R Counter [11:0] 1 0 1 0 0 0 EN_PLL 2_XTAL OSCin_FREQ [7:0] 0 1 PLL2_CP_GAIN [1:0] VCO_DIV [3:0] PLL_MUX [4:0] PLL2_N Counter [17:0] Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 Submit Documentation Feedback 29 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Register Map 15-0 Register 15 14 13 12 11 10 9 8 7 6 5 4 Data [15:4] 2 1 0 A2 A1 A0 R0 CLKout0_DIV [7:0] CLKout0_DLY [3:0] 0 0 0 0 R1 CLKout1_DIV [7:0] CLKout1_DLY [3:0] 0 0 0 1 R2 CLKout2_DIV [7:0] CLKout2_DLY [3:0] 0 0 1 0 R3 CLKout3_DIV [7:0] CLKout3_DLY [3:0] 0 0 1 1 R4 CLKout4_DIV [7:0] CLKout4_DLY [3:0] 0 1 0 0 R5 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 R6 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 R7 0 0 0 0 0 0 0 0 0 0 0 RESET 0 1 1 1 R8 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R9 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 R10 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 R11 0 0 0 0 CLKin1_ BUFTYP E 1 0 1 1 1 1 0 0 1 1 0 1 R12 R13 30 3 A3 CLKin0_ BUFTYP LOS_TIMEOUT [1:0] E LOS_TYPE [1:0] CLKin_SEL [1:0] PLL1_N Counter [11:0] PLL2 CP TRISTATE PLL1 CP TRISTATE PLL2_R4_LF [2:0] PLL2_R3_LF [2:0] PLL2_C3_C4_LF [3:0] R14 PLL2_R Counter [11:0] 1 1 1 0 R15 PLL2_N Counter [17:0] 1 1 1 1 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Default Device Register Settings After Power On/Reset Table 4 illustrates the default register settings programmed in silicon for the LMK040xx after power on or asserting the reset bit. Table 4. Default Device Register Settings after Power On/Reset Field Name Default Value (decimal) Default State Field Description Register Bit Location (MSB:LSB) CLKoutX_PECL_LVL 0 2VPECL disabled This bit sets LVPECL clock level. Valid when the clock channel is configured as LVPECL/2VPECL; otherwise, not relevant. R0 to R4 23 CLKoutXB_STATE 0 Inverted This field sets the state of output B of an LVCMOS Clock channel. R1 to R3 22:21 CLKoutXA_STATE 1 Non-Inverted This field sets the state of output A of an LVCMOS Clock channel. R1 to R3 20:19 EN_CLKoutX 0 OFF Clock Channel enable bit. Note: The state of CLKout2 is ON by default. R0 to R4 16 R5,R6,R8 R9,R10 NA Forces the VCO tuning algorithm state machine to wait until PLL1 is locked. R10 29 11 (1) Reserved Registers (1) RC_DLD1_Start 1 Enabled CLKin1_BUFTYPE 1 MOS mode CLKin1 Input Buffer Type R11 CLKin0_BUFTYPE 1 MOS mode CLKin0 Input Buffer Type R11 10 LOS_TIMEOUT 1 3 MHz (min.) Selects Lower Reference Clock input frequency for LOS Detection. R11 9:8 LOS_TYPE 3 CMOS Selects LOS output type R11 7:6 CLKin_SEL 0 CLKin0 Selects Reference Clock source R11 5:4 PLL1 CP Polarity 1 Positive polarity Selects the charge pump output polarity, i.e., the tuning slope of the external VCXO R12 31 PLL1_CP_GAIN 6 100 A Sets the PLL1 Charge Pump Gain R12 30:28 PLL1_R Counter 1 Divide = 1 Sets divide value for PLL1_R Counter R12 27:16 PLL1_N Counter 1 Divide = 1 Sets divide value for PLL1_N Counter R12 15:4 EN_PLL2_REF2X 0 Disabled Enables or disables the OSCin frequency doubler path for the PLL2 reference input R13 16 EN_PLL2_XTAL 0 OFF Enables or Disables internal circuits that support an external crystal driving the OSCin pins R13 21 EN_Fout 0 OFF Enables or disables the VCO output buffer R13 20 CLK Global Enable 1 Enabled Global enable or disable for output clocks R13 18 POWER DOWN 0 R13 17 PLL2 CP TRI-STATE 0 TRI-STATE disabled Enables or disables TRI-STATE for PLL2 Charge Pump R13 15 PLL1 CP TRI-STATE 0 TRI-STATE disabled Enables or disables TRI-STATE for PLL1 Charge Pump R13 14 (2) Disabled (device is Device power down control active) OSCin_FREQ 200 200 MHz Source frequency driving OSCin port R14 28:21 PLL_MUX 31 Reserved Selects output routed to LD pin R14 20:16 PLL2_R Counter 1 Divide = 1 Sets Divide value for PLL2_R Counter R14 15:4 PLL2_CP_GAIN 2 1600 A Sets PLL2 Charge Pump Gain R15 27:26 VCO_DIV 2 Divide = 2 Sets divide value for VCO output divider R15 25:22 PLL2_N Counter 1 Divide = 1 Sets PLL2_N Counter value R15 21:4 (1) (2) These registers are reserved. The Power On/Reset values for these registers are shown in the register map and should not be changed during programming. If the CLKin_SEL value is set to either [0,0] or [0,1], the LOS_TYPE field should be set to [0,0]. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 31 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Register R0 To R4 Registers R0 through R4 control the five clock outputs. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. Aside from this, the functions of the bits in these registers are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 4. CLKoutX_DIV: Clock Channel Divide Registers Each of the five clock output channels (0 though 4) has a dedicated 8-bit divider followed by a fixed divide by 2 that is used to generate even integer related versions of the distribution path clock frequency (VCO Divider output). If the VCO Divider value is even then the Channel Divider may be bypassed (See CLK Output Mux), giving an effective divisor of 1 while preserving a 50% duty cycle output waveform. Table 5. CLKoutX_DIV: Clock Channel Divide Values CLKoutX_DIV [ 7:0 ] Total Divide Value b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 invalid 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 4 0 0 0 0 0 0 1 1 6 0 0 0 0 0 1 0 0 8 0 0 0 0 0 1 0 1 10 - - - - -- - - - - 1 1 1 1 1 1 1 1 510 EN_CLKoutX: Clock Channel Output Enable Each Clock Output Channel may be either enabled or disabled via the Clock Output Enable control bits. Each output enable control bit is gated with the Global Output Enable input pin (GOE) and Global Output Enable bit (EN_CLKout_Global). The GOE pin provides an internal pull-up so that if it is unterminated externally, the clock output states are determined by the Clock Output Enable Register bits. All clock outputs can be set to the low state simultaneously if the GOE pin is pulled low by an external signal. If EN_CLKout_Global is programmed to 0 all outputs are turned off. If both GOE and EN_CLKout_Global are low the clock outputs are turned off. Table 6. EN_CLKoutX: Clock Channel Output Enable Control Bits BIT NAME BIT = 1 BIT = 0 DEFAULT EN_CLKout0 ON OFF OFF EN_CLKout1 ON OFF OFF EN_CLKout2 ON OFF ON EN_CLKout3 ON OFF OFF EN_CLKout4 ON OFF OFF EN_CLKout_Global According to individual channel settings All EN_CLKout X = OFF - Note the default state of CLKout2 is ON after power on or RESET assertion. The nominal frequency is 62 MHz (LMK040x1) or 81 MHz (LMK040x3). This is based on a channel divide value of 12 and default VCO_DIV value of 2. If an active CLKout2 at power on is inappropriate for the user's application, the following method can be employed to shut off CLKout2 during system initialization: When the device is powered on, holding the GOE pin LOW will disable all clock outputs. The device can be programmed while the GOE is held LOW. The state of CLKout2 can be altered during device programming according to the user's specific application needs. After device configuration is complete, the GOE pin should be set HIGH to enable the active clock channels. 32 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 CLKoutX_DLY: Clock Channel Phase Delay Adjustment Each output channel has an output delay register that can be used to introduce a lag relative to the distribution path frequency (VCO Divider output). These registers support a 150 ps stepsize and range from 0 to 2.25 ns of total delay. When the channel phase delay registers are enabled, a nominal fixed delay of 300 ps of delay is incurred in addition to the programmed delay. The Channel Phase Delay Adjustment Registers are 4 bits wide and are programmed as follows: Table 7. CLKoutX_DLY: Clock Channel Delay Control Bit Values CLKoutX_DLY [ 3:0 ] DELAY (ps) b3 b2 b1 b0 0 0 0 0 0 0 0 0 1 150 0 0 1 0 300 0 0 1 1 450 0 1 0 0 600 0 1 0 1 750 0 1 1 0 900 0 1 1 1 1050 1 0 0 0 1200 1 0 0 1 1350 1 0 1 0 1500 1 0 1 1 1650 1 1 0 0 1800 1 1 0 1 1950 1 1 1 0 2100 1 1 1 1 2250 CLKoutX/CLKoutX* LVCMOS Mode Control For clock outputs that are configured as LVCMOS, the LVCMOS CLKoutX/CLKoutX* outputs can be independently configured by uWire CLKoutXA_STATE and CLKoutXB_STATE bits. The following choices are available for LVCMOS outputs: Table 8. CLKoutXA_STATE, CLKoutXB_STATE Control Bits for LVCMOS Modes CLKoutXA_STATE CLKoutXB_STATE LVCMOS Modes b1 b0 b1 b0 0 0 0 0 Inverted 0 1 0 1 Normal 1 0 1 0 Low 1 1 1 1 TRI-STATE CLKoutX/CLKoutX* LVPECL Mode Control Clock outputs designated as LVPECL can be configured in one of two possible output levels. The default mode is the common LVPECL swing of 800 mVp-p single-ended (1.6 Vp-p differential). A second mode, 2VPECL, can be enabled in which the swing is increased to 1000 mVp-p single-ended (2 Vp-p differential). Table 9. LVPECL Output Format Control CLKoutX_PECL_LVL Output Format 0 LVPECL (800 mVpp) 1 2VPECL (1000 mVpp) Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 33 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com CLKoutX_MUX: Clock Output Mux The output of each CLKoutX channel pair is controlled by its' channel multiplexer (mux). The mux can select between several signals: bypassed, divided only, divided and delayed, or delayed only. Table 10. CLKoutX_MUX: Clock Channel Multiplexer Control Bits CLKout_MUX [1:0] Clock Mode b1 b0 0 0 Bypassed 0 1 Divided 1 0 Delayed 1 1 Divided and Delayed Registers 5, 6 These registers are reserved. These register values should not be modified from the values shown in the register map. Register 7 Reset bit This bit is only in register R7. The use of this bit is optional and it should be set to '0' if not used. Setting this bit to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit. Registers 8, 9 These registers are reserved. These register values should not be modified from the values shown in the register map. Register 10 RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit This bit is used to control the state machine for the PLL2 VCO tuning algorithm. The following table describes the function of this bit. Table 11. RC_DLD1_Start bit States RC_DLD1_Start Description 1 The PLL2 VCO tuning algorithm trigger is delayed until PLL1 Digital Lock Detect is valid. 0 The PLL2 VCO tuning algorithm runs immediately after any PLL2_N counter update, despite the state of PLL1 Digital Lock Detect. If the user is unsure of the state of the reference clock input at startup of the LMK040xx device, setting RC_DLD1_Start = 0 will allow PLL2 to tune and lock the internal VCO to the oscillator attached to the OSCin port. This ensures that the active clock outputs will start up at frequencies close to their desired values. The error in clock output frequency will depend on the open loop accuracy of the oscillator driving the OSCin port. The frequency of an active clock output is normally given by: FCLK = N R FOSCin A (VCO_DIV A CLK_DIV) If the open loop frequency accuracy of the external oscillator (either a VCXO or crystal based oscillator) is "X" ppm, then the error in the output clock frequency (FCLK error) will be: FCLK error = 34 Submit Documentation Feedback N R X A FOSCin A (VCO_DIV A CLK_DIV) Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Setting this bit to 0 does not prevent PLL1 from locking the external oscillator to the reference clock input after the latter input becomes valid. Register 11 CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer Mode Control The user may choose between one of two input buffer modes for the PLL1 reference clock inputs: either bipolar junction differential or MOS. Both CLKinX and CLKinX* input pins must be AC coupled when driven differentially. In single ended mode, the CLKinX* pin must be coupled to ground through a capacitor. The active CLKinX buffer mode is selected by the CLKinX_TYPE bits programmed via the uWire interface. Table 12. PLL1 CLKinX_BUFTYPE Mode Control Bits b1 b0 CLKin1_TYPE CLKin0_TYPE 0 0 BJT Differential BJT Differential 0 1 BJT Differential MOS 1 0 MOS BJT Differential 1 1 MOS MOS CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits This register allows the user to set the reference clock input that is used to lock PLL1, or to select an autoswitching mode. The automatic switching modes are revertive or non-revertive. In either revertive or nonrevertive mode, CLKin0 is the initial default reference source for the auto-switching mode. When revertive mode is active, the switching control logic will always select CLKin0 as the reference if it is active, otherwise it selects CLKin1. When non-revertive mode is active, the switching logic will only switch the reference input if the currently selected input fails. Table 13 illustrates the control modes. Modes [1,0] and [1,1] are the auto-switching modes. The behavior of both modes is tied to the state of the LOS signals for the respective reference clock inputs. If the reference clock inputs are active prior to configuration of the device, then the normal programming sequence described under General Programming Information can be used without modification. If it cannot be guaranteed that the reference clocks are active prior to device programming, then the device programming sequence should be modified in order to ensure that CLKin0 is selected as the default. Under this scenario, the device should be programmed as described in General Programming Information, with CLKin_SEL bits programmed to [0,0] in register R11. The other R11 fields for clock type and LOS timeout should be programmed with the appropriate values for the given application. After the reference clock inputs have started, register R11 should be programmed a second time with the CLKin_SEL field modified to the set the desired mode. The clock type field and LOS field values should remain the same. Table 13. CLKin_SEL: Reference Clock Selection Bits CLKin_SEL [1:0] Function b1 b0 0 0 Force CLKin0 / CLKin0* as PLL1 reference 0 1 Force CLKin1 / CLKin1* as PLL1 reference 1 0 Non-revertive. Auto-switching. CLKin0 is the default reference clock. If CLKin0 fails, CLKin1 is automatically selected if active. If CLKin0 restarts, CLKin1 remains as the selected reference clock unless it fails, then CLKin0 is re-selected. 1 1 Revertive. Auto-switching. CLKin0 is the preferred reference clock and is selected when active. CLKinX_LOS The CLKin0_LOS and CLKin1_LOS pins indicate the state of the respective PLL1 CLKinX reference input when the CLKin_SEL bits are set set to either [1,0] or [1,1]. The detection logic that determines the state of the reference inputs is sensitive to the frequency of the reference inputs and must be configured to operate with the appropriate frequency range of the reference inputs, as described in the next section. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 35 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com PLL1 Reference Clock LOS Timeout Control This register is used to tune the LOS timeout based upon the frequency of the reference clock input(s). The register value controls the timeout setting for both CLKin0 and CLKin1. The value programmed in the LOS_TIMEOUT register represents the minimum input frequency for which loss of signal can be detected. For example, if the reference input frequency is 12.288 MHz, then either register values (0,0) or (0,1) will result in valid loss of signal detection. If the reference input frequency is 1 MHz, then only the register value (0,0) will result in valid detection of signal loss. Table 14. Reference Clock LOS Timeout Control Bits b1 b0 Corresponding Minimum Input Frequency 0 0 1 MHz 0 1 3.0 MHz 1 0 13 MHz 1 1 32 MHz LOS Output Type Control The output format of the LOS pins may be selected as active CMOS, open drain NMOS and open drain PMOS, as shown in the following table. Table 15. Loss of Signal (LOS) Output Pin Format Type LOS_TYPE [1:0] Functional Description b1 b0 0 0 Reserved 0 1 NMOS open drain 1 0 PMOS open drain 1 1 Active CMOS The LOS output signal is valid only when CLKin_SEL bits are set to either [1,0] or [1,1]. If the CLKin_SEL field is programmed to either of the fixed inputs, [0,0] or [0,1], the LOS_TYPE bits should be set to [0,0]. Register 12 PLL1_N: PLL1_N Counter The size of the PLL1_N counter is 12 bits. This counter will support a maximum divide ratio of 4095 and minimum divide ratio of 1. The 12 bit resolution is sufficient to support minimum phase detector frequency resolution of approximately 50 kHz when the VCXO frequency is 200 MHz. For a 200 MHz external VCXO, the minimum phase detector rate will be PDmin = 200 MHz/4095 = 48.84 kHz Table 16. PLL1_N Counter Values N [17:0] 36 ... VALUE b11 b10 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 Not Valid 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 2 . . . . . . . 1 1 1 Submit Documentation Feedback ... 4095 Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 PLL1_R: PLL1_R Counter The size of the PLL1_R counter is 12 bits. This counter will support a maximum divide ratio of 4095 and minimum divide ratio of 1. Table 17. PLL1_R Counter Values R [11:0] VALUE b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 Not Valid 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . . . ... 1 1 1 1 1 1 1 1 1 1 1 1 4095 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control (PLL1_CP_POL) The Loop Band Width (LBW) on PLL1 should be narrow to suppress the noise from the system or input clocks at CLKinX/CLKinX* port. This configuration allows the noise of the external VCXO to dominate at low offset frequencies. Given that the noise of the external VCXO is far superior than the noise of PLL1, this setting produces a very clean reference clock to PLL2 at the OSCin port. In order to achieve a LBW as low as 10 Hz at the supported VCXO frequency (1 MHz to 200 MHz), a range of charge pump currents in PLL1 is provided. The table below shows the available current gains. A small charge pump current is required to obtain a narrow LBW at high phase detector rate (small N value). Table 18. PLL1 Charge Pump Current Selections (PLL1_CP_GAIN) PLL1_CP_GAIN [2:0] PLL1 Charge Pump Current Magnitude (A) b2 b1 b0 0 0 0 RESERVED 0 0 1 RESERVED 0 1 0 20 0 1 1 80 1 0 0 25 1 0 1 50 1 1 0 100 1 1 1 400 The PLL1_CP_POL bit sets the PLL1 charge pump for operation with a positive or negative slope VCO/VCXO. A positive slope VCO/VCXO increases frequency with increased tuning voltage. A negative slope VCO/VCXO increases frequency with decreased tuning voltage. Table 19. PLL1 Charge Pump Polarity Control Bits (PLL1_CP_POL) PLL1_CP_POL DESCRIPTION 0 Negative Slope VCO/VCXO 1 Positive Slope VCO/VCXO Register 13 EN_PLL2_XTAL: Crystal Oscillator Option Enable If an external crystal is being used to implement a discrete VCXO, the internal feedback amplifier must be enabled in order to complete the oscillator circuit. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 37 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Table 20. EN_PLL2_XTAL: External Crystal Option EN_PLL2_XTAL Oscillator Amplifier State 0 OFF 1 ON EN_Fout: Fout Power Down Bit The EN_Fout bit allows the Fout port to be enabled or disabled. By default EN_Fout = 0. CLK Global Enable: Clock Global enable bit In addition to the external GOE pin, an internal Register 13 bit (b18) can be used to globally enable/disable the clock outputs via the uWire programming interface. The default value is 1. When CLK Global Enable = 1, the active output clocks are enabled. The active output clocks are disabled if this bit is 0. POWERDOWN Bit -- Device Power Down This bit can power down the entire device. Enabling this bit powers down the entire device and all functional blocks, regardless of the state of any of the other bits or pins. Table 21. Power Down Bit Values POWERDOWN Bit Mode 0 Normal Operation 1 Entire device powered down EN_PLL2 REF2X: PLL2 Frequency Doubler control bit When FOSCin is below 50 MHz, the PLL2 frequency doubler can be enabled by setting EN_PLL2_REF2X = 1. The default value is 0. When EN_PLL2_REF2X = 1, the signal at the OSCin port bypasses the PLL2_R counter and is passed through a frequency doubler circuit. The output of this circuit is then input to the PLL2 phase comparator block. This feature allows the phase comparison frequency to be increased for lower frequency OSCin sources (< 50 MHz), and can be used with either VXCOs or crystals. For instance, when using a pullable crystal of 12.288 MHz to drive the OSCin port, the PLL2 phase comparison frequency is 24.576 MHz when EN_PLL2_REF2X = 1. A higher PLL phase comparison frequency reduces PLL2 in-band phase noise and RMS jitter. The PLL in-band phase noise can be reduced by approximately 2 to 3 dB. The on-chip loop filter typically is enabled to reduce PLL2 reference spurs when EN_PLL2_REF2X is enabled. Suggested values in this case are: R3 = 600 , C3 = 50 pF, R4 = 10 k, C4 = 60 pF. PLL2 Internal Loop Filter Component Values Internal loop filter components are available for PLL2, enabling the user to implement either 3rd or 4th order loop filters without requiring external components. The user may select from a fixed set of values for both the resistors and capacitors. Internal loop filter resistance values for R3 and R4 can be set individually according to Table 22 and Table 23. Table 22. PLL2 Internal Loop Filter Resistor Values, PLL2_R3_LF PLL2_R3_LF [2:0] 38 RESISTANCE b2 b1 b0 0 0 0 < 600 0 0 1 10 k 0 1 0 20 k 0 1 1 30 k 1 0 0 40 k 1 0 1 Invalid 1 1 0 Invalid 1 1 1 Invalid Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Table 23. PLL2 Internal Loop Filter Resistor Values, PLL2_R4_LF PLL2_R4_LF [2:0] RESISTANCE b2 b1 b0 0 0 0 < 200 0 0 1 10 k 0 1 0 20 k 0 1 1 30 k 1 0 0 40 k 1 0 1 Invalid 1 1 0 Invalid 1 1 1 Invalid Internal loop filter capacitors for C3 and C4 can be set individually according to the following table. Table 24. PLL2 Internal Loop Filter Capacitor Values PLL2_C3_C4_LF [3:0] Loop Filter Capacitance(pF) b3 b2 b1 b0 0 0 0 0 0 0 0 1 C3 = 0, C4 = 60 0 0 1 0 C3 = 50, C4 = 10 0 0 1 1 C3 = 0, C4 = 110 0 1 0 0 C3 = 50, C4 = 110 0 1 0 1 C3 = 100, C4 = 110 0 1 1 0 C3 = 0, C4 = 160 0 1 1 1 C3 = 50, C4 = 160 1 0 0 0 C3 = 100, C4 = 10 1 0 0 1 C3 = 100, C4 = 60 1 0 1 0 C3 = 150, C4 = 110 1 0 1 1 C3 = 150, C4 = 60 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved C3 = 0, C4 = 10 PLL1 CP TRI-STATE and PLL2 CP TRI-STATE The charge pump output of either CPout1 or CPout2 may be placed in a TRI-STATE mode by setting the appropriate PLLx CP TRI-STATE bit. Table 25. PLL1 Charge Pump TRI-STATE bit values PLL1 CP TRI-STATE Description 1 PLL1 CPout1 is at TRI-STATE 0 PLL1 CPout1 is active Table 26. PLL2 Charge Pump TRI-STATE bit values PLL2 CP TRI-STATE Description 1 PLL2 CPout2 is at TRI-STATE 0 PLL2 CPout2 is active Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 39 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Register 14 OSCin_FREQ: PLL2 Oscillator Input Frequency Register The frequency of the PLL2 reference input to the PLL2 Phase Detector (OSCin/OSCin* port) must be programmed in order to support proper operation of the internal VCO tuning algorithm. This is an 8-bit register that sets the frequency to the nearest 1-MHz increment. Table 27. OSCin_FREQ Register Values OSCin_FREQ [7:0] VALUE b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 Not Valid 0 0 0 0 0 0 0 1 1 MHz 0 0 0 0 0 0 1 0 2 MHz . . . . . . . ... 1 1 1 1 1 0 1 0 250 MHz 1 1 0 0 1 0 0 1 Not Valid . . . . . . . . . 1 1 1 1 1 1 1 1 Not Valid PLL2_R: PLL2_R Counter The PLL2 R Counter is 12 bits wide. It divides the PLL2 OSCin/OSCin* clock and is connected to the PLL2 Phase Detector. Table 28. PLL2_R: PLL2_R Counter Values R [11:0] VALUE b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . ... 1 1 1 1 1 1 1 1 1 1 4095 1 1 Not Valid PLL_MUX: LD Pin Selectable Output The signal appearing on the LD pin is programmable via the uWire interface and provides access to several internal signals which may be valuable for either status monitoring during normal operation or for debugging during the hardware development phase. This pin may be forced to either a HIGH or LOW state, and may also be configured as specified in Table 29. 40 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Table 29. PLL_MUX: LD Pin Selectable Outputs PLL_MUX [4:0] LD Output b4 b3 b2 b1 b0 0 0 0 0 0 HiZ 0 0 0 0 1 Logic High 0 0 0 1 0 Logic Low 0 0 0 1 1 PLL2 Digital Lock Detect Active High 0 0 1 0 0 PLL2 Digital Lock Detect Active Low 0 0 1 0 1 PLL2 Analog Lock Detect Push Pull 0 0 1 1 0 PLL2 Analog Lock Detect Open Drain NMOS 0 0 1 1 1 PLL2 Analog Lock Detect Open Drain PMOS 0 1 0 0 0 Reserved 0 1 0 0 1 PLL2_N Divider Output / 2 0 1 0 1 0 Reserved 0 1 0 1 1 PLL2_R Divider Output / 2 0 1 1 0 0 Reserved 0 1 1 0 1 Reserved 0 1 1 1 0 PLL1 Digital Lock Detect Active HIGH 0 1 1 1 1 PLL1 Digital Lock Detect Active LOW 1 0 0 0 0 Reserved 1 0 0 0 1 Reserved 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved 1 0 1 0 0 PLL1_N Divider Output / 2 1 0 1 0 1 Reserved 1 0 1 1 0 PLL1_R Divider Output / 2 1 0 1 1 1 PLL1 and PLL2 Digital Lock Detect 1 1 0 0 0 Inverted PLL1 and PLL2 Digital Lock Detect 1 1 0 0 1 Reserved 1 1 0 1 0 Reserved 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 Reserved 1 1 1 1 0 Reserved 1 1 1 1 1 Reserved Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 41 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Register 15 PLL2_N: PLL2_N Counter The PLL2_N Counter is 18 bits wide. It divides the output of the VCO Divider and is connected to the PLL2 Phase Detector. Each time the PLL2_N Counter value is updated via the uWire interface, an internal algorithm is triggered that optimizes the VCO performance. Table 30. PLL2_N: PLL2_N Counter Values N [17:0] VALUE b17 b16 ... b6 b5 b4 b3 b2 b1 b0 0 0 ... 0 0 0 0 0 0 0 Not Valid 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 2 . . . . . . . ... 1 1 1 1 1 1 1 262143 1 1 PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control The PLL2 charge pump output current level is controlled with the PLL2_CP_GAIN register. The following table presents the charge pump current control values. Table 31. PLL2_CP_GAIN: PLL2 Charge Pump Current Selections PLL2_CP_GAIN [1:0] CP_TRI Charge Pump Current (A) b1 b0 X X 1 Hi-Z 0 0 0 100 0 1 0 400 1 0 0 1600 1 1 0 3200 VCO_DIV: PLL2 VCO Divide Register A divider is provided on the output of the PLL2 VCO to enable a wide range of output clock frequencies. The output of this divider is placed on the input path for the clock distribution section, which feeds each of the individual clock channels. The divider provides integer divide ratios from 2 to 8. Table 32. VCO_DIV: PLL2 VCO Divider Values VCO_DIV [3:0] 42 Divide Value b3 b2 b1 b0 0 0 0 0 Invalid 0 0 0 1 Invalid 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 APPLICATION INFORMATION System Level Diagram The following diagram illustrates the typical interconnection of the LMK040xx in a clocking application. 120O 0.1 PF To System To System 0.1 PF 120O 120O 0.1 PF To System 100 pF 100 pF To System CLKout1* CLKout1 CLKout2B CLKout2A CLKout3* CLKout3 CLKout4* CLKout4 To System 0.1 PF 120O Vcc 1 PF Fout Bias PLL2 Loop Filter CPout2 51O LD (optional) GOE To Host 0.1 uF OSCin* LEuWire OSCin LMK040xx CLKuWire 0.1 PF 33 pF 33 pF 33 pF DATAuWire To Host CLKin1* LDObyp1 CLKin1 Rterm VCXO SYNC* 0.1 PF 100 O LDObyp2 0.1 PF CPout1 CLKin0* DLD_BYP CLKout0 CLKout0* 0.1 PF CLKin0 0.1 PF 10 PF Reference Clock #2 (Secondary) PLL1 Loop Filter 0.1 PF 0.47 PF 100O To System Reference Clock #1 (Primary) Figure 13. Typical Application Figure 13 shows an LMK04000 family device with external circuitry. The primary reference clock input is at CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC coupled differential drivers. The VCXO attached to the OSCin/OSCin* port is configured as an AC coupled single-ended driver. Any of the input ports (CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured as either differential or singleended. These options are discussed later in the data sheet. The diagram shows an optional connection between the LD pin and GOE. With this arrangement, the LD pin can be programmed to output a lock detect signal that is active HIGH (see Table 29 for optional LD pin outputs). If lock is lost, the LD pin will transition to a LOW, pulling GOE low and causing all clock outputs to be disabled. This scheme should be used only if disabling the clock outputs is desirable when lock is lost. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 43 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com The loop filter for PLL2 consists of three external components that implement two lower order poles, plus optional internal integrated components if 3rd or 4th order poles are needed. The loop filter components for PLL1 must be external components. The VCO output buffer signal that appears at the Fout pin when enabled (EN_Fout = 1) should be AC coupled using a 100 pF capacitor. This output is a single-ended signal by default. If a differential signal is required, a 50 balun may be connected to this pin to convert it to differential. The clock outputs are all AC coupled with 0.1 F capacitors. CLKout1 and CLKout3 are depicted as LVPECL, with 120 emitter resistors as source termination. However, the output format of the clock channels will vary by device part number, so the designer should use the appropriate source termination for each channel. Later sections of this data sheet illustrate alternative methods for AC coupling, DC coupling and terminating the clock outputs. LDO Bypass And Bias Pin The LDObyp1 and LDObyp2 pins should be connected to GND through external capacitors, as shown in the diagram. Furthermore, the Bias pin should be connected to VCC through a 1 F capacitor in series. Loop Filter Each PLL of the LMK04000 family requires a dedicated loop filter. The loop filter for PLL1 must be connected to the CPout1 pin. Figure 14 shows a simple 2-pole loop filter. The output of the filter drives an external VCXO module or discrete implementation of a VCXO using a crystal resonator. Higher order loop filters may be implemented using additional external R and C components. It is recommended the loop filter for PLL1 result in a total closed loop bandwidth in the range of 10 Hz to 200 Hz. The design of the loop filter is application specific and highly dependent on parameters such as the phase noise of the reference clock, VCXO phase noise, and phase detector frequency for PLL1. National's Clock Conditioner Owner's Manual covers this topic in detail and National's Clock Design Tool can be used to simulate loop filter designs for both PLLs. These resources may be found: http://www.national.com/timing/. As shown in the diagram, the charge pump for PLL2 is directly connected to the optional internal loop filter components, which are normally used only if either a third or fourth pole is needed. The first and second poles are implemented with external components. The loop must be designed to be stable over the entire applicationspecific tuning range of the VCO. The designer should note the range of KVCO listed in the table of Electrical Characteristics and how this value can change over the expected range of VCO tuning frequencies. Because loop bandwidth is directly proportional to KVCO, the designer should model and simulate the loop at the expected extremes of the desired tuning range, using the appropriate values for KVCO. When designing with the integrated loop filter of the LMK04000 family, considerations for minimum resistor thermal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4. Both the integrated loop filter resistors and capacitors (C3 and C4) also restrict the maximum loop bandwidth. However, these integrated components do have the advantage that they are closer to the VCO and can therefore filter out some noise and spurs better than external components. For this reason, a common strategy is to minimize the internal loop filter resistors and then design for the largest internal capacitor values that permit a wide enough loop bandwidth. In situations where spurs requirements are very stringent and there is margin on phase noise, it might make sense to design for a loop filter with integrated resistor values larger than their minimum value. 44 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 LMK040xx Internal VCO PLL2 Internal Loop Filter R3 R4 PLL2 Phase Detector C4 CPout2 C3 C2 PLL2 External Loop Filter C1 R2 LMK040xx External VCXO PLL1 Phase Detector CPout1 C2 C1 R2 PLL1 External Loop Filter Figure 14. Loop Filter Table 33. Typical Current Consumption for Selected Functional Blocks Typical ICC (Temp = 25 C, VCC = 3.3 V) (mA) Power Dissipated in device (mW) Power Dissipated in LVPECL/2VPECL Emitter Resistors (mW) Block Condition Entire device, core current Single input clock (CLKIN_SEL = 0 or 1); LOS disabled; PLL1 and PLL2 locked; All CLKouts are off; No LVPECL emitter resistors connected 115 380 - REFMUX Enable auto-switch mode (CLKIN_SEL = 2 or 3) 4.3 14 - LOS Enable LOS (LOS_TYPE = 1, or 2, or 3) 3.6 12 - Low Channel Internal Buffer The low channel internal buffer is enabled when CLKout0 is enabled 10 33 - High Channel Internal Buffer The high channel internal buffer is enabled when one of CLKout1 through CLKout4 is enabled 10 33 - Divider bypassed (CLKout_MUX = 0, 2) Divide circuitry per output 0 0 - Divider enabled, divide = 2 (CLKout_MUX = 1, 3) 5.3 17 - Divider enabled, divide > 2 (CLKout_MUX = 1, 3) 8.5 28 - Delay bypassed (CLKout_MUX = 0, 1) Delay circuitry per Delay enabled, delay < 8 (CLKout_MUX = 2, 3) output Delay enabled, delay > 7 (CLKout_MUX = 2, 3) 0 0 - 5.8 19 - 9.9 33 - Fout Buffer EN_Fout = 1 14.5 48 - LVDS Buffer LVDS buffer, enabled 19.3 64 - Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 45 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Table 33. Typical Current Consumption for Selected Functional Blocks (continued) Block Condition LVPECL/2VPECL buffer (enabled and with 120 emitter resistors) LVPECL/2VPECL LVPECL/2VPECL buffer (disabled and with 120 emitter Buffer resistors) LVPECL/2VPECL (disabled and with no emitter resistors) LVCMOS Buffer (1) (2) (3) Power Dissipated in device (mW) Power Dissipated in LVPECL/2VPECL Emitter Resistors (mW) 40 82 50 21.7 47 25 0 0 - LVCMOS buffer static ICC, CL = 5 pF 4.5 15 - LVCMOS buffer dynamic ICC, CL = 5 pF, CLKout = 100 MHz Entire device LMK0400x (Single input clock LMK0401x (CLKIN_SEL = 0 LMK0403x or 1); LOS disabled; PLL1 and PLL2 locked; Fout disabled; All CLKouts are on; No delay); Divide > 2 on each output. (1) Typical ICC (Temp = 25 C, VCC = 3.3 V) (mA) 16 53 - (2) (3) 379.5 1102 150 (2) (3) 377.5 996 250 337.1 1012 100 (2) (3) Dynamic power dissipation of LVCMOS buffer varies with output frequency and can be found in the LVCMOS dynamic ICC vs frequency plot, as shown in Typical Performance Characteristics. Total power dissipation of the LVCMOS buffer is the sum of static and dynamic power dissipation. CLKoutXa and CLKoutXb are each considered an LVCMOS buffer. Assuming ThetaJ = 27.4 C/W, the total power dissipated on chip must be less than 40/27.4 = 1450 mW to guarantee a junction temperature is less than 125 C. Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.2. Current Consumption / Power Dissipation Calculations Due to the myriad of possible configurations the following table serves to provide enough information to allow the user to calculate estimated current consumption of the device. Unless otherwise noted VCC = 3.3 V, TA = 25 C. From Table 33 the current consumption can be calculated in any configuration. For example, the current for the entire device with 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) output in bypassed mode can be calculated by adding up the following blocks: core current, clock buffer, one LVDS output buffer current, and one LVPECL output buffer current. There will also be one LVPECL output drawing emitter current, but some of the power from the current draw is dissipated in the external 120 resistors which doesn't add to the power dissipation budget for the device. If delays or divides are switched in, then the additional current for these stages needs to be added as well. For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) operating at 3.3 V, we calculate 3.3 V x (115 + 10 + 10 + 19.3 + 40) mA = 3.3 V x 194.3 mA = 641.2 mW. Because the LVPECL output (CLKout1) has the emitter resistors hooked up and the power dissipated by these resistors is 50 mW, the total device power dissipation is 641.2 mW - 50 mW = 591.2 mW. When the LVPECL output is active, ~1.7 V is the average voltage on each output as calculated from the LVPECL VOH & VOL typical specification. Therefore the power dissipated in each emitter resistor is approximately (1.7 V)2 / 120 = 25 mW. When the LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the power dissipated in each emitter resistor is approximately (1.07 V)2 / 120 = 9.5 mW. 46 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Power Supply Conditioning The recommended technique for power supply management is to connect the power pins for the clock outputs (pins 13, 37, 40, 43, and 46) to a dedicated power plane and connect all other power pins on the device (pins 3, 8, 18, 19, 22, 24, 30, 31, and 33) to a second power plane. Note: the LMK04000 family has internal voltage regulators for the PLL and VCO blocks to provide noise immunity. Thermal Management Power consumption of the LMK04000 family of devices can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 C. That is, as an estimate, TA (ambient temperature) plus device power consumption times JA should not exceed 125 C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 15. More information on soldering WQFN packages can be obtained: http://www.national.com/analog/packaging/. 5.0 mm, min 0.33 mm, typ 1.2 mm, typ Figure 15. Recommended Land and Via Pattern To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 15 should connect these top and bottom copper layers and to the ground layer. These vias act as "heat pipes" to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 47 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com OSCin* Copt CC1 = 2.2 nF R1 = 4.7k SMV1249-074LF R3 = 10k LMK040xx XTAL 1 nF R2 = 4.7k CC2 = 2.2 nF OSCin CPout1 Copt PLL1 Loop Filter Figure 16. Reference Design Circuit for Crystal Oscillator Option Optional Crystal Oscillator Implementation (OSCin/OSCin*) The LMK04000 family features supporting circuitry for a discretely implemented oscillator driving the OSCin port pins. Figure 16 illustrates a reference design circuit for a crystal oscillator: This circuit topology represents a parallel resonant mode oscillator design. When selecting a crystal for parallel resonance, the total load capacitance, CL, must be specified. The load capacitance is the sum of the tuning capacitance (CTUNE), the capacitance seen looking into the OSCin port (CIN), and stray capacitance due to PCB parasitics (CSTRAY), and is given by: CL = CTUNE + CIN + CSTRAY 2 CTUNE is provided by the varactor diode shown in Figure 16, Skyworks model SMV1249-074. A dual diode package with common cathode and provides the variable capacitance for tuning. The single diode capacitance ranges from approximately 31 pF at 0.3 V to 3.4 pF at 3 V. The capacitance range of the dual package (anode to anode) is approximately 15.5 pF at 3 V to 1.7 pF at 0.3 V. The desired value of VTUNE applied to the diode should be VCC/2, or 1.65 V for VCC = 3.3 V. The typical performance curve from the data sheet for the SMV1249-074 indicates that the capacitance at this voltage is approximately 6 pF (12 pF/2). The nominal input capacitance (CIN) of the LMK04000 family OSCin pins is 6 pF. The stray capacitance (CSTRAY) of the PCB should be minimized by arranging the oscillator circuit layout to achieve trace lengths as short as possible and as narrow as possible trace width (50 characteristic impedance is not required). As an example, assume that CSTRAY is 4 pF. The total load capacitance is nominally: CL = 6 + 6 + 4 = 14 pF 2 Consequently the load capacitance specification for the crystal in this case should be nominally 14 pF. 48 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 The 2.2 nF capacitors shown in the circuit are coupling capacitors that block the DC tuning voltage applied by the 4.7 k and 10 k resistors. The value of these coupling capacitors should be large, relative to the value of CTUNE (CC1 = CC2 >> CTUNE), so that CTUNE becomes the dominant capacitance. For a specific value of CL, the corresponding resonant frequency (FL) of the parallel resonant mode circuit is: 1 FL = FS A C1 2(C0 + CL1) + 1 = FS A C0 2 (c) C1 + CL * +1 C1 FS = Series resonant frequency C1 = Motional capacitance of the crystal CL = Load capacitance C0 = Shunt capacitance of the crystal, specified on the crystal datasheet The normalized tuning range of the circuit is closely approximated by: 1 'F FCL1 - FCL2 C1 = = F 2 FFCL1 A 1 1 1 = (C0 + CL1) (C0 + CL2) 2 A C0 C1 (c) + - C0 C1 (c) C1 CL1* 1 + CL2* C1 CL1, CL2 = The endpoints of the circuit's load capacitance range, assuming a variable capacitance element is one component of the load. FCL1, FCL2 = parallel resonant frequencies at the extremes of the circuit's load capacitance range. A common range for the pullability ratio, C0/C1, is 250 to 280. The ratio of the load capacitance to the shunt capacitance is ~(n * 1000), n < 10. Hence, picking a crystal with a smaller pullability ratio supports a wider tuning range because this allows the scale factors related to the load capacitance to dominate. Examples of the phase noise and jitter performance of the LMK04031 with a crystal oscillator are shown in Table 34. This table illustrates the clock output phase noise when a 12.288 MHz crystal is paired with PLL1. Table 34. Example RMS Jitter and Clock Output Phase Noise for LMK04031 with a 12.288 MHz Crystal Driving OSCin (T = 25 C, VCC = 3.3 V) (1) RMS Jitter (ps) Integration Bandwidth Clock Output Type FCLK = 122.88 MHz FCLK = 153.6 MHz FCLK = 122.88 MHz 100 Hz - 20 MHz LVPECL 0.279 0.263 0.300 LVCMOS 0.244 0.248 0.218 LVDS 0.272 0.269 0.245 LVPECL 0.251 0.234 0.284 LVCMOS 0.211 0.215 0.193 LVDS 0.236 0.235 0.217 10 kHz - 20 MHz PLL2 PDF = 12.288 MHz (EN_PLL2_REF2X = 0) PLL2 PDF = 24.576 MHz (EN_PLL2_REF2X = 1) Phase Noise (dBc/Hz) (1) Offset Clock Output Type PLL2 FPD = 12.288 MHz (EN_PLL2_REF2X = 0) PLL2 FPD = 24.576 MHz (EN_PLL2_REF2X = 1) FCLK = 122.88 MHz FCLK = 153.6 MHz FCLK = 122.88 MHz 100 Hz LVPECL -107 -106 -106 LVCMOS -105 -103 -104 LVDS -105 -104 -106 Performance data and crystal specifications contained in this section are based on Ecliptek model ECX-6465, 12.288 MHz. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 49 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Table 34. Example RMS Jitter and Clock Output Phase Noise for LMK04031 with a 12.288 MHz Crystal Driving OSCin (T = 25 C, VCC = 3.3 V) (1) (continued) 1 kHz LVPECL -126 -124 -130 LVCMOS -125 -124 -127 LVDS -126 -123 -126 LVPECL -125 -124 -131 LVCMOS -127 -125 -128 LVDS -126 -124 -131 10 kHz 100 kHz LVPECL -134 -133 -134 LVCMOS -135 -133 -134 LVDS -134 -132 -134 1 MHz LVPECL -155 -154 -154 LVCMOS -157 -155 -155 LVDS -155 -153 -154 10 MHz LVPECL -158 -158 -158 LVCMOS -160 -159 -159 LVDS -158 -158 -157 Example crystal specifications are presented in Table 35. Table 35. Example Crystal Specifications Parameter Value Nominal Frequency (MHz) 12.288 Frequency Stability, T = 25 C 10 ppm Operating temperature range -40 C to +85 C Frequency Stability, -40 C to +85 C 15 ppm Load Capacitance 14 pF Shunt Capacitance (C0) 5 pF Maximum Motional Capacitance (C1) 20 fF 30% 25 Maximum Equivalent Series Resistance Drive level 2 mWatts Maximum C0/C1 ratio 225 typical, 250 Maximum ppm See Figure 17 for a representative tuning curve. 180 140 100 60 20 -20 -60 -100 -140 -180 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VTUNE (VDC) Figure 17. Example Tuning Curve, 12.288 MHz Crystal 50 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 The tuning curve achieved in the user's application may differ from the curve shown above due to differences in PCB layout and component selection. This data is measured on the bench with the crystal integrated with the LMK04000 family. Using a voltmeter to monitor the VTUNE node for the crystal, the PLL1 reference clock input frequency is swept in frequency and the resulting tuning voltage generated by PLL1 is measured at each frequency. At each value of the reference clock frequency, the lock state of PLL1 should be monitored to ensure that the tuning voltage applied to the crystal is valid. The curve shows over the tuning voltage range of 0.17 VDC to 3.0 VDC, the frequency range is 163 ppm; or equivalently, a crystal frequency range of 2000 Hz. The measured tuning voltage at the nominal crystal frequency (12.288 MHz) is 1.4 V. Using the diode data sheet tuning characteristics, this voltage results in a tuning capacitance of approximately 6.5 pF. The tuning curve data can be used to calculate the gain of the oscillator (KVCO). The data used in the calculations is taken from the most linear portion of the curve, a region centered on the crossover point at the nominal frequency (12.288 MHz). For a well designed circuit, this is the most likely operating range. In this case, the tuning range used for the calculations is 1000 Hz ( 0.001 MHz), or 81.4 ppm. The simplest method is to calculate the ratio: KVCO = 'F = 'V 'F2 - 'F1 * MHz VTUNE2 - VTUNE1 , V (c) F2 and F1 are in units of MHz. Using data from the curve this becomes: 0.001 - (-0.001) MHz = 0.00164 2.03 - 0.814 V A second method uses the tuning data in units of ppm: KVCO = FNOM A ('ppm2 - 'ppm1) 'V A 10 6 FNOM is the nominal frequency of the crystal and is in units of MHz. Using the data, this becomes: 12.288 A (81.4 - (-81.4)) (2.03 - 0.814) A 10 6 = 0.00164, MHz V In order to ensure startup of the oscillator circuit, the equivalent series resistance (ESR) of the selected crystal should conform to the specifications listed in the table of Electrical Characteristics. It is also important to select a crystal with adequate power dissipation capability, or drive level. If the drive level supplied by the oscillator exceeds the maximum specified by the crystal manufacturer, the crystal will undergo excessive aging and possibly become damaged. Drive level is directly proportional to resonant frequency, capacitive load seen by the crystal, voltage and equivalent series resistance (ESR). For more complete coverage of crystal oscillator design, see Application Note AN-1939 at http://www.national.com/analog/timing/clocking or http://www.national.com/appnotes. Termination and use of Clock Output (Drivers) When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance: * Transmission line theory should be followed for good impedance matching to prevent reflections. * Clock drivers should be presented with the proper loads. For example: - LVDS drivers are current drivers and require a closed current loop. - LVPECL drivers are open emitters and require a DC path to ground. * Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level. In this case, the signal should normally be AC coupled. Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 51 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com It is possible to drive a non-LVPECL or non-LVDS receiver with an LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK04000 family, OSCin/OSCin* should be AC coupled because OSCin/OSCin* biases the signal to the proper DC level (See Figure 13) This is only slightly different from the AC coupled cases described in Driving CLKin Pins with a Single-Ended Source because the DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains the same. The receiver (OSCin/OSCin*) sets the input to the optimum DC bias voltage (common mode voltage), not the driver. Termination for DC Coupled Differential Operation For DC coupled operation of an LVDS driver, terminate with 100 as close as possible to the LVDS receiver as shown in Figure 18. 100: CLKoutX 100: Trace (Differential) LVDS Driver LVDS Receiver CLKoutX* Figure 18. Differential LVDS Operation, DC Coupling, No Biasing of the Receiver For DC coupled operation of an LVPECL driver, terminate with 50 to VCC - 2 V as shown in Figure 19. Alternatively terminate with a Thevenin equivalent circuit (120 resistor connected to VCC and an 82 resistor connected to ground with the driver connected to the junction of the 120 and 82 resistors) as shown in Figure 20 for VCC = 3.3 V. 50: Vcc - 2 V CLKoutX 100: Trace (Differential) LVPECL Driver LVPECL Receiver 50: CLKoutX* Vcc - 2 V Figure 19. Differential LVPECL Operation, DC Coupling 82: 120: Vcc CLKoutX 100: Trace (Differential) LVPECL Driver LVPECL Receiver 82: 120: CLKoutX* Vcc Figure 20. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent 52 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 Termination for AC Coupled Differential Operation AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level. When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do this is with the termination circuitry in Figure 21. LVDS Driver 100: Trace (Differential) 50: 0.1 PF CLKoutX LVDS Receiver 50: Vbias CLKoutX* 0.1 PF Figure 21. Differential LVDS Operation, AC Coupling, External Biasing at the Receiver Some LVDS receivers may have internal biasing on the inputs. In this case, the circuit shown in Figure 21 is modified by replacing the 50 terminations to Vbias with a single 100 resistor across the input pins of the receiver, as shown in Figure 22. When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output due to capacitor charging. The previous figures employ a 0.1 F capacitor. This value may need to be adjusted to meet the startup requirements for a particular application. LVDS Driver 100: 0.1 PF 100: Trace (Differential) LVDS Receiver 0.1 PF Figure 22. LVDS Termination for a Self-Biased Receiver LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 emitter resistors close to the LVPECL driver to provide a DC path to ground as shown in Figure 23. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82 resistor connected to VCC and a 120 resistor connected to ground with the driver connected to the junction of the 82 and 120 resistors) is a valid termination as shown in Figure 23 for VCC = 3.3 V. Note this Thevenin circuit is different from the DC coupled example in Figure 20. 82: 120: CLKoutX* 120: 0.1 PF 100: Trace (Differential) LVPECL Receiver 120: 0.1 PF LVPECL Driver 82: CLKoutX 120: Vcc Vcc Figure 23. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent, External Biasing at the Receiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 53 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com Termination for Single-Ended Operation A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal. It is possible to use an LVPECL driver as one or two separate 800 mVpp signals. When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused driver. When DC coupling one of the LMK04000 family clock LVPECL drivers, the termination should be 50 to VCC - 2 V as shown in Figure 24. The Thevenin equivalent circuit is also a valid termination as shown in Figure 25 for Vcc = 3.3 V. 50: Vcc - 2V CLKoutX 50: Trace LVPECL Driver Vcc - 2V CLKoutX* Load 50: Figure 24. Single-Ended LVPECL Operation, DC Coupling CLKoutX Vcc 50: Trace 120: LVPECL Driver Load 82 : CLKoutX* 82: 120: Vcc Figure 25. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent 120: CLKoutX* 50: Trace 0.1 PF 50: 0.1 PF LVPECL Driver 50: CLKoutX 120: When AC coupling an LVPECL driver use a 120 emitter resistor to provide a DC path to ground and ensure a 50 termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL receivers is 2 V (See Driving CLKin Pins with a Single-Ended Source). If the companion driver is not used it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a singleended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias point (0 VDC) is required for safe and proper operation. The internal 50 termination of the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 26. Load Figure 26. Single-Ended LVPECL Operation, AC Coupling 54 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 DRIVING CLKin AND OSCin INPUTS Driving CLKin Pins with a Differential Source Both CLKin ports can be driven by differential signals. It is recommended that the input mode be set to bipolar (CLKinX_TYPE = 0) when using differential reference clocks. The LMK04000 family internally biases the input pins so the differential interface should be AC coupled. The recommended circuits for driving the CLKin pins with either LVDS or LVPECL are shown in Figure 27 and Figure 28. Figure 27. CLKinX/X* Termination for an LVDS Reference Clock Source Figure 28. CLKinX/X* Termination for an LVPECL Reference Clock Source Finally, a reference clock source that produces a differential sinewave output can drive the CLKin pins using the following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in the Electrical Characteristics table. 100: Trace (Differential) Differential Sinewave Clock Source 100: CLKinX 0.1 PF 0.1 PF LMK040XX Input CLKinX* Figure 29. CLKinX/X* Termination for a Differential Sinewave Reference Clock Source Driving CLKin Pins with a Single-Ended Source The CLKin pins of the LMK04000 family can be driven using a single-ended reference clock source, for example, either a sinewave source or an LVCMOS/LVTTL source. Either AC coupling or DC coupling may be used. In the case of the sinewave source that is expecting a 50 load, it is recommended that AC coupling be used as shown in the circuit below with a 50 termination.. NOTE The signal level must conform to the requirements for the CLKin pins listed in the Electrical Characteristics table. CLKinX_TYPE in Register 11 is recommended to be set to bipolar mode (CLKinX_TYPE = 0). Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 55 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com 0.1 PF Clock Source CLKinX 50: 50: Trace 0.1 PF LMK040XX CLKinX* Figure 30. CLKinX/X* Single-ended Termination If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC coupling may be used. If DC coupling is used, the CLKinX_TYPE should be set to MOS buffer mode (CLKinX_TYPE = 1) and the voltage swing of the source must meet the specifications for DC coupled, MOSmode clock inputs given in the table of Electrical Characteristics. If AC coupling is used, the CLKinX_TYPE should be set to the bipolar buffer mode (CLKinX_TYPE = 0). The voltage swing at the input pins must meet the specifications for AC coupled, bipolar mode clock inputs given in the table of Electrical Characteristics. In this case, some attenuation of the clock input level may be required. A simple resistive divider circuit before the AC coupling capacitor is sufficient. Figure 31. DC Coupled LVCMOS/LVTTL Reference Clock Additional Outputs with an LMK04000 Family Device The number of outputs on a LMK04000 family device can be expanded in many ways. The first method is to use the differential outputs as two single-ended outputs. For CMOS outputs, both the positive and negative outputs can be programmed to be in phase, or 180 degrees out of phase. LVDS/LVPECL positive and negative outputs are always 180 degrees out of phase. LVDS single-ended is not recommended. In addition to this technique, the number of outputs can be expanded with a LMK01000 family device. To do this, one of the clock outputs of a LMK04000 can drive the LMK01000 device. For more information on phase synchronization with multiple devices, please refer to application note AN-1864: http://www.national.com/an/AN/AN-1864.pdf. Output Clock Phase Noise Performance VS. VCXO Phase Noise The jitter cleaning capability of the LMK04000 family is highly dependent on the phase noise performance of the VCXO (or crystal) that is integrated with PLL1. The VCXO is the reference for PLL2 which provides the clock for the output distribution path. Consequently, the designer must choose a VCXO (or crystal) that supports the required performance at the clock outputs. An example of the difference in performance that can be obtained from various VCXOs is illustrated in the following plots. Figure 32 compares the phase noise of two different VCXOs: VCXO "A" and VCXO "B". Both VCXOs have a center frequency of 100 MHz. The figure of merit, RMS jitter, is measured over the bandwidth 100 Hz to 200 kHz. This is the most relevant integration bandwidth for the VCXO because it will have the most impact inside the loop bandwidth of PLL2. 56 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 www.ti.com SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 -90 -100 -110 dBc -120 s yK ^ _ -130 -140 -150 -160 -170 s yK ^ _ -180 100 1000 10000 100000 1000000 10000000 100000000 OFFSET (Hz) Figure 32. VCXO Phase Noise Comparison, 100 MHz This plot shows that VCXO "B" exhibits superior phase noise when compared to VCXO "A". Both VCXOs offer excellent jitter performance from 100 Hz to 200 kHz. VCXO "A" exhibits RMS jitter of 151 femtoseconds (fs), while VCXO "B" has RMS jitter of 90 fs. Figure 33 Figure 34 Figure 35 present a side-by-side comparison of clock output phase noise at 250 MHz, organized by output format and associated VCXO. The total RMS jitter listed on the plots is integrated from 100 Hz to 20 MHz. Examining these plots, the clock output phase noise associated with VCXO "B" is superior in all cases. The average improvement in RMS jitter due to VCXO "B" is approximately 47 fs. The plots show the primary difference in clock output phase noise is in the band from 100 Hz to approximately 4 kHz. Across this range, the VCXO phase noise dominates that of the PLL, given the loop bandwidth of this design, which is 152 kHz. Above 4 kHz, the PLL noise dominates (inside the loop bandwidth), so it is basically the same for either VCXO. Comparing the jitter of two VCXOs in the 100 Hz to 4 kHz band, it can be shown that VCXO "A" exhibits jitter of 142 fs, and VCXO "B" exhibits jitter of 90 fs. The difference, 52 fs, accounts for the majority of the average difference in RMS jitter at the clock outputs when comparing VCXOs. The PLL configurations listed below were the same for both VCXOs/LMK040xx pair: * PLL1 loop filter components: C1 = 100 nF, C2 = 680 nF, R2 = 39 k * PLL1 fPD = 1 MHz, CP gain = 100 A, loop BW = 20 Hz * PLL2 loop filter components: C1 = 0, C2 = 12 nF, R2 = 1.8 k * PLL2 fPD = 25 MHz, CP gain = 3200 A, loop BW = 152 kHz -80 -90 s yK ^ _, RMS jitter = 224 fs -100 dBc -110 -120 -130 -140 -150 s yK ^ _, RMS jitter = 167 fs -160 -170 100 1000 10000 100000 1000000 10000000 100000000 OFFSET (Hz) Figure 33. LVDS Clock Output Phase Noise Comparison, 250 MHz Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 57 LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033 SNOSAZ8J - SEPTEMBER 2008 - REVISED SEPTEMBER 2011 www.ti.com -80 -90 s yK ^ _, RMS jitter = 211 fs -100 dBc -110 -120 -130 -140 -150 s yK ^ _, RMS jitter = 171 fs -160 -170 100 1000 10000 100000 1000000 10000000 100000000 OFFSET (Hz) Figure 34. LVPECL Clock Output Phase Noise Comparison, 250 MHz -80 -90 s yK ^ _, RMS jitter = 209 fs -100 dBc -110 -120 -130 -140 -150 s yK ^ _, RMS jitter = 166 fs -160 -170 100 1000 10000 100000 1000000 10000000 100000000 OFFSET (Hz) Figure 35. LVCMOS Clock Output Phase Noise Comparison, 250 MHz 58 Submit Documentation Feedback Copyright (c) 2008-2011, Texas Instruments Incorporated Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LMK04000BISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04000BI LMK04000BISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04000BI LMK04000BISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04000BI LMK04001BISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04001BI LMK04001BISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04001BI LMK04001BISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04001BI LMK04002BISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04002BI LMK04002BISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04002BI LMK04002BISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04002BI LMK04010BISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04010BI LMK04010BISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04010BI LMK04010BISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04010BI LMK04011BISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04011BI LMK04011BISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04011BI LMK04011BISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04011BI LMK04031BISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04031BI LMK04031BISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04031BI Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LMK04031BISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04031BI LMK04033BISQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04033BI LMK04033BISQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04033BI LMK04033BISQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 K04033BI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 2 Samples PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMK04000BISQ/NOPB WQFN RHS 48 LMK04000BISQE/NOPB WQFN RHS LMK04000BISQX/NOPB WQFN RHS LMK04001BISQ/NOPB WQFN LMK04001BISQE/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04001BISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04002BISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04002BISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04002BISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04010BISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04010BISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04010BISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04011BISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04011BISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04011BISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04031BISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04031BISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04031BISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMK04033BISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04033BISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK04033BISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK04000BISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK04000BISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK04000BISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK04001BISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK04001BISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK04001BISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK04002BISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK04002BISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK04002BISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK04010BISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK04010BISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK04010BISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK04011BISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK04011BISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK04011BISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK04031BISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK04031BISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK04031BISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK04033BISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK04033BISQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 LMK04033BISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 Pack Materials-Page 3 PACKAGE OUTLINE RHS0048A WQFN - 0.8 mm max height SCALE 1.800 PLASTIC QUAD FLATPACK - NO LEAD 7.15 6.85 A B PIN 1 INDEX AREA 0.5 0.3 7.15 6.85 0.30 0.18 DETAIL OPTIONAL TERMINAL TYPICAL 0.8 0.7 C SEATING PLANE 0.05 0.00 0.08 C 2X 5.5 (0.2) 5.1 0.1 (A) TYP 24 13 44X 0.5 DIM A OPT 1 OPT 2 (0.1) (0.2) 12 25 EXPOSED THERMAL PAD 2X 5.5 49 SYMM SEE TERMINAL DETAIL 1 PIN 1 ID (OPTIONAL) 36 48 37 SYMM 48X 0.5 0.3 48X 0.30 0.18 0.1 0.05 C A B 4214990/B 04/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RHS0048A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 5.1) SYMM 37 48 48X (0.6) 1 36 48X (0.25) (1.05) TYP 44X (0.5) (1.25) TYP 49 SYMM (6.8) (R0.05) TYP ( 0.2) TYP VIA 25 12 13 24 (1.25) TYP (1.05) TYP (6.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL EDGE EXPOSED METAL SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4214990/B 04/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN RHS0048A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD (0.625) TYP (1.25) TYP 37 48 48X (0.6) 1 36 49 48X (0.25) 44X (0.5) (1.25) TYP (0.625) TYP SYMM (6.8) (R0.05) TYP METAL TYP 25 12 13 16X ( 1.05) 24 SYMM (6.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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