TLE4275D V33 - Infineon Technologies

Type Package

TLE 4275 D V33 PG-TO252-5-11 (RoHS compliant)

TLE 4275 G V33 PG-TO263-5-1 (RoHS compliant)

PG-TO252-5-11

PG-TO263-5-1

Datasheet 1 Rev. 1.0, 2006-09-22

Linear Voltage Regulator

3.3 V Fixed Output Voltage

TLE 4275 V33

Feature Overview

• Output voltage 3.3 V ± 2 %

• Current capability 400 mA

• Stable with ceramic output capacitor

• Reset circuit functional without supply voltage present

• Reset output active low down to VQ = 1 V

• Reset circuit sensing the output voltage

with programmable delay time

• Maximum input voltage -42 V ≤ VI ≤ +45 V

• ESD Resistivity 4 kV (Human Body Model)

• Reverse polarity protection

• Short circuit protection

• Overtemperature shutdown

• Automotive temperature range -40 °C ≤ Tj ≤ 150 °C

• Green Product (RoHS compliant)

• AEC qualified

The TLE 4275 V33 is a monolithic integrated low dropout fixed

output voltage regulator for loads up to 400mA. An integrated reset

generator with adjustable power-on delay time as well as several

protection circuits predestine the IC for supplying microprocessor

systems in an automotive environment.

Figure 1 Simplified Block Diagram and Typical Application

Reset

Generator

Bandgap

Reference

Protection

Circuits

GND D

Load

e. g.

Micro

Controller

GND

Supply

Regulated

Output

Voltage

B lockDiagram_A ppCircuit1.vsd

TLE 4275 V33

or:

+5V

Datasheet 2 Rev. 1.0, 2006-09-22

TLE 4275 V33

Pin Definitions and Functions

1 Pin Definitions and Functions

Figure 2 Pin Assignment

Pin Symbol Function

1IRegulator Input and IC Supply.

• For compensating line influences, a capacitor to GND close to the IC terminals is

recommended.

2ROReset Output.

• Open collector output. External pull-up resistor to a positive voltage rail required.

• Leave open if the reset function is not needed.

3GNDPG-TO263-5-1 only: Ground Reference.

• Connect to TAB and heatsink area

4DReset Delay Timing.

• Connect a ceramic capacitor to GND for reset delay timing adjustment.

• Leave open if the reset function is not needed.

5QRegulator Output.

• Block to GND with a capacitor close to the IC terminals, respecting capacitance and

ESR requirements given in the table “Functional Range”.

TAB GND PG-TO252-5-11 only: Ground Reference.

• Connect to heatsink area.

TAB – PG-TO263-5-1 only:

• Connect to heatsink area and ground reference (pin 3).

AEP02580

ROΙDQ

GND

IEP02528

PG-TO252-5-11 PG-TO263-5-1

TLE 4275 V33

Electrical Characteristics

Datasheet 3 Rev. 1.0, 2006-09-22

2 Electrical Characteristics

2.1 Absolute Maximum Ratings

Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

-40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground (unless otherwise specified)

Pos. Parameter Symbol Limit Values Unit Conditions

Min. Max.

Regulator Input and IC Supply I

2.1.1 Voltage VI-42 45 V –

2.1.2 Current II––mA

internally limited

Regulator Output Q

2.1.3 Voltage VQ-1 16 V –

2.1.4 Current IQ––mA

internally limited

Reset Output RO

2.1.5 Voltage VRO -0.3 25 V –

2.1.6 Current IRO -5 5 mA

Reset Delay Timing D

2.1.7 Voltage VD-0.3 7 V –

2.1.8 Current ID-2 2 mA

Ground GND

2.1.9 Current IGND ––mA

internally limited

Temperatures

2.1.10 Junction Temperature Tj-40 150 °C–

2.1.11 Storage Temperature Tstg -50 150 °C–

ESD Susceptibility

2.1.12 ESD Resistivity VESD,HBM -4 4 kV HBM1)

1) ESD susceptibility, Human Body Model “HBM” according to EIA/JESD 22-A114B.

2.1.13 VESD,CDM -500 500 V CDM2)

2) ESD susceptibility, Charged Device Model “CDM” according to EIA/JESD22-C101 or ESDA STM5.3.1

Moisture Level

2.1.14 Moisture Level MSL 3––

Datasheet 4 Rev. 1.0, 2006-09-22

TLE 4275 V33

Electrical Characteristics

2.2 Functional Range

Note: Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics table.

2.3 Thermal Resistance

Pos. Parameter Symbol Limit Values Unit Conditions / Remarks

Min. Max.

2.2.1 Input Voltage VI4.4 42 V VQ = VI - Vdr 1)

1) For details on max. output current vs. input voltage see Table 1: Electrical Characteristics Voltage Regulator

2.2.2 Junction Temperature Tj-40 150 °C–

2.2.3 Output Capacitor CQ22 – µF – 2)

2) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%

2.2.4 ESRCQ –3Ω–

Pos. Parameter Symbol Typ.

Value

Unit Conditions

Package P-TO252-5:

2.3.1 Junction – Ambient

PG-TO252-5-11

Rth,j-a 144 K/W Footprint only1)

1) EIA/JESD 52_2, FR4, 80 × 80 × 1.5 mm; 35µ Cu, 5µ Sn; horizontal position; zero airflow.

Not subject to production test; specified by design.

2.3.2 78 K/W 300 mm2 PCB heatsink area1)

2.3.3 55 K/W 600 mm2 PCB heatsink area1)

2.3.4 Junction – Case PG-TO252-5-11 Rth,j-c 1.8 K/W

Package P-TO263-5:

2.3.1 Junction – Ambient

PG-TO263-5-1

Rth,j-a 79 K/W Footprint only1)

2.3.2 53 K/W 300 mm2 PCB heatsink area1)

2.3.3 39 K/W 600 mm2 PCB heatsink area1)

2.3.4 Junction – Case PG-TO263-5-1 Rth,j-c 1.3 K/W

TLE 4275 V33

Block Description and Electrical Characteristics

Datasheet 5 Rev. 1.0, 2006-09-22

3 Block Description and Electrical Characteristics

3.1 Voltage Regulator

The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass

transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip

temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output

capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Operating Range”

have to be maintained. For details see also the typical performance graph “Output Capacitor Series Resistor

ESRCQ vs. Output Current IQ”. Also, the output capacitor shall be sized to buffer load transients.

An input capacitor CI is strongly recommended to buffer line influences. Connect the capacitors close to the IC

terminals.

Protection circuitry prevent the IC as well as the application from destruction in case of catastrophic events. These

safeguards contain output current limitation, reverse polarity protection as well as thermal shutdown in case of

overtemperature.

In order to avoid excessive power dissipation that could never be handled by the pass element and the package,

the maximum output current is decreased at input voltages above VI=22V.

The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output

continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator

restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction

temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC lifetime.

The TLE 4275 V33 allows a negative supply voltage. However, several small currents are flowing into the IC

increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal

protection circuit is not operating during reverse polarity conditions For details see typical performance graphs.

Figure 3 Block Diagram Voltage Regulator Circuit

Bandgap

Reference

GND

BlockDiagram_VoltageRegulator.vsd

Saturation Control

Current Limitation

Tem peratur e

Shutdown

ESR

}

LOAD

Supply

Regulated Output Voltage

Datasheet 6 Rev. 1.0, 2006-09-22

TLE 4275 V33

Block Description and Electrical Characteristics

3.2 Current Consumption

Table 1 Electrical Characteristics Voltage Regulator

VI = 13.5 V; -40 °C ≤ Tj ≤ 150 °C (unless otherwise specified)

Pos. Parameter Symbol Limit Values Unit Remark / Test Condition

Min. Typ. Max.

3.1.1 Output Voltage VQ3.23 3.3 3.37 V 1 mA ≤ IQ ≤ 400 mA;

5 V ≤ VI ≤ 28 V

3.1.1 3.23 3.3 3.37 V 1 mA ≤ IQ ≤ 300 mA;

4.4 V ≤ VI ≤ 28 V

3.1.2 3.23 3.3 3.37 V 1 mA ≤ IQ ≤ 200 mA;

4.4 V ≤ VI ≤ 40 V

3.1.3 Load Regulation

steady-state

dVQ,load -30 -15 – mV IQ = 5 mA to 400 mA;

VI = 6 V

3.1.4 Line Regulation

steady-state

dVQ,line –5 15mVVI = 8 V to 32 V;

IQ = 5 mA

3.1.5 Power Supply Ripple

Rejection

PSRR –60– dBfripple = 100 Hz;

Vripple = 0.5 Vpp 1)

1) Parameter not subject to production test; specified by design.

3.1.6 Output Current Limitation IQ,max 401 – 1000 mA VQ = 3.0 V

3.1.7 Overtemperature Shutdown

Threshold

Tj,sd 151 – 200 °C Tj increasing 1)

3.1.8 Overtemperature Shutdown

Threshold Hysteresis

Tj,hy –25– K

Table 2 Electrical Characteristics Current Consumption

VI = 13.5 V; -40 °C ≤ Tj ≤ 150 °C (unless otherwise specified)

Pos. Parameter Symbol Limit Values Unit Conditions

Min. Typ. Max.

3.2.1 Current Consumption

Iq = IQ - II

Iq– 180 220 µA IQ = 1 mA;

Tj = 25 °C

3.2.2 – 180 240 µA IQ = 1 mA;

Tj ≤ 85 °C

3.2.3 – 8 12 mA IQ = 250 mA

3.2.4 – 20 30 mA IQ = 400 mA

TLE 4275 V33

Block Description and Electrical Characteristics

Datasheet 7 Rev. 1.0, 2006-09-22

3.3 Reset Function

The reset function contains serveal features:

Output Undervoltage Reset:

An output undervoltage condition is indicated setting the Reset Output “RO” to low. This signal might be used to

reset a microcontroller during low supply voltage.

In case the battery voltage is already lower than the buffered output voltage VQ of the voltage regulator, the reset

circuit is supplied from the output “Q”, ensuring a defined reset switching threshold also at VI = 0 V. The Reset

Output “RO” is held “low” down to an output voltage of VQ = 1 V, even if the input voltage VI is 0 V.

Power-On Reset Delay Time:

The power-on reset delay time td,PWR-ON allows a microcontoller and oscillator to start up. This delay time is the

time period from exceeding the reset switching threshold VRT until the reset is released by switching the reset

output “RO” from “low” to “high”. The power-on reset delay time td,PWR-ON is defined by an external delay

capacitor CD connected to pin “D” which is charged up by the delay capacitor charge current ID,ch starting from

VD= 0 V.

For easy calculating the power-on reset delay time, a multiplier factor Fd,PWR-ON =td,PWR-ON /CD is specified.

Hence, td,PWR-ON becomes:

td,PWR-ON = Fd,PWR-ON / CD . (1)

For a precise calculation consider also the delay capacitor’s tolerance.

Undervoltage Reset Delay Time:

Unlike the power-on reset delay time, the undervoltage reset delay td time considers a short output undervoltage

event where the delay capacitor CD is assumed to be discharged to VD=VDST,lo only before the charging sequence

restarts. Therefore, the undervoltage reset delay time td is defined by the delay capacitor charge current ID,ch

starting from VD=VDST,lo and the external delay capacitor CD.

For easy calculating the undervoltage reset delay time, a multiplier factor Fd=td/CD is specified. Hence, td

becomes:

td = Fd / CD . (2)

For a precise calculation consider also the delay capacitor’s tolerance.

Reset Reaction Time:

The total reset reaction rime trr,total considers the internal reaction time trr,int and the discharge time trr,d defined by

the external delay capacitor CD (see typical performance graph for details). Hence, the total reset reaction rime

becomes:

trr,total = trr,int + trr,d . (3)

Reset Output “RO” Low for VQ

≥

1V:

In case of an undervoltage reset condition reset output “RO” is held “low” for VQ≥1 V, even if the input voltage VI

is 0 V. This is achieved by supplying the reset circuit from the output capacitor.

Datasheet 8 Rev. 1.0, 2006-09-22

TLE 4275 V33

Block Description and Electrical Characteristics

Reset Output “RO”:

The Reset Output “RO” is an open collector output requiring an external pull-up resistor to a voltage rail VIO. As

the maximum Reset Output Sink Current IRO,max is limited, the minimum external pull-up resistor calculates:

RRO,external,min = VIO / IRO,max.(4)

Figure 4 Block Diagram Reset Circuit

Figure 5 Timing Diagram Reset

GND

BlockDiagram_ResetStandard_RO nopullup.vs d

Supply

DST

Int.

Supply

D,ch

DR,dsch

Control

Reset

VDD

Micro-

Controller

GND

e.g. +5 V

AED03010

Thermal

Power-on-Reset Voltage Dip Secondary Overload

at OutputSpike

D,c

Q, rt

at Input Undervoltage

Shutdown

DRL

TLE 4275 V33

Block Description and Electrical Characteristics

Datasheet 9 Rev. 1.0, 2006-09-22

Table 3 Electrical Characteristics Reset Function

VI = 13.5 V; -40 °C ≤ Tj ≤ 150 °C (unless otherwise specified)

Pos. Parameter Symbol Limit Values Unit Conditions

Min. Typ. Max.

Pos. Parameter Symbol Limit Values Unit Conditions / Remarks

Min. Typ. Max.

Output Undervoltage Reset Comperator:

3.3.1 Output Undervoltage Reset

Switching Threshold

VRT1 3.06 3.13 3.2 V VI ≥ 4.4 V

VQ decreasing

3.3.2 VRT2 2.5 2.9 VRT1 VVI = 0 V

VQ decreasing

3.3.3 Output Undervoltage Reset

Headroom

VRH 100 130 – mV Calculated Value: VQ,nom - VRT .

VI ≥ 4.4 V

Reset Output RO:

3.3.4 Reset Output Low Voltage VRO,low – 0.2 0.4 V 1 V ≤ VQ ≤ VRT ;

IRO = 0.3 mA

3.3.5 Reset Output

Sink Current Limitation

IRO,max 0.3 – – mA 1 V ≤ VQ < VRT ;

VRO = 3.3V

3.3.6 Reset Output External

Pull-up Resistor to VQ

RRO 3.3 – – kΩVRO ≤ 0.4 V at reset condition

3.3.7 Reset Output

Leakage Current

IRO,leak –02µAVRO = 5 V

Reset Delay Timing:

3.3.8 Upper Delay

Switching Threshold

VDST,hi –1.8–V–

3.3.9 Lower Delay

Switching Threshold

VDST,lo –0.6–V–

3.3.10 Delay Capacitor

Charge Current

ID,ch –6–µAVD = 1 V

3.3.11 Delay Capacitor

Reset Discharge Current

IDR,dsch – 70 – mA VD = 1 V

3.3.12 Undervoltage Reset Delay

Time Factor

Fd = td / CD

Fd 0.13 0.20 0.27 ms /

Calculated Value:

Fd = (VDST,hi - VDST,lo) / ID,ch

CD ≥ 10 nF 1)

1) For lower values of CD, the accuracy given is not guaranteed; see typ. performance graph for details.

3.3.13 Power-on Reset Delay

Time Factor

Fd,PWR-ON = td,PWR-ON / CD

Fd,PWR-ON 0.21 0.30 0.39 ms /

Calculated Value:

Fd = CD * VDST,hi / ID,ch

CD ≥ 10 nF 1)

3.3.14 Delay Capacitor

Discharge Time

trr,d –0.72µsCalculated Value:

trr,d = CD*(VDST,hi - VDST,lo)/ ID,dsch

CD = 47 nF

3.3.15 Internal Reset Reaction

Time

trr,int –26.5µsCD = 0 nF 2)

2) Parameter not subject to production test; specified by design.

Datasheet 10 Rev. 1.0, 2006-09-22

TLE 4275 V33

Package Outlines

4 Package Outlines

Figure 6 PG-TO252-5-11 Package Outline and Footprint

Figure 7 PG-TO263-5-1 Package Outline and Footprint

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with

government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-

free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Find more package information on the Infineon Internet Page: http://www.infineon.com/packages.

) Includes mold flashes on each side.

4.56 0.25 MA

6.5

5.7 MAX.

±0.1

per side

0.15 MAX.

-0.2

6.22

±0.5

9.98

(4.24) 1

1.14

5 x 0.6

±0.15

0.8

±0.1

+0.15

-0.05

0.1

-0.04

+0.08

0...0.15

0.51 MIN.

0.5

2.3

-0.10

0.5

+0.05

-0.04

+0.08

(5)

-0.01

0.9

+0.20

All metal surfaces tin plated, except area of cut.

5.36

5.8

10.6

6.4

0.34

0.8

2.2

Dimensions in mm

Footprint (Reflow Soldering)

BA0.25

±0.2

GPT0911

8.5

(15)

±0.2

9.25

±0.3

0...0.15

5 x 0.8

±0.1

1.27

4.4

0.5

±0.1

±0.3

2.7

4.7

±0.5

2.4

1.7

0...0.3 A

7.55

4 x

All metal surfaces tin plated, except area of cut.

Metal surface min. X = 7.25, Y = 6.9

Typical

0.1 B

0.1

0.05

8˚ MAX.

7.9

10.8

9.4

16.15

4.6

0.6

1.1

Dimensions in mm

Footprint (Reflow Soldering)

TLE 4275 V33

Revision History

Datasheet 11 Rev. 1.0, 2006-09-22

5 Revision History

TLE 4275 V33

Revision History: 2006-09-22 Rev. 1.0

Previous Version: n/a

Edition 2006-09-22

Published by Infineon Technologies AG,

81726 Munich, Germany

Attention please!

The information given in this data sheet shall in no event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values

stated herein and/or any information regarding the application of the device, Infineon Technologies hereby

disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-

infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.