oe oe GA National Semiconductor with TRI-STATE Outputs General Description The 'ACQ/"ACTQ821 is a 10-bit D flip-flop with non-invert- ing TRI-STATE outputs arranged in a broadside pinout. The "ACQ/ACTQ821 utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTOT output contro! and undershoot corrector in addition to a split ground bus for superior performance. The information for the ACQ821 is Advance information only. 54ACQ/74ACQ821 54ACTQ/74ACTQ821 Quiet Series 10-Bit D Flip-Flop November 1990 Features Guaranteed simultaneous switching noise level and dy- namic threshold performance @ Guaranteed pin-to-pin skew AC performance @ Non-inverting TRI-STATE outputs for bus interfacing @ 4 kV minimum ESD immunity @ Outputs source/sink 24 mA m@ Functionally identical to the AM29821 Logic Symbols Litti | | | Dy Dy Oz Dy Dy Ds Dg Oy Dy Dg OE cP Op 01 02 03 0 Os Og 07 0g Og Pr Tra bird TL/F/10686-1 IEEE/IEC OE EN cP Dy 9 Dy 0, Dp 04 Ds 05 D, Oo, Ds O5 Dg 0, by 0, Ds 8 Dy Q TL/F/10686-2 Pin Names Description Do-Dg Data Inputs O9-Og Data Outputs OE Output Enable Input CP Clock Input TRI-STATE is a registered trademark of National Semiconductor Corporation. FACT Quiet Series and GTO are trademarks of National Semiconductor Corporation. Connection Diagrams Pin Assignment for DIP, Flatpak and SOIC 7 oE41 241 Von Do-42 234-0, D.-43 22;0, D-44 21f-0, Dy-45 20;-0; Dy-46 19-0, Ds47 18|0. Dg48 17-0, D-49 16-0, De410 150g Dg 141-04 GND 412 13,;cP TL/F/10686-3 Pin Assignment for LCC Dy Dg Ds NC Dy Ds Dp fol (3) EE] Bae ss 1] 20 2 B24 23 24 Bs O7 Og Os NC Oy 03 05 TL/F/10686-4 1990 National Semiconductor Corporation TL/F/ 10686 | RRD-B20M110/Printed in U.S. A. L280 LOVPL/OLOVES LE8OOVPL/OOVPS $}NdjNO ALVLS-1HL UUM do]4-dil4 G Hg-OL Salas yeINDFunctional Description The 'ACQ/ACTQ821 consists of ten D-type edge-triggered flip-flops. The buffered Clock (CP) and buffered Output En- able (OE) are common to ali flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW the contents of the flip-flops are available at the outputs. When OE is HIGH the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The 'ACQ/ACTQ821 is functionally and pin compatible with the AM29821. Logic Diagram Function Table inputs Internal | Outputs Function OE | CP | D Q 0 H}| 7 IL L Zz High Z H ~~ |H H Z High Z L ~ L L L Load L ~~ H H H Load H = HIGH Voltage Level L = LOW Voltage Level 2 = HIGH Impedance _~ = LOW-to-HIGH Clock Transition eg! o-oo 8 Oo q E=1) ___| O oI | on*, Lh di | Oo aol J) -oOo oi a! Og TL/F/10686~5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.Absolute Maximum Rating (note 1) Recommended Operating If Military/Aerospace specified devices are required, Conditions please contact the National Semiconductor Sales S . . upply Voltage (Vcc) Office/Distributers for availability and specifications. "ACO 2.0V to 6.0V Supply Voltage (Vcc) 0.5V to +7.0V "ACTQ 4.5V to 5.5V md Input ive Current (Ix) 30 ma input Voltage (V)) OV to Voc p= 9%. - Vi = Voc + 0.5V +20 mA outing tee oe ty OV to Voc _ perating Temperature (Ta DC Input Voltage (Vi) 0.5V to Voc + 0.5V 74ACQ/ACTO ~A0C to +85C DC Output Diode Current (Ix) 54ACQ/ACTQ 55C to + 125C Vo = 0.5V 20mA e _ Minimum Input Edge Rate AV/At Vo = Vcc + 0.5V +20mA ACQ Devices DC Output Voltage (Vo) O0.5V to Voc + 0.5V Vin from 30% to 70% of Voc DC Output Source Voc @ 3.0V, 4.5V, 5.5V 125 mV/ns or Sink Current (Io) +50 mA Minimum Input Edge Rate AV/At DC Vcc or Ground Current "ACTQ Devices per Output Pin (cc or Ignp) +50 mA Vin from 0.8V to 2.0V Storage Temperature (Tstq) 65C to + 150C Voc @ 4.5V, 5.5V 125 mV/ns DC Latch-Up Source or Sink Current +300 mA Junction Temperature (Ty) CDIP 175C PDIP 140C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook spacifications should be mat, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recom- mend operation of FACTT circuits outside databook specifications. DC Electrical Characteristics for "ACQ Family Devices 74ACQ 54ACQ 74ACQ Symbol Parameter Vec | +, = +25C Ta = Ta = Units | Conditions () 55C to + 128C | 40C to + 85C Typ Guaranteed Limits Vin Minimum High Level | 3.0 1.5 2.1 2.1 2.1 Vout = 0.1V Input Voltage 45 2.25 3.15 3.15 3.15 Vv of Vcc 0.1V 5.5 2.75 3.85 3.85 3.85 VIL Maximum Low Level | 3.0 1.5 0.9 0.9 0.9 Vout = 0.1V Input Voltage 4.5 2.25 1.35 1.35 1.35 V or Voc 0.1V 5.5 2.75 1.65 1.65 1.65 Vou Minimum High Level | 3.0 2.99 2.9 2.9 2.9 louT = 50 pA Output Voltage 4.5 4.49 44 4.4 4.4 V 5.5 5.49 5.4 5.4 5.4 Vin = Vit or Vin 3.0 2.56 2.4 2.46 12mA 4.5 3.86 3.7 3.76 Vv lox 24mA 5.5 4.86 4.7 4.76 24mA VoL Maximum Low Level | 3.0 | 0.002 0.1 0.1 0.1 louT = 50 yA Output Voltage 4.5 | 0.001 0.1 0.1 0.1 V 5.6 | 0.001 0.1 0.1 0.1 "Vin = ViL or Vin 3.0 0.36 0.50 0.44 12mMA 4.5 0.36 0.50 0.44 Vv lov 24mA 5.5 0.36 0.50 0.44 24mA *All outputs loaded; thresholds on input associated with output under test.DC Electrical Characteristics for ACQ Family Devices (continued) 74ACQ 54ACQ 74ACQ Symbol Parameter Vec Ta = + 28C Ta = Ta = Units Conditions (V) 55C to + 125C | 40C to + 85C Typ Guaranteed Limits lin Maximum Input + + + Vi = Voc, GND Leakage Current 5 0.4 +10 1.0 pA (Note 4) loto TMinimum Dynamic 5.5 50 75 mA | Voip = 1.65V Max lonp | Output Current 5.5 50 ~75 mA | Voup = 3.85V Min loc Maximum Quiescent Vin = Veco . 8. 160. . Supply Current 5.5 60.0 80.0 HA | of GND (Note 1) loz Maximum TRI-STATE Vi, (OE) = Vit. Vin Leakage Current 5.5 +0.5 +10.0 +5.0 vA | Vi = Voc, GND Vo = Voc, GND VoLP Quist Output 5.0 11 15 Vv Figures 1, 2 Maximum Dynamic VoL (Notes 2, 3) VoLv Quiet Output Figures 1, 2 . 0. 1.2 Minimum Dynamic Vo, 5.0 0.6 1 V (Notes 2, 3) VIHD Minimum High Level 50 34 35 Vv (Notes 2, 4) Dynamic Input Voltage VILD Maximum Low Level 5.0 19 15 V (Notes 2, 4) Dynamic Input Voltage All outputs loaded; thresholds on input associated with output under test. tMaximum test duration 2.0 ms, one output loaded at a time. Note 1: Ii and ioc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Voc. log for S4ACQ @ 25C is identical ta 74ACQ @ 25C. Note 2: Worst case package. Note 3: Max number of outputs defined as (n). Data inputs are driven OV to 5V. One output @ GND. Note 4: Maximum number of data inputs (n) switching. (n 1) inputs switching OV to 5V (ACQ). Input-under-test switching: 5V to threshold (V\_p}, OV to threshold (Vinp). f = 1 MHz.DC Electrical Characteristics for 'ACTQ Family Devices 74ACTQ 54ACTQ 74ACTQ Symbol Parameter Voc Ta = +26C Ta = Ta = Units Conditions qv) | 4 ~ 55C to + 125C | 40C to + 85C Typ Guaranteed Limits VIH Minimum High Levet 4.5 1.5 2.0 2.0 2.0 Vv Vout = 0.1V Input Voltage 5.5 1.5 2.0 2.0 2.0 or Voc 0.1V VIL Maximum Low Level 45 1.5 0.8 0.8 0.8 V Vout = 0.1V Input Voltage 5.5 1.5 0.8 0.8 . 0.8 or Vcc 0.1V Vou Minimum High Level 45 | 449 | 4.4 4.4 4.4 y | four = 50zA Output Voltage 5.5 | 5.49 5.4 5.4 5.4 "Vin = Vit or Vin 45 3.85 3.70 3.76 Vv 24mA 5.5 4.86 4.70 4.76 OH 24mA VoL Maximum Low Level 4.5 | 0.001 0.1 0.1 0.1 Vv louT = 50 pA Output Voltage 5.5 | 0.001 0.1 0.1 0.1 "Vin = Vit or Vin 45 0.36 0.50 0.44 Vv | 24mA 5.5 0.36 0.50 0.44 ot 24mA hin Maximum Input 5.5 +04 +1.0 +1.0 pa | i= Voc, GND Leakage Current loz Maximum TRI-STATE Vi = Vin Vin + 10. +5. Leakage Current 8 40.5 +10.0 60 yA Vo = Vec, GND lect | Maximum 55 | 06 1.6 15 ma | i= Voc ~ 2.1V loc/Input foLp tMaximum Dynamic 5.5 50 75 mA | Voip = 1.65V Max lonp | Output Current 55 ~50 -75 mA | Voup = 3.85V Min loc Maximurn Quiescent Vin = Voc 5. . 160.0 - A Supply Current 6 8.0 60 80.0 pe or GND (Note 1) VoLp Maximum High Level Figures 1,2 . . . 1.5 Output Noise 8.0 1 V {Notes 2, 3) VoLv Maximum Low Level Figures 1,2 . -0.6 | -1. Vv Output Noise 8.0 0 V2 (Notes 2, 3) Vin Maximum High Level 5.0 19 22 Vv (Notes 2, 4) Dynamic Input Voltage VILD Maximum Low Level 5.0 42 0.8 y (Notes 2, 4) Dynamic Input Voltage All outputs loaded; thresholds on input associated with output under test. tMaximum test duration 2.0 ms, one output loaded at a time. Note 1: icc for 54ACTQ @ 25C is identical to 74ACTQ @ 25C. Note 2: Worst case package. Note 3: Max number of outputs defined as (n). Data inputs are driven OV to 3V. One output @ GND. Note 4: Maximum number of data inputs (n) switching. (n 1) inputs switching OV to 3V (ACTQ). Input-under-test switching: 3V to threshold (Vj_p), OV to threshold (inp), f = 1 MHz.AC Electrical Characteristics 74ACQ 54ACQ 74ACQ * _ Ta = 55C Ta = 40C Symbot Parameter ee % _ Soor to + 125C to +85C Units L P C, = 50 pF C. = 50 pF Min Typ Max Min Max Min Max fmax Maximum Clock 3.3 120 110 MHz Frequency 5.0 tPLH, Propagation Delay 3.3 teHL CP to O, 5.0 9. 105) ns tpZH, Output Enable Time 3.3 trol OE to 0, 50 11.0 12.0 ns tpHz, Output Disable Time 3.3 teLz DE toO, 50 12.9 13.0 ns tosLH, Output to Output Skew** 3.3 1.0 1.5 1.5 ns tosHL CP to Op, 5.0 0.5 1.0 1.0 *Voltage Range 3.3 is 3.3V +0.3V Voltage Range 5.0 is 5.0V +0.5V **Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (togH_) or LOW to HIGH (tog_y). Parameter guaranteed by design. Not tested. AC Operating Requirements 74ACQ 54ACQ 74ACQ . Lore Ta = 55C Ta = 40C Symbol Parameter ee a _ oor to + 125C to + 85C Units L P C. = 50 pF CL = 50 pF Typ Guaranteed Minimum ts Setup Time, HIGH or LOW 3.3 Dp to CP 5.0 3.0 3.0 ns th Hold Time, HIGH or LOW 3.3 D, to CP 50 1.5 1.5 ns tw CP Pulse Width 3.3 HIGH or LOW 5.0 5.0 5.0 ns *Voltage Range 3.3 is 3.3V +0.3V Voltage Range 5.0 is 5.0V +0.5VAC Electrical Characteristics 74ACTQ 54ACTQ 74ACTQ : _ Ta = 55C Ta = 40C Symbol Parameter Vec Ta + 25C to + 125C to + 85C Units (V) CL = 50 pF C,_ = 50 pF C_ = 50 pF Min Typ Max Min Max Min Max imax Frequency 5.0 120 110 | MHz ct po peation Delay 5.0 3.0 6.5 95 25 10.5 ns nf ea ae but Enable Time 5.0 3.0 75 10.5 25 11.5 ns n nee oe sable Time 5.0 1.0 6.5 85 1.0 9.0 ns n tos_y, Output to Output Skew** town | GPt00, 5.0 0.5 1.0 1.0 ns *Voltage Range 5.0 is 5.0V +0.5V **Skew is defined as the absolute value of the differance between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tagy,) or LOW to HIGH (tosin). Parameter guaranteed by design. Not tested. AC Operating Requirements 74ACTQ 54ACTQ 74ACTQ . _ Ta = 55C Ta = 40C Symbol Parameter ec vA _ to or to + 125C to + 385C Units L P C. 50 pF C. = 50 pF Typ Guaranteed Minimum ts Setup Time, HIGH or LOW Dp to CP 5.0 3.0 3.0 ns th Hold Time, HIGH or LOW D, to CP 5.0 1.5 1.5 ns tw CP Pulse Width HIGH or LOW 9.0 48 5.6 ns Voltage Range 5.0 is 5.0V +0.5V Capacitance Symbol Parameter Typ Units Conditions Cin Input Capacitance 4.5 pF Voc = 5.0V Cpp Power Dissipation _ Capacitance 55.0 pF Voc = 5.0VFACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500. 2. Deskew the word generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. Swap out the channels that have more than 150 ps of skew until all channels being used are within 150 ps. It is important to deskew the word generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate ail inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4, Set Vcc to 5.0V. 5. Set the word generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and affect the results of the measurement. ACTIVE OUTPUTS QUIET OUTPUT UNDER TEST TL/F/10686-6 FIGURE 8. Quiet Output Noise Voltage Waveforms Note A: Vony and Vo.p are measured with respect to ground reference. Note B: Input pulses have the following characteristics: f = 1 MHz, t = 3ns, ty = 3.ns, skew < 150 ps. 6. Set the word generator input levels at OV LOW and 3V HIGH for ACT devices and OV LOW and 5V HIGH for AC devices. Verify levels with a digital volt meter. VotpP/Vorv and Voup/Vonv: Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output volt- ages using a 502 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Measure Vo_p and Vo.y on the quiet output during the HL transition. Measure Voup and Voyy on the quiet out- put during the LH transition. * Verify that the GND reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. Vito and Vinp: * Monitor one of the switching outputs using a 502M coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. First increase the input LOW voltage level, Vj, until the output begins to oscillate. Oscillation is defined as noise on the output LOW level that exceeds Vj, limits, or on output HIGH tevels that exceed Vi limits. The input LOW voltage level at which oscillation occurs is defined as Vitp- Next increase the input HIGH voltage level on the word generator, Vj} until the output begins to oscillate. Oscilla- tion is defined as noise on the output LOW level that exceeds Vj, limits, or on output HIGH levels that exceed Vin limits. The input HIGH voltage level at which oscilla- tion occurs is defined as Vipp. * Verify that the GND reference recorded on the ascillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. close to DUT pins as possible. Vec ! DUT @) 7oinputs 4500 ) HP &t80A > TEK 7854 WORD 50 pF Oscilloscope GENERATOR t 500 Inputs Yee 4500 hah i SP GND t 50 pF Probes are grounded as GND is supplied vie U a copper plane Load capacitors are placed as close to OUT as possible. TL/F/10686-7 FIGURE 9. Simuitaneous Switching Test CircuitOrdering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74ACTQ: 821 P C QR Temperature Range Family cL Special Variations 74ACQ = Commercial X = Device shipped in 13 reels 54ACQ = Military QR = Commercial grade device with burn- 74ACTQ = Commercial TTL-Compatible in 54ACTQ = Military TTL-Compatible QB = Military grade device with ; environmental and burn-in Device Type processing shipped in tubes Package Code Temperature Range SP = Slim Plastic DiP C = Commercial ( 40C to + 85C) SD =Slim Ceramic DIP M = Military (- 55C to+ 125C) F =Flatpak L =Leadless Ceramic Chip Carrier (LCC) S = Small Outline (SOIC)Physical DimensiONs inches (millimeters) 0.404 {10.26} 0.065 0,076 sa . 7) [7 (1-651 1 930) 651 1.930) i + 16 oe parr 3-11 =| TOP BOTTOM SIDE VIEW view VIEW E2BA (REV C} 28 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 0.025 1.208 (ease) "A? isa. ** |_f2a] [23] fee) [2] fe] fos) fre) for) fre] Fis] Pal 3] fo O315 MAX (8.001) GLASS 0.030-0.055 (0.7621.397) RAD TYP GLASS 0.060 +0005 0.290-0.320 SEALANT 1.524 40.127) sazoere (7.366-8.128) (0508-1778) 0.180 { 0.226 (4.572) k (5.715) MAX | MAX FTE 0.008-0.012 95 25 <$<$<$<_< 16 | 4 (0.263-0.305) TYP pees MAX ewan | L 0.018 +0.003 meas | 0.125 LL 0310-0410 | 80TH 1 TE (2.413) ewns (2.54 saz (0.457 +0.078) wn) G78 (7.874-10.41) J24F(REV G} 24 Lead Slim (0.300 Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 10