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Copyright © 2012 Active-Semi, Inc.
High Performance ActivePSRTM Primary Switching Regulator
FEATURES
Ultra Low Standby Power < 30mW
Patented Primary Side Regulation
Technology
Suitable Operation Frequency up to 85kHZ
Proprietary Fast Startup Circuit
Integrated Line and Primary Inductance
Compensation
Integrated Programmable Output Cor d
Resistance Compensati on
Line Under-Voltage, Output Over-Voltage,
Output Short-Circuit and Over-Temperatur e
Protection
Complies with all Global Energy Efficiency
and CEC Average Efficiency Standards
Adjustable Po wer from 7W to 12W
Minimum External Components
SOP-8 Package
APPLICATIONS
RCC Adapter Replacements
Linear Adapter Replacements
Standby and Auxiliary Supplies
GENERAL DESCRIPTION
The ACT337 belongs to the high performance
patented ActivePSRTM Family of Universal-input
AC/DC off-line controllers for battery charger and
adapter applications. It is designed for flyback
topology working in discontinuous conduction mode
(DCM). The ACT337 meets all of the global energy
efficiency regulations (CEC, European Blue Angel,
and US Energy Star standards) while using very
few external components.
The ACT337 ensures safe operation with complete
protection against all fault conditions. Built-in
protection circuitry is provided for output short-
circuit, output over-voltage, line under-voltage, and
over temperature conditions.
The ACT337 ActivePSRTM is optimized for high
performance, cost-sensitive applications, and
utilizes Active-Semi’s proprietary primary-side
feedback architecture to provide accurate constant
voltage, constant current (CV/CC) regulation
without the need of an opto-coupler or reference
device. Integrated line and primary inductance
compensation circuitry provides accurate constant
current operation despite wide variations in line
voltage and primary inductance. Integrated output
cord resistance compensation further enhances
output accuracy. The ACT337 achieves excellent
regulation and transient response, yet requires less
than 30mW of standby power.
The ACT337 is optimized for compact size 7W to
12W charger applications. It is available in space-
saving 8 pin SOP-8 package.
Figure 1:
Simplified Application Circuit
ACT337
Rev 2, 14-Nov-12
ACT337
Rev 2, 14-Nov-12
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Copyright © 2012 Active-Semi, Inc.
PIN CONFIGURATION
PIN DESCRIPTIONS
PART NUMBER TEMPERATURE RANGE PACKAGE PINS PACKING
METHOD TOP MARK
ACT337SH-T -40°C to 85°C SOP-8 8 TAPE & REEL ACT337SH
PIN NAME DESCRIPTION
SOP-8
1 SW
Switch Drive. Switch node for the external NPN transistor. Connect this pin to the external
power NPN’s emitter. This pin also supplies current to VDD during startup.
2,4,7 GND Ground(2,4 and 7 pin must be connected together).
8 BD Base Drive. Base driver for the external NPN transistor.
6 VDD
Power Supply. This pin provides bias power for the IC during startup and steady state
operation.
5 FB Feedback Pin. Connect this pin to a resistor divider network from the auxiliary winding.
3 CS
Current Sense Pin. Connect an external resistor (RCS) between this pin and ground to set
peak current limit for the primary switch. The peak current limit is set by (0.396V × 0.9) /
RCS. For more detailed information, see Application Information.
ORDERING INFORMATION
SOP-8
ACT337SH
ACT337SH
Rev 2, 14-Nov-12
ACT337
Rev 2, 14-Nov-12
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Copyright © 2012 Active-Semi, Inc.
ABSOLUTE MAXIMUM RATINGSc
ELECTRICAL CHARACTERISTICS
(VDD = 12V, VOUT = 5V, LP = 1.25mH, NP = 110, NS = 8, NA = 18, TA = 25°C, unless otherwise specified.)
c: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Supply
VDD Turn-On Voltage VDDON V
DD Rising from 0V 17.6 18.6 19.6 V
VDD Turn-Off Voltage VDDOFF V
DD Falling after Turn-on 5.25 5.5 5.75 V
Supply Current IDD V
DD = 12V, after Turn-on 240 340 440 uA
Start Up Supply Current IDDST V
DD = 12V, before Turn-on 23 45 µA
BD Current during Startup IBDST 1 µA
Internal Soft Startup Time 10 ms
Oscillator
Switching Frequency fSW
100% VOUTCV @ full load 80
kHz
25% VOUTCV @ full load 40
Maximum Switching Frequency FCLAMP 89 98 107 kHz
Maximum Duty Cycle DMAX 65 75 85 %
Feedback
Effective FB Voltage VFB 2.17 2.19 2.22 V
FB Leakage Current IFBLK 1 µA
Output Cable Resistance
Compensation DVCOMP
No RCORD between VDD and SW 0
%
RCORD = 300k 3
RCORD = 150k 6
RCORD = 75k 9
RCORD = 33k 12
PARAMETER VALUE UNIT
VDD, BD, SW to GND -0.3 to + 28 V
Maximum Continuous VDD Current 100 mA
FB, CS to GND -0.3 to + 6 V
Continuous SW Current Internally limited A
Maximum Power Dissipation (derate 6.7mW/˚C above TA = 50˚C)(SOP-8) 0.67 W
Junction to Ambient Thermal Resistance (θJA)(SOP-8) 150 ˚C/W
Operating Junction Temperature -40 to 150 ˚C
Storage Junction -55 to 150 ˚C
Lead Temperature (Soldering, 10 sec) 300 ˚C
ACT337
Rev 2, 14-Nov-12
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Copyright © 2012 Active-Semi, Inc.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Current Limit
SW Current Limit Range ILIM 100 600 mA
CS Current Limit Threshold VCSLIM t
OFF_DELAY = 0 380 396 412 mV
Leading Edge Blanking Time 200 300 ns
Driver Outputs
Switch ON-Resistance RON I
SW = 50mA 1.6 3
SW Off Leakage Current VSW = VDD = 22V 1 µA
Protection
VDD Latch-Off Voltage VDDOVP VDDON
+2
VDDON
+3
VDDON
+4 V
Thermal Shutdown Temperature 135 ˚C
Thermal Hysteresis 20 ˚C
Line UVLO IFBUVLO 134 µA
ELECTRICAL CHARACTERISTICS CONT’D
(VDD = 12V, VOUT = 5V, LP = 1.25mH, NP = 110, NS = 8, NA = 18, TA = 25°C, unless otherwise specified.)
FUNCTIONAL BLOCK DIAGRAM
CS
BASE
DRIVER
+
-
SIGNAL
FILTER
2.20V
CURRENT
SHAPING
CABLE
COMPENSATION
LOGIC
OSCILLATOR
ON
0.4V
+
G
FB
VDD BD SW
REFERENCE
REGULATOR
&
UVLO
OTP
OVP
-
+
+
-
+
-
ACT337
Rev 2, 14-Nov-12
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Copyright © 2012 Active-Semi, Inc.
As shown in the Functional Block Diagram, to
regulate the output voltage in CV (constant voltage)
mode, the ACT337 compares the feedback voltage
at FB pin to the internal reference and generates an
error signal to the pre-amplifier. The error signal,
after filtering out the switching transients and
compensated with the internal compensation
network, modulates the external NPN transistor
peak current at CS pin with current mode PFWM
(Pulse Frequency and Width Modulation) control.
To regulate the output current in CC (constant
current) mode, the oscillator frequency is modulated
by the output voltage.
SW is a driver output that drives the emitter of an
external high voltage NPN transistor. This base-
emitter-drive method makes the drive circuit the
most efficient.
Fast Startup
VDD is the power supply terminal for the ACT337.
During startup, the ACT337 typically draws only
25μA supply current. The startup resistor from the
rectified high voltage DC rail supplies current to the
base of the NPN transistor. This results in an
amplified emitter current to VDD through the SW
pin via Active-Semi's proprietary fast-startup
circuitry until it exceeds the VDDON threshold 19V. At
this point, the ACT337 enters internal startup mode
with the peak current limit ramping up in 10ms.
After switching starts, the output voltage begins to
rise. The VDD bypass capacitor must supply the
ACT337 internal circuitry and the NPN base drive
until the output voltage is high enough to sustain
VDD through the auxiliary winding. The VDDOFF
threshold is 5.5V; therefore, the voltage on the VDD
capacitor must remain above 5.5V while the output
is charging up.
Constant Voltage (CV) Mode Operation
In constant voltage operation, the ACT337 captures
the auxiliary flyback signal at FB pin through a
resistor divider network R5 and R6 in Figure 6. The
signal at FB pin is pre-amplified against the internal
reference voltage, and the secondary side output
voltage is extracted based on Active-Semi's
proprietary filter architecture.
This error signal is then amplified by the internal
error amplifier. When the secondary output voltage
is above regulation, the error amplifier output
voltage decreases to reduce the switch current.
When the secondary output voltage is below
regulation, the error amplifier output voltage
increases to ramp up the switch current to bring the
secondary output back to regulation. The output
regulation voltage is determined by the following
relationship:
where RFB1 (R5) and RFB2 (R6) are top and bottom
feedback resistor, NS and NA are numbers of
transformer secondary and auxiliary turns, and VD
is the rectifier diode forward drop voltage at
approximately 0.1A bias.
Standby (No Load) Mode
In no load standby mode, the ACT337 oscillator
frequency is further reduced to a minimum
frequency while the current pulse is reduced to a
minimum level to minimize standby power. The
actual minimum switching frequency is
programmable with an output preload resistor.
Loop Compensation
The ACT337 integrates loop compensation circuitry
for simplified application design, optimized transient
response, and minimal external components.
Output Cable Resistance Compensation
The ACT337 provides programmable output cable
resistance compensation during constant voltage
regulation, monotonically adding an output voltage
correction up to predetermined percentage at full
power. There are four levels to program the output
cable compensation by connecting a resistor (R10
in Figure 6) from the SW pin to VDD pin. The
percentage at full power is programmable to be 3%,
6%, 9% or 12%, and by using a resistor value of
300k, 150k, 75k or 33k respectively. If there is no
resistor connection, there is no cord compensation.
This feature allows for better output voltage
accuracy by compensating for the output voltage
droop due to the output cable resistance.
Constant Current (CC) Mode Operation
When the secondary output current reaches a level
set by the internal current limiting circuit, the
ACT337 enters current limit condition and causes
the secondary output voltage to drop. As the output
voltage decreases, so does the flyback voltage in a
proportional manner. An internal current shaping
circuitry adjusts the switching frequency based on
the flyback voltage so that the transferred power
remains proportional to the output voltage, resulting
FUNCTIONAL DESCRIPTION
(1)
D
A
S
2FB
1FB
OUTCV V
N
N
R
R
1V20.2V ×
+×=
ACT337
Rev 2, 14-Nov-12
Innovative PowerTM - 6 - www.active-semi.com
Copyright © 2012 Active-Semi, Inc.
in a constant secondary side output current profile.
The energy transferred to the output during each
switching cycle is ½(LP × ILIM
2) × η, where LP is the
transformer primary inductance, ILIM is the primary
peak current, and η is the conversion efficiency.
From this formula, the constant output current can
be derived:
where fSW is the switching frequency and VOUTCV is
the nominal secondary output voltage.
The constant current operation typically extends
down to lower than 40% of nominal output voltage
regulation.
Primary Inductance Compensation
The ACT337 integrates a built-in proprietary
(patent-pending) primary inductance compensation
circuit to maintain constant current regulation
despite variations in transformer manufacturing.
The compensated range is ±7%.
Primary Inductor Current Limit Compensation
The ACT337 integrates a primary inductor peak
current limit compensation circuit to achieve
constant input power over line and load ranges.
Protection
The ACT337 incorporates multiple protection
functions including over-voltage, over-current and
over-temperature.
Output Short Circuit Protection
When the secondary side output is short circuited,
the ACT337 enters hiccup mode operation. In this
condition, the VDD voltage drops below the VDDOFF
threshold and the auxiliary supply voltage
collapses. This turns off the ACT337 and causes it
to restart. This hiccup behavior continues until the
short circuit is removed.
Output Over Voltage Protection
The ACT337 includes output over-voltage
protection circuitry, which shuts down the IC when
the output voltage is 40% above the normal
regulation voltage for 4 consecutive switching
cycles. The ACT337 enters hiccup mode when an
output over voltage fault is detected.
Over Temperature Shutdown
The thermal shutdown circuitry detects the ACT337
die temperature. The typical over temperature
threshold is 135°C with 20°C hysteresis. When the
die temperature rises above this threshold the
ACT337 is disabled until the die temperature falls
by 20°C, at which point the ACT337 is re-enabled.
TYPICAL APPLICATION
Design Example
The design example below gives the procedure for
a DCM flyback converter using the ACT337. Refer
to Application Circuit in Figure 6, the design for a
charger application starts with the following
specification:
The operation for the circuit shown in Figure 6 is as
follows: the rectifier bridge D1D4 and the capacitor
C1/C2 convert the AC line voltage to DC. This
voltage supplies the primary winding of the
transformer T1 and the startup resistor R7/R8. The
primary power current path is formed by the
transformer’s primary winding, the NPN transistor,
the ACT337 internal MOSFET and the current
sense resistor R9. The network consisting of
capacitor C4 and diode D6 provides a VDD supply
voltage for ACT337 from the auxiliary winding of the
transformer. C4 is the decoupling capacitor of the
supply voltage and energy storage component for
startup. The diode D8 and the capacitor C5 rectifies
and filters the output voltage. The resistor divider
consisting of R5 and R6 programs the output
voltage.
The minimum and maximum DC input voltages can
be calculated:
FUNCTIONAL DESCRIPTION CONT’D
×
×
×
××=
OUTCV
SW
2
CS
POUTCC V
f
R
9.0V396.0
L
2
1
I
η
(2)
V90
Fμ102%77
)ms4
502
1
(52
902
C
)t
f2
1
(P2
V2V
2
IN
C
L
OUT
2
ACMININDCMIN
××
×
×
×=
×
=
η
(3)
V3752652V2V ACMAXINDCMAX =×=×= (4)
Input Voltage Range 90VAC - 265VAC, 50/60Hz
Output Power, PO 10.5W
Output Voltage, VOUTCV 5.0V
OCP Current, IOUTMAX 2.5A
Full Load Current, IOUTFL 2.1A
Transformer Efficiency, ηxfm 0.92
System Efficiency CC, ηsystem 0.76
System Efficiency CV, η 0.77
ACT337
Rev 2, 14-Nov-12
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Copyright © 2012 Active-Semi, Inc.
V7.573
58.040
3.05(375
VV
)VV(V
V
OUTCVDREV
DSOUTCVINDCMAX
RO =
×
+×
=
+×
=(5)
110
T/nH110
mH52.1
A
L
N2
LE
P==
25.2
385.030.05
5.025.012
VVV
VVV
N
N
CORDDSOUTCV
RDADD
S
A=
++
++
=
++
++
=
mH1
KHz72mA634
%4890
fI
DV
L
SWPK
INDCMIN
P
×
×
=
×
×
=
mA634
%48
.31522
D
I2
IIN
PK =
×
=
×
=
mA3.152
%7790
2.15
V
IV
I
INDCMIN
OUTPLOUTCV
IN =
×
×
=
×
×
=
η
(6)
(7)
(8)
(9)
k.2180.68
20.225.2)25.05(
20.2
R
V
N
N
)VV(
V
R1FB
FB
S
A
DSOUTCV
FB
2FB
×
×+
=
+
=
(16)
Fμ280
mV50kHz72
48.0.12
Vf
DI
C
RIPPLESW
OUTCC
OUT =
×
×
=
×
×
=(17)
(10)
8110
3.71
1
N
N
N
NP
P
S
S=×=×=
(11)
18825.2N
N
N
NS
S
A
A=×=×= (13)
k80.6242326
62.0
25.1
110
18
K
R
L
N
N
R
CS
P
P
A
1FB ××=××= (15)
()()
R64.0
92.0
77.0
7225.1
55.22.1
396.09.0
fL
VII
V9.0
R
xfm
system
SWP
OUTOUTMAXOUTFL
CSLIM
CS =
××
×+
×
=
××
×+
×
=
η
η
(14)
where η is the estimated circuit efficiency, fL is the
line frequency, tC is the estimated rectifier
conduction time, CIN is empirically selected to be
2×10µF electrolytic capacitors based on the
2.5~3µF/W rule of thumb.
When the transistor is turned off, the voltage on the
transistor’s collector consists of the input voltage
and the reflected voltage from the transformer’s
secondary winding. There is a ringing on the rising
top edge of the flyback voltage due to the leakage
inductance of the transformer. This ringing is
clamped by a RCD network if it is used. Design this
clamped voltage as 50V below the breakdown of
the NPN transistor. The flyback voltage has to be
considered with selection of the maximum reverse
voltage rating of secondary rectifier diode. If a 40V
Schottky diode is used, then the flyback voltage can
be calculated:
where VDS is the Schottky diode forward voltage,
VDREV is the maximum reverse voltage rating of the
diode and VOUTCV is the output voltage.
The maximum duty cycle is set to be 48% at low
line voltage 90VAC and the circuit efficiency is
estimated to be 77%. Then the full load input
current is:
The maximum input primary peak current at full
load base on duty of 48%:
The primary inductance of the transformer:
NP/NS can be calculated according to below
equation
The auxiliary to secondary turns ratio NA/NS:
Where VDA is diode forward voltage of the auxiliary
side and VR is the resister voltage.
An EPC17 transformer gapped core with an
effective inductance ALE of 110nH/T2 is selected.
The number of turns of the primary winding is:
The number of turns of secondary and auxiliary
windings can be derived when Np/Ns=13.7:
The current sense resistance (RCS) determines the
current limit value based on the following equation:
The voltage feedback resistors are selected
according to below equation:
Where K is IC constant and K = 242326.
When selecting the output capacitor, a low ESR
electrolytic capacitor is recommended to minimize
ripple from the current ripple. The approximate
equation for the output capacitance value is given by:
A 470µF electrolytic capacitor is used to keep the
ripple small.
PCB Layout Guideline
Good PCB layout is critical to have optimal
performance. Decoupling capacitor (C4), current
sense resistor (R9) and feedback resistor (R5/R6)
should be placed close to VDD, CS and FB pins
respectively. There are two main power path loops.
One is formed by C1/C2, primary winding, NPN
transistor and the ACT337. The other is the
secondary winding, rectifier D8 and output
capacitors (C5). Keep these loop areas as small as
possible. Connect high current ground returns, the
input capacitor ground lead, and the ACT337 G pin
TYPICAL APPLICATION CONT’D
(12)
92
000023.03000
634.0001.0
AB
IL
N
Emax
peakP
MIN
×
×
=
×
×
=
ACT337
Rev 2, 14-Nov-12
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Copyright © 2012 Active-Semi, Inc.
TYPICAL APPLICATION CONT’D
to a single point (star ground configuration).
NPN Selection Guideline
NPN transistors with HFE of 20 to 25 are highly
recommended in the design due to the start up
time. If the HFE is too low the start up time
becomes longer because of 30M start up resister.
VFB Sampling Waveforms
ACT337 senses the output voltage information
through the VFB waveforms. Proper VFB waveforms
are required for IC to operate in a stable status. To
avoid mis-sampling, 1.38µs blanking time is added
to blank the ringing period due to the leakage
inductance and the circuit parasitic capacitance.
Figure 2 is the recommended VFB waveform to
guarantee the correct sampling point so that the
output information can be sent back into the IC to
do the appropriate control.
VFB waveforms of Figure 3, Figure 4, and Figure 5
violate the sampling design margin and are not
recommended. Figure 3 has very long overshoot
period. Figure 4, and Figure 5 have very long
ringing period. The undesired waveforms cause the
IC to operate in an unstable mode easily due to
wrong feedback information.
Figure 2 Figure 3
Figure 4 Figure 5
1.8µs
1.8µs 1.8µs
1.8µs
ACT337
Rev 2, 14-Nov-12
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Copyright © 2012 Active-Semi, Inc.
Figure 6:
Universal VAC Input, 5V/2.1A Output Charger
Item Reference Description QTY
1 C1, C2 Capacitor, Electrolytic, 10µF/400V, 10×16mm (Low leakage current) 2
2 C3 Capacitor, Ceramic,220pF/500V,1206,SMD 1
3 C4 Capacitor, Ceramic, 10µF/35V,1206,SMD 1
4 C5 Capacitor, Electrolytic, 1000µF/6.3V, 8 ×16mm 1
5 C6 Capacitor, Electrolytic, 820µF/6.3V, 6.3 × 16mm 1
6 C9 Capacitor, Ceramic,1000pF/50V,0805,SMD 1
7 CY1 Safety Y1,Capacitor,1000pF/400V,Dip 1
8 BD1 Bridge Rectifier,D1010S,1000V/1.0A,SDIP 1
9 D5 Fast Recovery Rectifier, RS1M,1000V/1.0A, RMA 1
10 D6 Fast Recovery Rectifier,RS1D,200V/1.0A,SMA 1
11 D8 Diode, Schottky, 45V/10A, S10U45S, SMD 1
12 L1 Choke Coil, 1.5mH, ¢6x8mm, DIP 1
13 Q1 Transistor, NPN, 700V,D13005,TO-126 1
14 F1 Fuse:1A 250V 3.6*10mm With Pigtail, ceramic tube 1
15 R1 Chip Resistor, 22, 0805, 5% 1
16 R2 Chip Resistor, 1M,1206, 5% 1
17 R3 Chip Resistor, 390,1206, 5% 1
18 R4 Chip Resistor, 15, 0805, 5% 1
19 R5 Chip Resistor, 80.6k,0805, 1% 1
20 R6 Chip Resistor,18.2k,0805, 1% 1
21 R7 Chip Resistor, 30M, 1206, 5% 1
22 R9 Chip Resistor, 0.62,1206, 1% 1
23 R10 Chip Resistor, 162k,0805, 5% 1
24 R11 Chip Resistor, 3k, 0805, 5% 1
25 R13 Chip Resistor, 10, 0805, 5% 1
26 T1 Transformer, LP = 1.25mH±7%, EPC17 1
27 U1 IC, ACT337SH-T,SOP-8 1
Table 1:ACT337 Bill of Materials
ACT337
Rev 2, 14-Nov-12
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Copyright © 2012 Active-Semi, Inc.
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(Circuit of Figure 6, unless otherwise specified.)
ACT337-012
Internal MOSFET RON vs. Temperature
RON ()
2.4
2.0
1.6
1.2
0.8
0.4
0.0
ACT337-007
ACT337-008
VDD ON/OFF Voltage vs. Temperature Start Up Supply Current vs. Temperature
20.5
16.5
14.5
12.5
10.5
8.5
6.5
4.5
18.5
VDDON and VDDOFF (V)
Temperature (°C)
0 25 50 75
ACT337-009
FB Voltage vs. Temperature
VFB (V)
2.25
2.20
2.15
2.10
2.05
2.00
VDDON
VDDOFF
Temperature (°C)
0 25 50 75
28
26
24
22
20
18
16
14
IDDST (µA)
Temperature (°C)
0 25 50 75
Temperature (°C)
0 25 50 75
ACT337-010
Normalized ILIM vs. Temperature
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
Normalized ILIM (mA)
Temperature (°C)
0 25 50 75
ACT337
Rev 2, 14-Nov-12
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Copyright © 2012 Active-Semi, Inc.
PACKAGE OUTLINE
SOP-8 PACKAGE OUTLINE AND DIMENSIONS
θ
CD
B
e
SYMBOL DIMENSION IN
MILLIMETERS DIMENSION IN
INCHES
MIN MAX MIN MAX
A 1.350 1.750 0.053 0.069
A1 0.100 0.250 0.004 0.010
A2 1.350 1.550 0.053 0.061
B 0.330 0.510 0.013 0.020
C 0.190 0.250 0.007 0.010
D 4.700 5.100 0.185 0.201
E 3.800 4.000 0.150 0.157
E1 5.800 6.300 0.228 0.248
e 1.270 TYP 0.050 TYP
L 0.400 1.270 0.016 0.050
θ
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
sales@active-semi.com or visit http://www.active-semi.com.
is a registered trademark of Active-Semi.
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