2010-2016 Microchip Technology Inc. DS20002230G-page 1
MCP2003/4/3A/4A
Features
• The MCP2003/2003A and MCP2004/2004A are
Compliant with Local Interconnect Network (LIN)
Bus Specifications 1.3, 2.0 and 2.1, and are
Compliant to SAE J2602
• Supports Baud Rates up to 20 Kbaudwith
LIN Bus Compatible Output Driver
• 43V Load Dump Protected
• Very Low/High Electromagnetic Immunity (EMI)
meets Stringent Original Equipment
Manufacturers (OEM) Requirements
• Very High Electrostatic Discharge (ESD)
Immunity:
->20kV on V
BB
(IEC 61000-4-2)
->14kV on L
BUS
(IEC 61000-4-2)
• Very High Immunity to RF Disturbances meets
Stringent OEM Requirements
• Wide Supply Voltage, 6.0V-27.0V Continuous
• Extended Temperature Range: -40°C to +125°C
• Interface to PIC
®
MCU EUSART and Standard
USARTs
• LIN Bus Pin:
- Internal pull-up resistor and diode
- Protected against battery shorts
- Protected against loss of ground
- High-current drive
• Automatic Thermal Shutdown
• Low-Power mode:
- Receiver monitoring bus and transmitter off
(
5µA)
Description
This device provides a bidirectional, half-duplex commu-
nication, physical interface to automotive and industrial
LIN systems to meet the LIN Bus Specification
Revision 2.1 and SAE J2602. The device is short-circuit
and overtemperature protected by internal circuitry. The
device has been specifically designed to operate in the
automotive operating environment and will survive all
specified transient conditions, while meeting all of the
stringent quiescent current requirements.
MCP200X family members:
• 8-pin PDIP, DFN and SOIC packages:
- MCP2003: LIN bus compatible driver with
WAKE pins, wake-up on falling edge of L
BUS
- MCP2003A: LIN bus compatible driver with
WAKE pins, wake-up on rising edge of L
BUS
- MCP2004: LIN bus compatible driver with
FAULT/T
XE
pins, wake-up on falling edge of
L
BUS
- MCP2004A: LIN bus compatible driver with
FAULT/T
XE
pins, wake-up on rising edge of
L
BUS
Package Types
MCP2004/2004A
PDIP, SOIC
FAULT/T
XE
CS/WAKE
TXD
VBB
LBUS
1
2
3
4
8
7
6
5
VSS
V
REN
RXD
MCP2003/2003A
PDIP, SOIC
WAKE
CS
TXD
VBB
LBUS
1
2
3
4
8
7
6
5
VSS
VREN
RXD
MCP2003/2003A
4x4 DFN*
WAKE
CS
TXD
VBB
LBUS
1
2
3
4
8
7
6
5VSS
VREN
RXD
EP
9
MCP2004/2004A
4x4 DFN*
FAULT/TXE
CS/WAKE
TXD
VBB
LBUS
1
2
3
4
8
7
6
5VSS
VREN
RXD
EP
9
* Includes Exposed Thermal Pad (EP); see Table 1-2.
LIN J2602 Transceiver
Not Recommended for New Designs
Please use ATA663211 or MCP2003B
MCP2003/4/3A/4A
DS20002230G-page 2 2010-2016 Microchip Technology Inc.
MCP2003/2003A Block Diagram
MCP2004/2004A Block Diagram
Thermal
Protection
V
REN
R
XD
T
XD
V
BB
L
BUS
V
SS
~30 k
CS
Wake-up
Logic and
Power Control
Short-Circuit
Protection
4.3V
WAKE
Ratiometric
Reference
–
+
OC
Thermal
Protection
V
REN
FAULT/T
XE
R
XD
T
XD
V
BB
L
BUS
V
SS
~30 k
CS/WAKE
Wake-up
Logic and
Power Control
Short-Circuit
Protection
4.3V 4.3V
–
+
Ratiometric
Reference
OC
2010-2016 Microchip Technology Inc. DS20002230G-page 3
MCP2003/4/3A/4A
1.0 DEVICE OVERVIEW
The MCP2003/4/3A/4A devices provide a physical
interface between a microcontroller and a LIN bus.
These devices will translate the CMOS/TTL logic levels
to the LIN logic level and vice versa. It is intended for
automotive and industrial applications with serial bus
speeds up to 20 Kbaud.
LIN Bus Specification Revision 2.1 requires that the
transceiver of all nodes in the system is connected via
the LIN pin, referenced to ground, and with a maximum
external termination resistance load of 510 from LIN
bus to battery supply. The 510 corresponds to
1 master and 15 slave nodes.
The V
REN
pin can be used to drive the logic input of an
external voltage regulator. This pin is high in all modes
except for Power-Down mode.
1.1 External Protection
1.1.1 REVERSE BATTERY PROTECTION
An external reverse battery blocking diode should be
used to provide polarity protection (see Example 1-1).
1.1.2 TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 43V Transient Suppressor (TVS) diode,
between V
BB
and ground with a 50 Transient
Protection Resistor (R
TP
) in series with the battery
supply and the V
BB
pin, serve to protect the device from
power transients (see Example 1-1) and ESD events.
While this protection is optional, it is considered good
engineering practice.
1.2 Internal Protection
1.2.1 ESD PROTECTION
For component-level ESD ratings, please refer to the
maximum operation specifications.
1.2.2 GROUND LOSS PROTECTION
The LIN Bus Specification states that the LIN pin must
transition to the Recessive state when the ground is
disconnected. Therefore, a loss of ground effectively
forces the LIN line to a high-impedance level.
1.2.3 THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter.
There are two causes for a thermal overload. A thermal
shutdown can be triggered by either, or both, of the
following thermal overload conditions:
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
Driving the T
XD
pin and checking the R
XD
pin makes it
possible to determine whether there is a bus contention
(R
XD
= low, T
XD
= high) or a thermal overload condition
(R
XD
= high, T
XD
= low). After a thermal overload event,
the device will automatically recover once the die
temperature has fallen below the recovery temperature
threshold (see Figure 1-1).
FIGURE 1-1: THERMAL SHUTDOWN
STATE DIAGRAM
Operation
Mode
Transmitter
Shutdown
Shorted LIN Bus
to VBB
Temp < Shutdown
TEMP
MCP2003/4/3A/4A
DS20002230G-page 4 2010-2016 Microchip Technology Inc.
1.3 Modes of Operation
For an overview of all operational modes, refer to
Table 1-1.
1.3.1 POWER-DOWN MODE
In Power-Down mode, everything is off except the
wake-up section. This is the lowest power mode. The
receiver is off, thus its output is open-drain.
On CS going to a high level or a falling edge on WAKE
(MCP2003/MCP2003A only), the device will enter
Ready mode as soon as the internal voltage stabilizes.
Refer to Section 2.4 “AC Specifications” for further
information. In addition, LIN bus activity will change the
device from Power-Down mode to Ready mode;
MCP2003/4 wakes up on a falling edge on L
BUS
,
followed by a low level lasting at least 20 µs.
MCP2003A/4A wakes up on a rising edge on L
BUS
,
followed by a high level lasting 70 µs, typically. See
Figures 1-2 to 1-5 about remote wake-up. If CS is held
high as the device transitions from Power-Down to
Ready mode, the device will transition to either Opera-
tion or Transmitter Off mode, depending on the T
XD
input, as soon as internal voltages stabilize.
1.3.2 READY MODE
Upon entering Ready mode, V
REN
is enabled and the
receiver detect circuit is powered up. The transmitter
remains disabled and the device is ready to receive
data but not to transmit.
Upon V
BB
supply pin power-on, the device will remain
in Ready mode as long as CS is low. When CS
transitions high, the device will either enter Operation
mode, if the T
XD
pin is held high, or the device will enter
Transmitter Off mode, if the T
XD
pin is held low.
1.3.3 OPERATION MODE
In this mode, all internal modules are operational.
The device will go into Power-Down mode on the falling
edge of CS. For the MCP2003/4 device, a specific
process should be followed to put all nodes into Power-
Down mode. Refer to Section 1.6 “MCP2003/4 and
MCP2003A/4A Difference Details” and Figure 1-6.
The device will enter Transmitter Off mode in the event
of a Fault condition, such as thermal overload, bus
contention and T
XD
timer expiration.
The MCP2004/2004A device can also enter Transmitter
Off mode if the FAULT/T
XE
pin is pulled low. The V
BB
to
L
BUS
pull-up resistor is connected only in Operation
mode.
1.3.4 TRANSMITTER OFF MODE
Transmitter Off mode is reached whenever the
transmitter is disabled, either due to a Fault condition or
pulling the FAULT/T
XE
pin low on the MCP2004/2004A.
The Fault conditions include: thermal overload, bus
contention, R
XD
monitoring or T
XD
timer expiration.
The device will go into Power-Down mode on the falling
edge of CS or return to Operation mode if all Faults are
resolved and the FAULT/T
XE
pin on the MCP2004/2004A
is high.
FIGURE 1-2: OPERATIONAL MODES STATE DIAGRAM – MCP2003
POR
VREN OFF
RX OFF
TX OFF
VBAT > 5.5V
Ready
VREN ON
RX ON
TX OFF
TOFF
Mode
VREN ON
RX ON
TX OFF
Operation
Mode
VREN ON
RX ON
TX ON
POWER-
DOWN
VREN OFF
RX OFF
TX OFF
CS = 1 and TXD = 0
CS = 1 and TXD = 1
CS = 1 and TXD = 1 and No Fault
Fault (thermal or timer)
CS = 0
Falling Edge on LIN
or CS = 1
or Falling Edge on WAKE Pin
CS = 0
2010-2016 Microchip Technology Inc. DS20002230G-page 5
MCP2003/4/3A/4A
FIGURE 1-3: OPERATIONAL MODES STATE DIAGRAM – MCP2003A
FIGURE 1-4: OPERATIONAL MODES STATE DIAGRAM – MCP2004
POR
VREN OFF
RX OFF
TX OFF
VBAT > 5.5V
Ready
VREN ON
RX OFF
TX OFF
TOFF
Mode
VREN ON
RX ON
TX OFF
Operation
Mode
VREN ON
RX ON
TX ON
POWER-
DOWN
VREN OFF
RX OFF
TX OFF
CS = 1 and TXD = 0
CS = 1 and TXD = 1
CS = 1 and TXD = 1 and No Fault
Fault (thermal or timer)
CS = 0
Rising Edge on LIN
or CS = 1
or Falling Edge on WAKE Pin
CS = 0
POR
VREN OFF
RX OFF
TX OFF
VBAT > 5.5V
Ready
VREN ON
RX ON
TX OFF
TOFF
Mode
VREN ON
RX ON
TX OFF
Operation
Mode
VREN ON
RX ON
TX ON
POWER-
DOWN
VREN OFF
RX OFF
TX OFF
CS = 1 and (TXE = 0 or TXD = 0)
CS = 1 and TXD = 1 and TXE = 1
CS = 1 and TXD = 1 and TXE = 1
and No Fault
CS = 0
Falling Edge on LIN or
CS = 1
CS = 0
Fault (thermal or time-out) or
FAULT/TXE = 0
MCP2003/4/3A/4A
DS20002230G-page 6 2010-2016 Microchip Technology Inc.
FIGURE 1-5: OPERATIONAL MODES STATE DIAGRAM – MCP2004A
TABLE 1-1: OVERVIEW OF OPERATIONAL MODES
State Transmitter Receiver V
REN
Operation Comments
POR OFF OFF OFF Check CS; if low, then proceed to Ready mode.
If high, transitions to either T
OFF
or Operation
mode, depending on T
XD
(MCP2003/A), or T
XD
and FAULT/T
XE
(MCP2004/A).
V
BB
> V
BB(MIN)
and
internal supply is
stable
Ready OFF ON ON If CS is a high level, then proceed to Operation
or T
OFF
mode.
Bus Off state
Operation ON ON ON If CS is a low level, then proceed to
Power-Down mode. If FAULT/T
XE
is a low level,
then proceed to Transmitter Off mode.
Normal Operation
mode
Power-Down OFF Activity
Detect
OFF On CS high level, proceed to Ready mode; then
proceed to either Operation mode or T
OFF
mode.
MCP2003/2003A: Falling edge on WAKE will
put the device into Ready mode.
MCP2003/MCP2004: Falling edge on LIN bus
will put the device into Ready mode.
MCP2003A/MCP2004A: Rising edge on
LIN bus will put the device into Ready mode.
Low-Power mode
Transmitter Off OFF ON ON If CS is a low level, then proceed to
Power-Down mode. If FAULT/T
XE
and T
XD
are
high, then proceed to Operation mode.
FAULT/T
XE
is only
available on
MCP2004/2004A
POR
VREN OFF
RX OFF
TX OFF
VBAT > 5.5V
Ready
VREN ON
RX ON
TX OFF
TOFF
Mode
VREN ON
RX ON
TX OFF
Operation
Mode
VREN ON
RX ON
TX ON
POWER-
DOWN
VREN OFF
RX OFF
TX OFF
CS = 1 and (TXE = 0 or TXD = 0)
CS = 1 and TXD = 1 and TXE = 1
CS = 1 and TXD = 1 and
TXE = 1 and No Fault
Fault (thermal or time-out) or
FAULT/TXE = 0
CS = 0
Rising Edge on LIN
or CS = 1
CS = 0
2010-2016 Microchip Technology Inc. DS20002230G-page 7
MCP2003/4/3A/4A
1.4 Typical Applications
EXAMPLE 1-1: TYPICAL MCP2003/2003A APPLICATION
EXAMPLE 1-2: TYPICAL MCP2004/2004A APPLICATION
LIN Bus
V
DD
T
XD
R
XD
+12
1.0 µF
I/O
50
43V
1k
+12
Master Node Only
+12
3.9 k
Wake-up
Voltage Reg
(Note 1)
Note 1: For applications with current requirements of less than 20 mA, the connection to +12V can be deleted and voltage
to the regulator can be supplied directly from the V
REN
pin.
2: ESD protection diode.
4.7 k
Optional Resistor and
33 k
MMBZ27V
(2)
220 pF
V
BB
L
BUS
V
REN
T
XD
R
XD
V
SS
CS
WAKE
Transient Suppressor
LIN Bus
V
DD
T
XD
R
XD
1.0 µF
I/O
I/O
50
43V
1k
+12
Master Node Only
+12
220 k
Wake-up
Voltage Reg
100 nF
4.7 k
+12
Optional Resistor and
MMBZ27V
(2)
220 pF
(Note 1)
V
BB
L
BUS
V
REN
T
XD
R
XD
V
SS
CS/WAKE
FAULT/T
XE
Transient Suppressor
Note 1: For applications with current requirements of less than 20 mA, the connection to +12V can be deleted and voltage
to the regulator can be supplied directly from the V
REN
pin.
2: ESD protection diode.
MCP2003/4/3A/4A
DS20002230G-page 8
2010-2016 Microchip Technology Inc.
EXAMPLE 1-3: TYP ICAL LIN NETWORK CONFIGURATION
Master
(MCU)
1k
V
BB
Slave 1
(MCU)
40m + Return
LIN Bus
LIN Bus
MCP2000X
LIN Bus
MCP200X
LIN Bus
MCP200X
Slave 2
(MCU)
LIN Bus
MCP200X
Slave n < 23
(MCU)
2010-2016 Microchip Technology Inc. DS20002230G-page 9
MCP2003/4/3A/4A
1.5 Pin Descriptions
TABLE 1-2: PINOUT DESCRIPTIONS
1.5.1 RECEIVE DATA OUTPUT (R
XD
)
The Receive Data Output pin is an Open-Drain (OD)
output and follows the state of the LIN pin, except in
Power-Down mode.
1.5.1.1 R
XD
Monitoring
The R
XD
pin is internally monitored. It has to be at a
high level (> 2.5V typical) while L
BUS
is recessive.
Otherwise, an internal Fault will be created and the
device will transition to Transmitter Off mode. On the
MCP2004/2004A, the FAULT/T
XE
pin will be driven low
to indicate the Transmitter Off state.
1.5.2 CHIP SELECT (CS)
This is the Chip Select input pin. An internal pull-down
resistor will keep the CS pin low. This is done to ensure
that no disruptive data will be present on the bus while
the microcontroller is executing a Power-on Reset and
an I/O initialization sequence. The pin must detect a high
level to activate the transmitter. An internal low-pass
filter, with a typical time constant of 10 µs, prevents
unwanted wake-up (or transition to Power-Down mode)
on glitches.
If CS = 0 when the V
BB
supply is turned on, the device
goes to Ready mode as soon as internal voltages sta-
bilize and stays there as long as the CS pin is held low
(0). In Ready mode, the receiver is on and the LIN
transmitter driver is off.
If CS = 1 when the V
BB
supply is turned on, the device
will proceed to Operation mode or T
OFF
mode (refer to
Figures 1-2 to 1-5) as soon as internal voltages
stabilize.
This pin may also be used as a local wake-up input
(refer to Example 1-1). In this implementation, the
microcontroller I/O controlling the CS should be con-
verted to a high-impedance input, allowing the internal
pull-down resistor to keep CS low. An external switch,
or other source, can then wake-up both the transceiver
and the microcontroller (if powered). Refer to
Section 1.3 “Modes of Operation”, for detailed
operation of CS.
1.5.3 WAKE-UP INPUT (WAKE)
This pin is only available on the MCP2003/2003A.
The WAKE pin has an internal 800 kΩ pull-up to V
BB
.
A falling edge on the WAKE pin causes the device to
wake from Power-Down mode. Upon waking, the
MCP2003/3A will enter Ready mode.
Pin Name 8-Lead
PDIP,
SOIC
4x4
DFN
MCP2003/2003A MCP2004/2004A
Normal Operation Normal Operation
R
XD
1 1 Receive Data Output (OD),
HV tolerant
Receive Data Output (OD),
HV tolerant
CS 2 2 Chip Select (TTL), HV tolerant Chip Select/Local WAKE (TTL),
HV tolerant
WAKE
(MCP2003/2003A only) 3 3 Wake-up, HV tolerant Fault Detect Output (OD),
Transmitter Enable (TTL),
HV tolerant
FAULT/T
XE
(MCP2004/2004A only)
T
XD
4 4 Transmit Data Input (TTL),
HV tolerant
Transmit Data Input (TTL),
HV tolerant
V
SS
5 5 Ground Ground
L
BUS
6 6 LIN Bus (bidirectional) LIN Bus (bidirectional)
V
BB
7 7 Battery Positive Battery Positive
V
REN
8 8 Voltage Regulator Enable Output Voltage Regulator Enable Output
EP — 9 Exposed Thermal Pad; do not
electrically connect or connect
to V
SS
Exposed Thermal Pad; do not
electrically connect or connect
to V
SS
Legend: TTL = TTL Input Buffer; OD = Open-Drain Output
Note: It is not recommended to tie CS high as
this can result in the device entering
Operation mode before the microcontrol-
ler is initialized and may result in
unintentional LIN traffic.
MCP2003/4/3A/4A
DS20002230G-page 10
2010-2016 Microchip Technology Inc.
1.5.4 FAULT/T
XE
This pin is only available on the MCP2004/2004A. This
pin is bidirectional and allows disabling of the transmitter,
as well as Fault reporting related to disabling the
transmitter. This pin is an open-drain output with states
as defined in Table 1-3. The transmitter is disabled
whenever this pin is low (‘0’), either from an internal
Fault condition or by an external drive. While the trans-
mitter is disabled, the internal 30 k pull-up resistor on
the L
BUS
pin is also disconnected to reduce current.
TABLE 1-3: FAULT/T
XE
TRUTH TABLE
1.5.5 TRANSMIT DATA INPUT (T
XD
)
The Transmit Data input pin has an internal pull-up.
The LIN pin is low (dominant) when T
XD
is low and high
(recessive) when T
XD
is high.
For extra bus security, T
XD
is internally forced to ‘1’
whenever the transmitter is disabled, regardless of the
external T
XD
voltage.
1.5.5.1 T
XD
Dominant Time-out
If T
XD
is driven low for longer than approximately
25 ms, the L
BUS
pin is switched to Recessive mode and
the part enters T
OFF
mode. This is to prevent the LIN
node from permanently driving the LIN bus dominant.
The transmitter is reenabled on the T
XD
rising edge.
1.5.6 GROUND (V
SS
)
This is the Ground pin.
1.5.7 LIN BUS (L
BUS
)
The bidirectional LIN Bus pin (L
BUS
) is controlled by the
T
XD
input. L
BUS
has a current-limited open-collector
output. To reduce EMI, the edges, during the signal
changes, are slope controlled, and include corner
rounding control for both falling and rising edges.
The internal LIN receiver observes the activities on the
LIN bus and matches the output signal, R
XD
, to follow
the state of the L
BUS
pin.
1.5.7.1 Bus Dominant Timer
The Bus Dominant Timer is an internal timer that
deactivates the L
BUS
transmitter after approximately
25 ms of Dominant state on the L
BUS
pin. The timer is
reset on any recessive L
BUS
state.
The LIN bus transmitter will be reenabled after a
Recessive state on the L
BUS
pin as long as CS is high.
Disabling can be caused by the LIN bus being
externally held dominant or by T
XD
being driven low.
Additionally, on the MCP2004/2004A, the FAULT pin
will be driven low to indicate the Transmitter Off state.
1.5.8 BATTERY (V
BB
)
This is the Battery Positive Supply Voltage pin.
1.5.9 VOLTAGE REGULATOR ENABLE
OUTPUT (V
REN
)
This is the External Voltage Regulator Enable pin. The
open source output is pulled high to V
BB
in all modes,
except Power-Down.
1.5.10 EXPOSED THERMAL PAD (EP)
Do not electrically connect or connect to V
SS
.
Note: The FAULT/T
XE
pin is true (‘0’) whenever
the internal circuits have detected a short
or thermal excursion and have disabled
the L
BUS
output driver.
T
XD
In R
XD
Out LIN
BUS
I/O Thermal
Override
FAULT/T
XE
Definition
External
Input Driven
Output
LHV
BB
OFF H L FAULT, T
XD
driven low, L
BUS
shorted to V
BB
(Note 1)
HHV
BB
OFF H H OK
LLGND OFF H HOK
HLGND OFF H HOK, data is being received from L
BUS
xxV
BB
ON H L FAULT, transceiver in thermal shutdown
xxV
BB
xLxNO FAULT, the CPU is commanding the
transceiver to turn off the transmitter driver
Legend: x = don’t care.
Note 1: The FAULT/T
XE
is valid after approximately 25 µs after the T
XD
falling edge. This is to eliminate false Fault
reporting during bus propagation delays.
2010-2016 Microchip Technology Inc. DS20002230G-page 11
MCP2003/4/3A/4A
1.6 MCP2003/4 and MCP2003A/4A
Difference Details
The differences between the MCP2003/4 and the
MCP2003A/4A devices are isolated to the wake-up
functionality. The changes were implemented to make
the device more robust to LIN bus conditions outside of
the normal operating conditions. The MCP2003/4 will
wake-up from Power-Down mode during any LIN falling
edge held low longer than 20 µs.
In the case where a LIN system is designed to minimize
standby current by disconnecting all bus pull-up resis-
tors (including the external master pull-up resistor to
V
BB
), the original MCP2003/4 could wake-up if the float-
ing bus drifted to a valid low level. The MCP2003A/4A
revisions were modified to require a rising edge after a
valid low level. This will prevent an undesired system
wake-up in this scenario, while maintaining functional
capability with the original version.
It should be noted that the original MCP2003/4 meets
all LIN transceiver specification requirements and
modules can be designed to pass all LIN system
requirements. However, when all bus pull-up resistors
are disconnected, the MCP2003/4 requires the module
designer to write firmware to monitor the LIN bus, after
any wake-up event, to prevent the transceiver from
automatically transitioning from Ready mode to
Operational mode.
If the MCP2003/4 is placed into Operational mode, the
V
BB
to L
BUS
pull-up resistor is automatically connected,
which will raise the LIN bus to a Recessive level; then
putting the device into Power-Down mode may cause
L
BUS
to be floating, and thus, wake-up all bus nodes. To
prevent this, the designer should ensure T
XD
(MCP2003)
or T
XE
(MCP2004) is held low until valid bus activity is
verified (see Figure 1-6). This will ensure the transceiver
transitions from Ready mode to Transmitter Off mode
until bus activity can be verified.
In the case of valid bus activity, the transceiver can shift to
Operation mode; while if there is no bus activity, the
device can again be placed into Power-Down mode. The
design practices needed to accomplish this are fully
detailed in Tech Brief TB3067, “MCP2003 Power-Down
Mode and Wake-up Handling in the Case of LIN Bus
Loss” (DS93067).
The revised MCP2003A/4A devices now eliminate the
need for firmware to prevent system wide wake-up.
The revised devices now require a longer valid bus low
(see updated t
BDB
value in Section 2.3 “DC Specifi-
cations” and Figure 2-7), which enables a rising edge
detect circuit. The device will now only wake-up after a
rising edge, following a low longer than t
BDB
. While
the module designer can still hold T
XD
(MCP2003) or
T
XE
(MCP2004) low during wake-up to enter Transmitter
Off mode from Ready mode, it is not required to prevent
an advertent system wake-up.
In addition to the longer t
BDB
value, the time from wake-
up detect to V
REN
enable is shortened, as documented
in Section 2.3 “DC Specifications”.
FIGURE 1-6: MCP20 03/2 004 SWITCHING TIMING DIAGRAM FOR THE FORCED
POWER-DOWN MODE SEQUENCE
TXD
VREN
CS
Ready
Mode
Transmitter Off
Mode
Power-Down
Mode after Master
SLEEP Instruction
Power-Down
Mode
t
Tx2CS
QV
tCSactive
V
T
XD
to ‘0’
Forced
Externally
T
XD
State Depending
on how the Slave
Microcontroller is
Powered
LBUS
State
LIN Bus
Disconnected
MCP2003/4/3A/4A
DS20002230G-page 12
2010-2016 Microchip Technology Inc.
2.0 ELECTRICAL CHARACTERISTICS
2.1 Absolute Maximum Ratings†
V
IN
DC Voltage on R
XD
, T
XD
, FAULT/T
XE
, CS .............................................................................................. -0.3 to +43V
V
IN
DC Voltage on WAKE and V
REN
............................................................................................................. -0.3 to +V
BB
V
BB
Battery Voltage, Continuous, Non-Operating (Note 1)........................................................................... -0.3 to +40V
V
BB
Battery Voltage, Non-Operating (LIN bus recessive) (Note 2)............................................................... -0.3 to +43V
V
BB
Battery Voltage, Transient ISO 7637 Test 1 ..................................................................................................... -200V
V
BB
Battery Voltage, Transient ISO 7637 Test 2a ...................................................................................................+150V
V
BB
Battery Voltage, Transient ISO 7637 Test 3a ................................................................................................... -300V
V
BB
Battery Voltage, Transient ISO 7637 Test 3b ...................................................................................................+200V
V
LBUS
Bus Voltage, Continuous ..................................................................................................................... -18 to +40V
V
LBUS
Bus Voltage, Transient (Note 3).......................................................................................................... -27 to +43V
I
LBUS
Bus Short-Circuit Current Limit ....................................................................................................................200 mA
ESD Protection on LIN, V
BB
, WAKE (IEC 61000-4-2) (Note 4).............................................................................. ±8 KV
ESD Protection on LIN, V
BB
(Human Body Model) (Note 5).................................................................................. ±8 KV
ESD Protection on All Other Pins (Human Body Model) (Note 5).......................................................................... ±4 KV
ESD Protection on All Pins (Charge Device Model) (Note 6)................................................................................. ±2 KV
ESD Protection on All Pins (Machine Model) (Note 7)............................................................................................±200V
Maximum Junction Temperature ............................................................................................................................. 150C
Storage Temperature...................................................................................................................................-65 to +150C
Note 1: LIN 2.x compliant specification.
2: SAE J2602 compliant specification.
3: ISO 7637/1 load dump compliant (t < 500 ms).
4: According to IEC 61000-4-2, 330 ohm, 150 pF and Transceiver EMC Test Specifications [2] to [4]. For
WAKE pin to meet the specification, a series resistor must be in place (refer to Example 1-2).
5: According to AEC-Q100-002/JESD22-A114.
6: According to AEC-Q100-011B.
7: According to AEC-Q100-003/JESD22-A115.
2.2 Nomenclature Used in This Document
Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent
values are shown below.
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device, at those or any other conditions above
those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
LIN 2.1 Name Term Used in the Following Tables Definition
V
BAT
not used ECU operating voltage
V
SUP
V
BB
Supply voltage at device pin
I
BUS_LIM
I
SC
Current limit of driver
V
BUSREC
V
IH(LBUS)
Recessive state
V
BUSDOM
V
IL(LBUS)
Dominant state
2010-2016 Microchip Technology Inc. DS20002230G-page 13
MCP2003/4/3A/4A
2.3 DC Specifications
DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for
V
BB
= 6.0V to 30.0V, T
A
= -40°C to +125°C
Parameter Sym. Min. Typ. Max. Units Conditions
Power
V
BB
Quiescent Operating
Current
I
BBQ
— 90 150 µA Operating mode, bus is
Recessive (Note 1)
V
BB
Transmitter Off
Current
I
BBTO
— 75 120 µA Transmitter off, bus is
Recessive (Note 1)
V
BB
Power-Down Current I
BBPD
—5 15µA
V
BB
Current
with V
SS
Floating
I
BBNOGND
-1 — 1 mA V
BB
= 12V, GND to V
BB
,
V
LIN
=0-27V
Microcontroller Interface
High-Level Input Voltage
(T
XD
, FAULT/T
XE
)
V
IH
2.0 — 30 V
Low-Level Input Voltage
(T
XD
, FAULT/T
XE
)
V
IL
-0.3 — 0.8 V
High-Level Input Current
(T
XD
, FAULT/T
XE
)
I
IH
-2.5 — — µA Input voltage = 4.0V
Low-Level Input Current
(T
XD
, FAULT/T
XE
)
I
IL
-10 — — µA Input voltage = 0.5V
High-Level Voltage (V
REN
)V
HVREN
-0.3 — V
BB
+ 0.3 V
High-Level Output Current
(V
REN
)
I
HVREN
-40 — -10 mA Output voltage = V
BB
– 0.5V
-125 — -35 Output voltage = V
BB
-2.0V
High-Level Input Voltage
(CS)
V
IH
2.0 — 30 V Through a current-limiting
resistor
Low-Level Input Voltage
(CS)
V
IL
-0.3 — 0.8 V
High-Level Input Current
(CS)
I
IH
— — 10.0 µA Input voltage = 4.0V
Low-Level Input Current
(CS)
I
IL
— — 5.0 µA Input voltage = 0.5V
Low-Level Input Voltage
(WAKE)
V
IL
V
BB
– 4.0V — — V
Low-Level Output Voltage
(R
XD
)
V
OL
—— 0.4 VI
IN
= 2 mA
High-Level Output Current
(R
XD
)
I
OH
-1 — -1 µA V
LIN
= V
BB
, V
RXD
= 5.5V
Note 1: Internal current limited; 2.0 ms maximum recovery time (R
LBUS
= 0, TX = 0.4 V
REG
, V
LBUS
= V
BB
).
2: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
MCP2003/4/3A/4A
DS20002230G-page 14
2010-2016 Microchip Technology Inc.
Bus Interface
High-Level Input Voltage V
IH(LBUS)
0.6 V
BB
— — V Recessive state
Low-Level Input Voltage V
IL(LBUS)
-8 — 0.4 V
BB
V Dominant state
Input Hysteresis V
HYS
— — 0.175 V
BB
VV
IH(LBUS)
– V
IL(LBUS)
Low-Level Output Current I
OL(LBUS)
40 — 200 mA Output voltage = 0.1 V
BB
,
V
BB
= 12V
High-Level Output Current I
OH(LBUS)
—— 20µA
Pull-up Current on Input I
PU(LBUS)
5—180µA~30k internal pull-up
@ V
IH(LBUS)
= 0.7 V
BB
Short-Circuit Current Limit I
SC
50 — 200 mA (Note 1)
High-Level Output Voltage V
OH(LBUS)
0.9 V
BB
—V
BB
V
Driver Dominant Voltage V_
LOSUP
—— 1.2 VV
BB
= 7V, R
LOAD
= 500
Driver Dominant Voltage V_
HISUP
—— 2.0 VV
BB
= 18V, R
LOAD
= 500
Driver Dominant Voltage V_
LOSUP
–1k 0.6 — — V V
BB
= 7V, R
LOAD
= 1 k
Driver Dominant Voltage V_
HISUP
–1k 0.8 — — V V
BB
= 18V, R
LOAD
= 1 k
Input Leakage Current
(at the receiver during
Dominant bus level)
I
BUS_PAS_DOM
-1 -0.4 — mA Driver off, V
BUS
= 0V,
V
BB
= 12V
Input Leakage Current
(at the receiver during
Recessive bus level)
I
BUS_PAS_REC
— 12 20 µA Driver off, 8V < V
BB
< 18V,
8V < V
BUS
< 18V,
V
BUS
V
BB
Leakage Current
(disconnected from ground)
I
BUS_NO_GND
-10 1.0 +10 µA GND
DEVICE
= V
BB
,
0V < V
BUS
< 18V,
V
BB
= 12V
Leakage Current
(disconnected from V
BB
)
I
BUS_NO_VBB
—— 10µAV
BB
= GND,
0 < V
BUS
< 18V (Note 2)
Receiver Center Voltage V
BUS_CNT
0.475 V
BB
0.5 V
BB
0.525 V
BB
VV
BUS_CNT
= (V
IL(LBUS)
+
V
IH(LBUS)
/2
Slave Termination R
SLAVE
20 30 47 k
Capacitance of Slave
Node
C
SLAVE
—— 50pF
2.3 DC Specifications (Continued)
DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for
V
BB
= 6.0V to 30.0V, T
A
= -40°C to +125°C
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Internal current limited; 2.0 ms maximum recovery time (R
LBUS
= 0, TX = 0.4 V
REG
, V
LBUS
= V
BB
).
2: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
2010-2016 Microchip Technology Inc. DS20002230G-page 15
MCP2003/4/3A/4A
2.4 AC Specifications
AC Characteristics Electrical Characteristics: Unless otherwise indicated, all limits are specified for
V
BB
= 6.0V to 27.0V; T
A
= -40°C to +125°C
Parameter Sym. Min. Typ. Max. Unit s Test Conditions
Bus Interface – Constant Slope Time Parameters
Slope Rising and Falling Edges t
SLOPE
3.5 — 22.5 µs 7.3V V
BB
18V
Propagation Delay of
Transmitter
t
TRANSPD
——4.0µst
TRANSPD
= max (t
TRANSPDR
or
t
TRANSPDF
)
Propagation Delay of Receiver t
RECPD
——6.0µst
RECPD
= max (t
RECPDR
or t
RECPDF
)
Symmetry of Propagation
Delay of Receiver Rising Edge
w.r.t. Falling Edge
t
RECSYM
-2.0 — 2.0 µs t
RECSYM
= max (t
RECPDF
– t
RECPDR
)
R
RXD
2.4 to V
CC
, C
RXD
20 pF
Symmetry of Propagation
Delay of Transmitter Rising
Edge w.r.t. Falling Edge
t
TRANSSYM
-2.0 — 2.0 µs t
TRANSSYM
= max
(t
TRANSPDF
– t
TRANSPDR
)
Time to Sample FAULT/T
XE
for
Bus Conflict Reporting
t
FAULT
——32.5µst
FAULT
= max
(t
TRANSPD
+
TSLOPE
+ t
RECPD
)
Duty Cycle 1 @ 20.0 kbit/sec 0.396 — — — C
BUS
; R
BUS
Conditions:
1nF; 1k | 6.8 nF; 660 | 10 nF; 500,
TH
REC(MAX)
= 0.744 x V
BB
,
TH
DOM(MAX)
= 0.581 x V
BB
,
V
BB
= 7.0V – 18V, t
BIT
= 50 µs,
D1 = t
BUS_REC(MIN)
/2 x t
BIT
)
Duty Cycle 2 @ 20.0 kbit/sec — — 0.581 — C
BUS
; R
BUS
Conditions:
1nF; 1k | 6.8 nF; 660 | 10 nF; 500,
TH
REC(MAX)
= 0.284 x V
BB
,
TH
DOM(MAX)
= 0.422 x V
BB
,
V
BB
= 7.6V – 18V, t
BIT
= 50 µs,
D2 = t
BUS_REC(MAX)
/2 x t
BIT
)
Duty Cycle 3 @ 10.4 kbit/sec 0.417 — — — C
BUS
; R
BUS
Conditions:
1nF; 1k | 6.8 nF; 660 | 10 nF; 500,
TH
REC(MAX)
= 0.778 x V
BB
,
TH
DOM(MAX)
= 0.616 x V
BB
,
V
BB
= 7.0V – 18V, t
BIT
= 96 µs,
D3 = t
BUS_REC(MIN)
/2 x t
BIT
)
Duty Cycle 4 @ 10.4 kbit/sec — — 0.590 — C
BUS
; R
BUS
Conditions:
1nF; 1k | 6.8 nF; 660 | 10 nF; 500,
TH
REC(MAX)
= 0.251 x V
BB
,
TH
DOM(MAX)
= 0.389 x V
BB
,
V
BB
= 7.6V – 18V, t
BIT
= 96 µs,
D4 = t
BUS_REC(MAX)
/2 x t
BIT
Wake-up Ti ming
Bus Activity Debounce Time t
BDB
5 — 20 µs MCP2003/2004
30 70 125 µs MCP2003A/2004A
Bus Activity to V
REN
On t
BACTVE
35 — 150 µs MCP2003/2004
10 30 90 µs MCP2003A/2004A
WAKE to V
REN
On t
WAKE
——150µs
Chip Select to V
REN
On t
CSOR
——150µsV
REN
floating
Chip Select to V
REN
Off t
CSPD
——80µsV
REN
floating
MCP2003/4/3A/4A
DS20002230G-page 16
2010-2016 Microchip Technology Inc.
2.5 Thermal S pecifications(1)
Parameter Symbol Typ. Max. Units Test Conditions
Recovery Temperature
RECOVERY
+140 — C
Shutdown Temperature
SHUTDOWN
+150 — C
Short-Circuit Recovery Time t
THERM
1.5 5.0 ms
Thermal Package Resistances
Thermal Resistance, 8L-DFN
JA
35.7 — C/W
Thermal Resistance, 8L-PDIP
JA
89.3 — C/W
Thermal Resistance, 8L-SOIC
JA
149.5 — C/W
Note 1: The maximum power dissipation is a function of T
JMAX
,
JA
and ambient temperature, T
A
. The maximum
allowable power dissipation at an ambient temperature is P
D
= (T
JMAX
– T
A
)
JA
. If this dissipation is
exceeded, the die temperature will rise above +150C and the device will go into thermal shutdown.
2010-2016 Microchip Technology Inc. DS20002230G-page 17
MCP2003/4/3A/4A
2.6 Typical Performance Curves
Note: Unless otherwise indicated, V
BB
= 6.0V to 18.0V, T
A
= -40°C to +125°C.
FIGURE 2-1: TYPICAL I
BBQ
FIGURE 2-2: TYPICAL I
BBPD
FIGURE 2-3: TYPICAL I
BBTO
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
6 7.3 12 14.4 18
VBB (V)
Current (mA)
-40C
25C
85C
125C
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
6 7.3 12 14.4 18
VBB (V)
Current (mA)
-40C
25C
85C
125C
0
0.02
0.04
0.06
0.08
0.1
0.12
6V 7.3V 12V 14.4V 18V
VBB (V)
Current (mA)
-40C
25C
85C
125C
MCP2003/4/3A/4A
DS20002230G-page 18
2010-2016 Microchip Technology Inc.
2.7 Timing Diagrams and Specifications
FIGURE 2-4: BUS TIMING DIAGRAM
FIGURE 2-5: CS TO V
REN
TIMING DIAGRAM
.95 V
LBUS
0.05 V
LBUS
T
TRANSPDR
T
RECPDR
T
TRANSPDF
T
RECPDF
T
XD
L
BUS
R
XD
Internal T
XD
/R
XD
Compare
FAULT Sampling
T
FAULT
T
FAULT
FAULT/T
XE
Output Stable StableStable
Match MatchMatch Match Match
Hold
Value
Hold
Value
50%
50%
.50 V
BB
50%
50%
0.0V
T
CSPD
T
CSOR
CS
V
REN
V
BB
Off
2010-2016 Microchip Technology Inc. DS20002230G-page 19
MCP2003/4/3A/4A
FIGURE 2-6: MCP2003/4 REMOTE WAKE-UP
FIGURE 2-7: MCP2003A/4A REMOTE WAKE-UP
tBDB
tBACTIVE
LBUS
0.4 VBB
VBB
VREN
tBDB
tBACTIVE
LBUS
0.4 VBB
VBB
VREN
MCP2003/4/3A/4A
DS20002230G-page 20
2010-2016 Microchip Technology Inc.
3.0 PACKAGING INFORMATION
3.1 Package Marking Information
Example:8-Lead DFN (4x4x0.9 mm)
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC
®
designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
8-Lead PDIP (300 mil)
8-Lead SOIC (150 mil) Example:
NNN
MCP2003E
SN^^ 1642
256
3
e
Example:
MCP2003
E/P^^ 256
1642
3
e
2003
E/MD^^
1642
256
3
e
2010-2016 Microchip Technology Inc. DS20002230G-page 21
MCP2003/4/3A/4A
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
MCP2003/4/3A/4A
DS20002230G-page 22
2010-2016 Microchip Technology Inc.
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
2010-2016 Microchip Technology Inc. DS20002230G-page 23
MCP2003/4/3A/4A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2003/4/3A/4A
DS20002230G-page 24
2010-2016 Microchip Technology Inc.
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
D
E1
c
C
PLANE
.010 C
12
N
NOTE 1
TOP VIEW
END VIEWSIDE VIEW
e
2010-2016 Microchip Technology Inc. DS20002230G-page 25
MCP2003/4/3A/4A
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b.014 .018 .022
Overall Row Spacing eB - - .430
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
1.
protrusions shall not exceed .010" per side.
2.
4.
Notes:
§
--
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
e
DATUM A DATUM A
e
b
e
2
b
e
2
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
MCP2003/4/3A/4A
DS20002230G-page 26
2010-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2016 Microchip Technology Inc. DS20002230G-page 27
MCP2003/4/3A/4A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2003/4/3A/4A
DS20002230G-page 28
2010-2016 Microchip Technology Inc.
!"#$%
& !"#$%&"'""($)%
*++&&&!!+$
2010-2016 Microchip Technology Inc. DS20002230G-page 29
MCP2003/4/3A/4A
APPENDIX A: REVISION HISTORY
Revision G (December 2016)
The following is the list of modifications”
1. Added note to page 1 header: “Not recommended
for new designs”.
2. Updated Section 3.1 “Package Marking
Information”.
3. Minor typographical corrections.
Revision F (November 2014)
The following is the list of modifications:
1. Updated typical application circuits with values
used during ESD tests.
Revision E (October 2013)
The following is the list of modifications:
1. Added additional specification for I
HVREN
in
Section 2.3 “DC Specifications”.
2. Clarified wake-up on L
BUS
functionality.
3. Added R
XD
monitoring description.
Revision D (December 2011)
The following is the list of modifications:
1. Added the MCP2003A and MCP2004A devices
and related information throughout the docu-
ment.
2. Updated Figures 1.2, 1.3, 1.4, 1.5, 2.6, 2.7.
Revision C (August 2010)
The following is the list of modifications:
1. Updated all references of Sleep mode to Power-
Down mode, and updated the Max. parameter
for Duty Cycle 2 in Section 2.4 “AC Specifica-
tions”.
Revision B (July 2010)
The following is the list of modifications:
1. Added Section 2.2 “Nomenclature Used in
This Document”, and added the “Capacitance
of Slave Node” parameter to Section 2.3 “DC
Specifications”.
Revision A (March 2010)
• Original release of this document.
MCP2003/4/3A/4A
DS20002230G-page 30
2010-2016 Microchip Technology Inc.
NOTES:
2010-2016 Microchip Technology Inc. DS20002230G-page 31
MCP2003/4/3A/4A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office
.
PART NO. X/XX
PackageTemperature
Range
Device
Device: MCP2003: LIN Transceiver with WAKE pins, wake-up on
falling edge of LBUS
MCP2003T: LIN Transceiver with WAKE pins, wake-up on
falling edge of LBUS (Tape and Reel) (DFN and
SOIC only)
MCP2003A: LIN Transceiver with WAKE pins, wake-up on
rising edge of LBUS
MCP2003AT: LIN Transceiver with WAKE pins, wake-up on
rising edge of LBUS (Tape and Reel) (DFN and
SOIC only)
MCP2004: LIN Transceiver with FAULT/TXE pins, wake-up
on falling edge of LBUS
MCP2004T: LIN Transceiver with FAULT/TXE pins, wake-up
on falling edge of LBUS (Tape and Reel) (DFN
and SOIC only)
MCP2004A: LIN Transceiver with FAULT/TXE pins, wake-up
on rising edge of LBUS
MCP2004AT: LIN Transceiver with FAULT/TXE pins, wake-up
on rising edge of LBUS (Tape and Reel) (DFN
and SOIC only)
Temperature Range: E = -40°C to +125°C
Package: MD = Plastic Dual Flat, No Lead Package – 4x4x0.9mm
Body, 8-Lead
P = Plastic Dual In-Line – 300 mil Body, 8-Lead
SN = Plastic Small Outline – Narrow 3.90 mm Body, 8-Lead
Examples:
a) MCP2003A-E/MD: Extended Temperature,
8L-DFN package
b) MCP2003A-E/P: Extended Temperature,
8L-PDIP package
c) MCP2003A-E/SN: Extended Temperature,
8L-SOIC package
d) MCP2003AT-E/MD: Tape and Reel,
Extended Temperature,
8L-DFN package
e) MCP2003AT-E/SN: Tape and Reel,
Extended Temperature,
8L-SOIC package
a) MCP2004-E/MD: Extended Temperature,
8L-DFN package
b) MCP2004-E/P: Extended Temperature,
8L-PDIP package
c) MCP2004A-E/SN: Extended Temperature,
8L-SOIC package
d) MCP2004AT-E/MD: Tape and Reel,
Extended Temperature,
8L-DFN package
e) MCP2004AT-E/SN: Tape and Reel,
Extended Temperature,
8L-SOIC package
MCP2003/4/3A/4A
DS20002230G-page 32
2010-2016 Microchip Technology Inc.
NOTES:
2010-2016 Microchip Technology Inc. DS20002230G-page 33
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, K
EE
L
OQ
,
K
EE
L
OQ
logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2016, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-1230-4
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microch ip rece iv ed ISO/T S -16 94 9:20 09 certifi cat i on for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPI C
®
DSCs, KEELOQ
®
code hoppi ng
devices, Serial EEPROMs, microperiph erals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20002230G-page 34
2010-2016 Microchip Technology Inc.
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11/07/16
