This document provides an overview of the MPC535/MPC536 microcontrollers, including a
block diagram showing the major modular components, sections that list the major features,
and dif ferences be tween the MPC535/MPC536 and t he MPC555. The MPC535 and MPC536
devices are me mbers of the Motorol a MPC500 RISC Microcontr oller family. The parts her ein
will be referred to only as MPC535 unless specific parts need to be referenced.
1 Introduction
The MPC535 device offers the following features:
•PowerPC
™ core with a floating point unit (FPU) and a burst buffer controller (BBC)
• Unified system int egr at ion unit (USI U), a fl exible memory control l er, and impro ved
interrupt contro ller
• 1 Mbyte of Flash memory (UC3F)
— Typical endurance of 100,000 write/erase cycles @ 25ºC
— Typical data retention of 100 years @ 25ºC
• 36 Kbytes of static RAM (two CALRAM modules)
— 8 Kbytes of normal access or overlay access (sixteen 512-byte regions)
— 4 Kbytes in CALRAM A, 4 Kbytes in CALRAM B
• A 22-timer channel modular I/O system (MIOS14)
— Same as MIOS1 plus a real-time clock sub-module (MRTCSM), 4 counter
sub-modules (MCSM), and 4 PWM sub-modules (MPWMSM)
• One TouCAN module (TouCAN_B)
• One enhanced queued analog to digital converter (QADC64E A).
• One queued serial multi-channel module (QSMCM A) which contains a queued
serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)
•-40
°C – 85°C ambient temperature
Table 1. MPC535/MPC536 Features
Device Flash Code Compress ion
MPC535 1 Mbyte Code compression not supported
MPC536 1 Mbyte Code compression supported
Product Brief
MPC535PB/D
Rev. 0, 2/2003
MPC535/MPC536
Product Brief
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
2MPC535/MPC536 Product Brief MOTOROLA
Block Diagram
• Debug features:
— A Nexus debug port (class 3) – IEEE-ISTO 5001-1999
— JTAG and background debug mode (BDM)
• Packaging and Electrical
1.1 Block Diagram
Figure 1 is a block diagram of the MPC535.
Figure 1. MPC535 Block Di agram
1.2 Detailed Feature List
The MPC535 key features are explained in the following sections.
1.2.1 High Performance CPU System
• Fully static design
• Four major power saving modes
— On, doze, sleep, deep- sl eep and power-down
E-Bus
MPC500
Core
L-Bus
U-Bus
IMB3
Flash
512 Kbytes
+
FP
USIU
Flash
512 Kbytes
L2U
I/F
UIMB
MIOS14
READI
JTAG
QADC64E QSMCM
Tou
32 Kbyte CALRAM A
4 Kbyte Overlay
4 Kbyte CALRAM B
4 Kbyte Overlay
CAN
Buffer
Burst
Controller 2
DECRAM
(4Kbytes)
28 Kbytes SRAM
No Overlay
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MOTOROLA MPC535/MPC536 Product Brief 3
Detailed Feature List
1.2.2 RISC MCU Central Processing Unit (RCPU)
• High-performance core
— PowerPC single issue integer core
— Precise exception model
— Floating point
— Code compression (MPC536 only)
– Compression reduces usage of internal or external Flash memory
– Compression optimized for automotive (non-cached) applications
– New compression scheme decreases code size to 40% –50% of source
1.2.3 MPC500 System Interface (USIU)
• MPC500 system interface (USIU, BBC, L2U)
• Periodic interrupt timer, bus monitor, clocks, decrementer and time base
• Clock synthesizer, power management, reset controller
• External bus tolerates 5-V inputs, provides 2.6-V outputs
• Enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40
internal interrupts
• IEEE 1149.1 JTAG test access port
• Bus supports multiple master designs
• USIU supports dual-mapping of Flash to move part of internal Flash memory to external bus for
development
• External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions
per memory cycle
1.2.4 Burst Buffer Controller (BBC) Module
• Exception vector table relocation features allow exception table to be relocated to following
locations:
— 0x0000 0000 - 0x0000 1FFF (normal MPC500 exception table location)
— 0x0001 0000 - 0x0001 1FFF (0 + 64 Kbytes; second page of internal Flash)
— Second internal Flash module
— Intern al SRAM
— 0x0FFF_0100 (external memory space; normal MPC500 exception table location)
1.2.5 Flexible Memory Protection Unit
• Flexible memory protection units in BBC (IMPU) and L2U (DMPU)
• Default attributes available in one global entry
• Attribute support for speculative accesses
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
4MPC535/MPC536 Product Brief MOTOROLA
Detail e d Feat u re List
1.2.6 Memory Controller
• Flexible chip selects via memory controller
• 24-bit address and 32-bit data buses
• 4- to 16-Mbyte (data) or 4-Gbyte (instruction) region size support
• Four-beat transfer bursts, two-clock minimum bus transactions
• Use with SRAM, EPROM, Flash and other peripherals
• Byte selects or write enables
• 32-bit address decodes with bit masks
• Four instruction regions
• Four data regions
1.2.7 1 Mbyte of CDR3 Flash EEPROM Memory (UC3F)
•1 Mbyte Flash
— Two UC3F modules, 512 Kbytes each
• Page mode read
• Block (64 -Kbyte) erasable
• External 4.75- to 5.25-V VPP program and erase power supply
• Typical endurance of 100,000 write/erase cycles @ 25ºC
• Typical data retention of 100 years @ 25ºC
1.2.8 36-Kbyte Static RAM (CALRAM)
• 36-Kbyte static calibration RAM
— Composed of 4-Kbyte and 32-Kbyte CALRAM modules
• Fast ac cess: one clock
• Keep-alive power
• Soft defect detection (SDD)
• 4 Kbyte calibration (overlay) RAM per module (8 Kbytes total)
• Eight 512-byte overlay regions per module (16 regions total)
1.2.9 General Purpose I/O Support (GPIO)
• General-purpose I/O support
• Address (24) and data (32) pins can be used as GPIO in single-chip mode
• 16 GPIO in MIOS14
• Many peripheral pins can be used as GPIO when not used as primary functions
• 5-V outputs with slew rate control
1.2.10 Debug Features
• Extensive system debug support
• On-chip watchpoints and breakpoints
• Program flow tracking
• Background debug mode (BDM)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MOTOROLA MPC535/MPC536 Product Brief 5
Detailed Feature List
1.2.10. 1 Nexus Debug Port (Class 3)
• Nexus/IEEE – ISTO 5001-1999 debug port (Class 3)
• Nine- or 16-pin interface
1.2.11 Integrated I/O System
• True 5-V I/O
1.2.11.1 22-Channel Modul ar I/O System (MIOS14)
• 22-c hann el MIOS timer (MIOS14 )
• Six modulus counter submodules (MCSM)
— Four additional MCSM submodules compared to MIOS1
• 10 double action submodules (DASM).
• 12 dedicated PWM submodules (PWMSM)
— Four additional PWM submodules compared to MIOS1 (shared with MIOS GPIO pins)
• MIOS real-time clock submodule (MRTCSM) provides low power clock/counter
— Requires external 32-KHz crystal
— Uses four pins: two for 32-KHz crystal, two for power/ground.
1.2.12 One Enhanced Queued Analog-to-Digital Converter
Module (QADC64E)
• One enhanced queued analog to digital converter (QADC64E A) with 16 total analog channels.
• 10 bit A/D converter with internal sam ple/hold
— Typical conversion time is 4 µs (250-Kbyte samples/sec)
— Two conversion command queues of variable length
• Automated queue modes initiated by:
— External edge trigger/level gate
— Software co mman d
— Periodic/interval timer, assignable to both queue 1 and 2
• 64 result registers
— Output data is right or left justified, signed or unsigned
• Conversions alternate reference (ALTREF) pin. This pin can be connected to a different reference
voltage
1.2.13 One CAN 2.0B Controller (TouCAN) Module
• One TouCAN module (TouCAN_B)
• 16 message buffers, programmable I/O mode
• Maskable interrupts
• Programmable loopback for self-test operation
• Independent of the transmission medium (external transceiver is assumed)
• Open network architecture, multimaster concept
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
6MPC535/MPC536 Product Brief MOTOROLA
Detail e d Feat u re List
• Hig h imm unity to EMI
• Short latency time for high-priority messages
• Low power sleep mode, with programmable wake up on bus activity
1.2.14 Queued Serial Multi-Channel Module (QSMCM)
• One queued serial module with one queued-SPI and two SCI (QSMCM_A)
— QSMCM_A matches full MPC555 QSMCM functionality
• Queued-SPI
— Provides full-duplex communication port for peripheral expansion or interprocessor
communication
— Up to 32 preprogrammed transfers, reducing overhead
— Synchronous serial interface with baud rate of up to system clock / 4
— Four programmable peripheral-select pins support up to 16 devices
— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient
interfaci ng to serial analog-to-digital (A/D) converters
•SCI
— UART mode provides NRZ format and half- or full-duplex interface
— 16 regi ster receive buffer and 16 regi ster transmit buffer on o ne SCI
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separate transmitter and receiver enable bits, and double buffering of data
— Wake-up functions allow the CPU to run unint errupted u ntil ei ther a true id le lin e is de tecte d,
or a new address byte is received
1.2.15 Electrical Specifications and Packaging
• 40 MHz operation
•-40
°C – 85°C ambient temperature
•2.6 V ± 0.1 V external bus
— External bus is compatible with external memory devices operating from 2.5 V to 3.4 V.
— Extended voltage range (2.7 – 3.4 V) degrades data drive timing by 1.1 ns on date writes.
•2.6
± 0.1 V internal logic
• 5-V I/O (5. 0 ± 0.25 V)
• Plasti c ball grid arr ay (PBGA) pack agi ng
– 388 ball PBGA
– 27 mm x 27 mm body size
• 1.0 mm ball pitch
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MOTOROLA MPC535/MPC536 Product Brief 7
MPC535 Optional Features
1.3 MPC535 Optional Featur es
The following features of the MPC535 are optional features and may not appear in certain configurations:
•40-MHz operation
• MPC536 supports code compression
2 Differences between the MPC535 and the MPC555
The MPC535 is an enhanced version of the MPC555. Most functional features of the MPC555 are
unchanged on the MPC535. Table 2 shows the high level differences.
Table 2. Differences Between Modules of the MPC555 and the MPC535
Module MPC555 MPC535
CPU Core No Change
BBC BBC BBC with improved code compression 1
1Available on some options.
L2U No Change
SRAM 26-Kbytes 36-Kbyte CALRAM with overlay features
Flash 448-Kbyte CMF 1-Mbyte UC3F
(new programming, etc.)
USIU USIU USIU with enhanced interrupt controller
JTAG No Change
READI None New Modul e
UIMB No Change
QADC64 2 QADC64 (16 channels on each QADC
for 32 total channels) 1 QADC64E
( 16 channels accessible)
QSMCM (1) No Change (1)
MIOS MIOS1 MIOS14: MIOS1 with real-time clock
(MR TCSM), 4 m ore PWMSMs and 4 more
MCSMs
TouCAN (2) No Change (1)
Power Supplies
— 40 MHz with two power supplies:
nominal 3.3-V to 5.0-V power supplies 40 MHz with two power supplies :
5.0-V I/O, 2.6-V internal logic
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
8MPC535/MPC536 Product Brief MOTOROLA
Additional MPC535 Differences
2.1 Additional MPC535 Differences
The following are additional differences between the MPC555 and the MPC535.
• SPI (MISO, MOSI, and SCK) pin drive.
— MPC535 provides 21-ns rise/fall with 200-pf load using CMOS (20%/70%) levels
• GPIO on MODCK1 pin outputs only 2.6 V
— MODCK1 pin is in keep-alive power section with no 5-V rail available
— 5.0-V compatibility modes
– Input is 5-V friendly
– 2.6-V outp ut has less slew rate co ntrol
– 2.6-V: VOH = 2.3 V
• Power supplies for external bus pins
— QVDDL is quiet supply to hold non-switching outputs quiet even when noisy supply
(NVDDL) sags
— QVDDL supplies pre-drive and other pad logic
— NVDDL only supplies final PMOS driver stage
— QVDDL and NVDDL shorted on customer board after filtering
• Pull-up and pull-down changes during PORESET and HRESET
— All 2.6-V/5-V pads (external bus: address/data/control) pull down at reset
— All 5-V pads pull up at reset
— Additional control granularity in the PDMCR register
• No pull-ups on QSMCM SCI receive pads
• A_RXD1_QGPI1, A_RXD2_QGPI2 pins do not have weak pull-up during reset or any other time
• CLKOUT has 3 drive strength options
— Bett er matches drive to req uir em en ts to reduce EMI
— 25, 50, 100 pf instead of 45 and 90 pf
• Change reset value of ENGCLK to maximum divide (crystal/128)
— For a 4-MHz crystal, this is 31.25 KHz
– ENGCLK is selectable between 2.6 V and 5 V
• A daisy chain between UC3F modules allows either module to provide the reset configuration
word (RCW)
• Censorship operation
— A RCW bit cont r ols whet her or not the e nti re UC3F can be e ras ed whi l e ce nsor shi p i s vi ol at ed
• BBC SPRs (PPC regs) access in two clocks instead of one clock
• CALRAM internal protection block size is 8 Kbytes
— Instead of 4 Kbytes on MPC555 LRAM
• CALRAM causes machine check exception instead of data storage interrupt (DSI) exception in
cer tain ca ses
— For non-overlay CPU core accesses, a DSI exception is taken
— For overlay accesses and any non-core access (slave mode), a machine check exception is
taken
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MOTOROLA MPC535/MPC536 Product Brief 9
Additional MPC535 Differences
• CALRAM causes DSI exception only if the data relocation (DR) bit in the core machine state
register, MSR[DR ], is set.
— L2U on MPC555 already followed this protocol, but the LRAM did not. Now all L-bus
periphe rals follo w this prot oco l.
— The MSR[DR] bit is des cribed in the reference m anual for mo re information.
• Four additional PRDS control bits were added to the USIU to allow more granularity of PRDS
control on a part
• BBC includes a 4-Kbyte DECRAM that can be used if compression is not used or is not available.
3 SRAM Keep-Alive Power Behavior
The SRAM has three keep-alive power pins (VDDSRAM1, VDDSRAM2, and VDDSRAM3). These pins
provide keep-alive power to the SRAM arrays in the CALRAM modules.
The VDDSRAM1 pin powers the 32-Kbyte CALRAM A during keep-alive while power is off to the
MPC535 (except for the keep-alive power sup plies). CALRAM A keeps all of its 32 Kbytes powered during
power down.
The VDDSRAM2 pin power s t he 4-Kbyte CALRAM B module. Th e CALRAM module s o nly power th ei r
arrays from the VDDSRAM pins during keep-alive. During normal operation, they are powered by the
normal internal VDD of the part.
The 4-Kbyte DECRAM in the BBC module power its arrays via the VDDSRAM3 pin during keep-alive and
are supplied by VDD during normal operation.
4 MPC535 Memory Map
The inte rnal memory map i s or ganized as a single 4-Mbyte bloc k. This is shown i n Figure 3. This blo ck can
be moved to one of eight different locations. The internal memory space is divided into the following
sections:
• Flash memory (1 Mbyte) — U-bus memory
• Static RAM memory (36 Kbytes CALRAM) — L-bus memory
• Control registers and IMB3 modules (64 Kbytes), partitioned as
— USIU and fla sh co ntrol registers
— UIMB interface and IMB3 modules
— CALRAM and READI control registers (L-bus control register space)
The internal memory block can reside in one of eight possible 4-Mbyte memory spaces. These eight
locations are the first eight 4-Mbyte memory blocks starting with address 0x0000 0000, as shown in
Figure 2. There is a user programmable register in the USIU to configure the internal memory map to one
of the eight possible locations. Programmability of internal memory map location allows multiple chip
system.
The IMB3 address space block in Figure 3 shows memory allocation for IMB3 modules. It does not show
the actual memory space required for individual modules. All modules are mapped to the low address,
numerically, of the memory allocated for that module in the IMB3 address space.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
10 MPC535/MPC536 Product Brief MOTOROLA
Additional MPC535 Differences
Figure 2. Memory Map
0x0000 0000
0xFFFF FFFF
0x0100 0000
0x00FF FFFF
0x01FF FFFF
0x00C0 0000
0x00BF FFFF
0x0080 0000
0x00 7F FFFF
0x0040 0000
0x00 3F FFFF
0x01C0 0000
0x01BF FFFF
0x0140 0000
0x01 3F FFFF
0x0180 0000
0x01 7F FFFF
Internal 4-Mbyte Memory Block
(Re s ides in one of eight locations)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MOTOROLA MPC535/MPC536 Product Brief 11
Additional MPC535 Differences
Figure 3. Internal Memory Block
CALRAM/
Readi Control
256 bytes
0x38 00FF
0x38 0100 Reserved (L-bu s Control)
~32 Kbytes
4-Kbyte Overlay Section
0x30 7FFF
0x2F FFFF
0x30 0000
0x3F 6FFF
0x3F 7000
0x08 0000
0x3F 7FFF
0x3F 8000
0x00 0000
USIU & Flash Control
16 Kbytes
UIMB I/F & IMB
Modules
32 Kbytes
0x07 FFFF
0x10 0000
CALRAM_A (32 Kbyte)
Reserved for Flash
(2,016 Kbytes )
0x2F BFFF
0x30 8000
0x37 FFFF
Reserved for IMB
480 Kbyt es
Reserved (L-bus Mem)
444 Kbytes
0x38 4000
UC3F_B Flash
512 Kbytes
0x38 0000
0x38 3FFF
0x0F FFFF
UC3F_A Flash
512 Kbytes
0x2F C000
CALRAM_B (4 Kbyte)
0x3F FFFF
All 4-Kbytes can be
0x2F 7FFF
Ox2F 8000
Ove rlay Se ction
0x30 0000
0x30 7FFF
QSMCM_A (1 Kbytes)
MIOS14 (4 Kbyte s)
Reserved* (1 Kbytes)
TOUCAN_B (1 Kbytes)
UIMB Control Registers
(128 bytes)
Reserved* (2 Kbytes)
QADC64_A (1 Kbytes)
Reserved* (1 Kbytes)
Reserved (2 Kbytes)
USIU Control Registers
UC3F_A Control
UC3F_B Contr ol
0x2F C000
0x2F C87F
Reserved* (1 Kbytes)
0x30 7900
0x30 7000
0x30 6000
0x30 5800
0x30 5400
0x30 4C00
0x30 4800
0x30 4400
0x30 4000
0x30 3800
0x30 2000
0x30 7400
Reserved* (10 Kbytes) 0x30 1000
Reserved (1 Kbytes)
Reserved (896 bytes)
Reserved* (1 Kbytes) 0x30 5C00
0x30 7800
0x2F C800
0x2F C840
0x30 7F80
Reserved* (1 Kbytes)
Reserved (3952 bytes)
0x30 0080
0x30 0090
0x30 5000
DECRAM
0x2F 8FFF
0x2F 9000 4 Kbytes
0x2F 9FFF Reserved
BBC Control Regis ter s
0x2 F A000 8 Kbytes
(64 bytes)
(64 bytes)
Reserved* (144 bytes)
Note: Reserved, do not write to this space.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
12 MPC535/MPC536 Product Brief MOTOROLA
Additional MPC535 Differences
5 MPC535 Pinout Diagram
Figure 4 shows the pinout for the MPC535.
Figure 4. MPC535 Pinout Diagram
VSS
VSS
VSS
VSS
VSS
1 2 3 4 5 6 7 8 91011121314151617181920212223242526
AVDD VSS VRH VRL AN48_A_ AN53_A_
MA1_ VDDA VSSA QVDDL VSS A
BVSS VDD AN44_
_A_PQB0 ALTREF AN49_A_ AN52_A_ AN56_A_ AN58_A_ QVDDL ETRIG2 VSS VSS VDD B
CVDDRTC VSS VDD AN45_
_A_PQB1
AN46_
PQB2 AN50_A_ AN54_A_ AN57_A_ QVDDL ETRIG1 B_CNRX0 VSS VDD C
DEXTAL32 VDDSRAM2 VSS VDD VDDH AN82 AN47_
PQB3 AN51_A_ AN55_A_ AN59_A_ QVDDL VDDH NVDDL VSS VDD D
EXTAL32 B_CNTX0 VDDSRAM1 VSS VDD MPWM17 E
FVSSRTC NVDDL MPWM5_ MPWM18 MDA11 MDA13 F
GVDDSRAM3 MDA12 MDA27 MDA28 MDA29 G
HMDA30 MDA31 MPWM0 MPWM1 H
JMPWM3 MPWM2 MPWM16 MPWM20_
MPIO J
KMDA15 MDA14 MPWM21_
MPIO MPIO K
LMDI_0 TCK_ MDI_1 MCKI VSS VSS VSS VSS VSS VSS MPIO MPIO MPWM19 VF0_ L
MTDI_DSDI EVTI_B RSTI_B MSEI_B VSS VSS VSS VSS VSS VSS VF1_ VF2_ MPWM4_
MPIO VFLS0_ M
NTMS MDO_4_ MDO_6_ MDO_5_ VSS VSS VSS VSS VSS VSS VDDH VFLS1_
MPIO N
PMDO_7_ JCOMP MCKO MDO_0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS P
RMDO_1 TDO_ MDO_2 IWP1_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS R
TMDO_3 MSEO IWP0_ SGPIOC6_ VSS VSS VSS VSS VSS VSS A_TXD1_ A_MISO_
QGPIO4 VSS A_SCK_
(C3F_CLK) T
UADDR_ ADDR_ ADDR_ NVDDL A_PCS2_
QGPIO2
A_RXD1_ A_MOSI_
QGPIO5
A_PCS3_
QGPIO3 U
VADDR_ ADDR_ ADDR_ ADDR_ A_PCS0_SS
_B_QGPIO0 A_TXD2_ A_RXD2_
(C3F_SUP2) VSS V
WADDR_ ADDR_ ADDR_ ADDR_ NVDDL VFLASH A_PCS1_
QGPIO1 PULLSEL W
YADDR_ ADDR_ ADDR_ ADDR_ VDDF EXTCLK NC KAPWR Y
AA ADDR_ ADDR_ ADDR_ ADDR_ PORESET_B VSS VSSF XTAL AA
AB ADDR_ ADDR_ ADDR_ QVDDL HRESET IRQ6_B_
MODCK2 RSTCONF_
B_TEXP EXTAL AB
AC ADDR_ NC QVDDL VSS VDD VDDH DATA_
SGPIOD29
DATA_
SGPIOD27 NVDDL DATA_
SGPIOD24
DATA_ DATA_
SGPIOD20 NVDDL SGPIOC7_ NVDDL WE_B_ NVDDL CS3_B BI_B_ VDDH VDD VSS QVDDL SRESET IRQ7_B_
MODCK3 VSSSYN AC
AD ADDR_ QVDDL VSS VDD NC DATA_ DATA_ DATA_ DATA_
SGPIOD26 DATA_
SGPIOD25 DATA_ DATA_
SGPIOD21 DATA_
SGPIOD19
IRQ4_
_SGPIOC4 TEA_B IRQ2_B_
SGPIOC2 WE_B_ CS1_B TSIZ0 B0EPEE CLKOUT VDD VSS QVDDL IRQ5_B_
SGPIOC5_ XFC AD
AE QVDDL VSS VDD DATA_ DATA_ DATA_ DATA_ DATA_ DATA_
SGPIOD11 DATA_ DATA_ DATA_
SGPIOD17
IRQ3_B_KR
_B_RETRY_B
_SGPIOC3
BB_B_ RD_WR OE_B WE_B_ CS0_B BURST TS_B BDIP_B NC VDD VSS QVDDL VDDSYN AE
AF VSS VDD DATA_ DATA_ DATA_ DATA_ DATA_ DATA_
SGPIOD10 DATA_
SGPIOD12 DATA_
SGPIOD14 DATA_
SGPIOD16 DATA_
SGPIOD18
IRQ1_B_
SGPIOC1
BG_B_ BR_B_ IRQ0_B_
SGPIOC0 WE_B_ CS2_B TSIZ1 TA_B EPEE ENGCLK_ NC VDD VSS QVDDL AF
1 2 3 4 5 6 7 8 91011121314151617181920212223242526
_TRST_B
NOTE: This is a top down view of the balls.
SGPIOA16
SGPIOA18
SGPIOA20
SGPIOA17
SGPIOA19
SGPIOA21
SGPIOA23
SGPIOA25
SGPIOA27
SGPIOA22
SGPIOA24
SGPIOA26
SGPIOA28
SGPIOA29
MPIO32B7
SGPIOA8
VFLS0 FRZ_
VFLS1
MPIO32B8 MPIO32B9MPIO32B10
MPIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS
VSSVSS
VSS
VSS
VSS
VSS
VSS
VSSVSS
PQA7
PQA3
PQA5
PQA6PQA4
MA2_
PQB6
PQB7
MA0_
PQB4
PQB5
VSSVSSVSS VSS
VSSVSSVSS VSS
VSSVSSVSS VSS
VSSVSS VSS
VSS VSS
VSSVSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VSS
VSS VSS VSS VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS
MPIO
MPIO
MPIO
MPIO
VSS VSS
QGPO1 QGPIO6
(C3F_SUP1)
QPI1 (C3F_IOUT)
QPI2
QGPO2
MODCK1
BUCLK
STS_B
VF1_IWP2
RSV_B_
SGPIOD8SGPIOD6SGPIOD4
SGPIOD3 SGPIOD5 SGPIOD7 SGPIOD9
B_LWP0
IRQOUT_
IWP3
SGPIOD30SGPIOD31 SGPIOD28
SGPIOD1
SGPIOD2SGPIOD0
SGPIOA31
SGPIOD23
SGPIOD13 SGPIOD15
SGPIOA15 SGPIOA30
SGPIOA14SGPIOA13
SGPIOA11SGPIOA12
SGPIOA9 SGPIOA10
32B13
32B14 32B15
32B2 32B5 32B3
32B0
32B1
32B4
32B11
32B12
_B
_B
AT1
AT2
AT0
AT3
B_AT2
LWP1
VF0_
VF2_
PTR_B
DSDO
_B
DSCK
ANW
ANX
PQA1
PQA0
ANY_A_
ANZ_A_
PQA2
32B6
SGPIOD22
_B
CR_B_
_B
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MOTOROLA MPC535/MPC536 Product Brief 13
Additional MPC535 Differences
THIS PAGE INTENTIONALLY LEFT BLANK
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
14 MPC535/MPC536 Product Brief MOTOROLA
Additional MPC535 Differences
THIS PAGE INTENTIONALLY LEFT BLANK
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MOTOROLA MPC535/MPC536 Product Brief 15
Additional MPC535 Differences
THIS PAGE INTENTIONALLY LEFT BLANK
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MPC535PB/D
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-303-675-2140 or 1-800-441-2447
JAPAN:
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu Minato-ku
Tokyo 106-8573 Japan
81-3-3440-3569
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre, 2 Dai King Street
Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
TECHNICAL INFORMATION CENTER:
1-800-521-6274
HOME PAGE:
http://www.motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use
Motorola products. There are no express or implied copyright licenses granted hereunder to design
or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein.
Motorola makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does Motorola assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be provided in
Motorol a data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “T ypicals” must be validated
for each customer application by customer’s technical experts. Motorola does not convey any
license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the
body , or other applications intended to support or sustain life, or for any other application in which
the failure of the Motorola product could create a situation where personal injury or death may
occu r. Shou ld Buy e r pu r cha s e or us e Mot o ro l a pr od uc ts fo r any s uc h uni nt e nd ed or un a ut h or iz ed
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and T rademark Office.
digital dna is a trademark of Motorola, Inc. The described product contains a PowerPC processor
core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product
or service names are the property of their respective owners. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2003
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
