ISL5586CIM - Intersil Corporation

4-1

File Number 4924.1

ISL5586

Low Power Ringing SLIC for Home

Gateways

The ISL5586 is a very low

power Ringing Subscriber

Interface circuit designed for

use with the Broadcom*

BCM3352 Cable Modem

Chip, with on-board voiceband codecs, or other 3.3V

voiceband codec devices.

The ISL5586 provides on board ringing signal generation up

to 95V peak supporting sinusoidal or trapezoidal

waveshapes with DC offset. Loop start and ground start

trunks are supported, and an open circuit DC voltage of less

than56V is maintainedon the subscriber loop in the on-hook

condition, in compliance with MTU operation and the safety

requirements of UL-1950.

Together with the Broadcom BCM3352, the ISL5586

provides resistive and complex two wire impedance

matching and transhybrid balancing. Also supported are on-

hook transmission of caller id signals, soft and hard polarity

reversal and 12/16kHz subscriber pulse metering systems

used in Europe and Asia, thereby allowing a low cost, low

risk, global product design to be achieved.

Related Literature

• Evaluation Board for the ISL5586 family AN9918

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

Features

• Interfaces to Broadcom 3352 cable modem device

• Very low on-hook power consumption

- 64mW @ Vbh = 75V

• User Programmable constant current to the subscriber

loop

• On Chip ring generation

- Balanced to 95 Vpk

• Sinewave, Trapezoid, DC offset

• Programmable loop start and ring trip detectors

• Loop start, Ground Start, Polarity Reversal (soft/hard)

• On-Hook transmission and pulse metering support

• Integrated battery switch

• Open circuit line voltage clamp

• Compatible with 3.3V devices

• TR-57 compliant Longitudinal balance

• 28 PLCC packaging

• Latch-up free Bipolar design

• Thermal protection

Applications

• Cable Modems

• Voice Over DSL (VoDSL)

• Broadband Wireless Access

• Voice Over Internet Protocol (VoIP)

• ISDN Terminal Adapters (TA)

• Small Office Home Office PBX

• Wireless Local Loop

Block Diagram

*Broadcom is a registered trademark of Broadcom Corp.

VRSP

VRXM

-IN

VFB

ILIM

RTD DET

RINGING

PORT

4-WIRE

PORT

CONTROL

LOGIC

BATTERY

SWITCH

TRANSMIT

SENSING

DETECTOR

LOGIC

CONTROL

2-WIRE

PORT

INTERNAL

LOOP BACK

POL CDCM VBH

VBL

BSEL

TRANSIENT

CURRENT

LIMIT

TIP

RING

VRSM

VRXP

VTXP

VTXM

VZO

CDCP

Data Sheet June 2001

RSLIC18™ is a trademark of Intersil Corporation.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 |Intersil and Design is a trademark of Intersil Americas Inc.

4-2

Pinout

ISL5586 (PLCC)

TOP VIEW

Ordering Information

PART NUMBER

HIGH BATTERY (VBH)LONGITUDINAL

BALANCE TEMP.

RANGE oC PACKAGE PACKAGE NO.100V 85V 75V 58dB 53dB

ISL5586FCM ••

0to75 28LdPLCC N28.45

ISL5586BIM •• -40to85 28LdPLCC N28.45

ISL5586CIM ••

-40to85 28LdPLCC N28.45

ISL5586DIM ••

-40to85 28LdPLCC N28.45

Device Operating Modes

MODE F2 F1 F0 DET DESCRIPTION

Low Power Standby (LPS) 0 0 0 SHD MTU compliant on hook operating mode.

Forward Active (FA) 0 0 1 SHD MTU compliant and OHT capable on hook mode, off hook loop feed mode.

Unused 0 1 0 n/a Reserved for internal purposes.

Reverse Active (RA) 0 1 1 SHD Signalling mode which reverses direction of loop current, otherwise like Forward Active.

Ringing 1 0 0 RTD Signalling mode used to generate high voltage balanced ringing signal.

Forward Loop Back (FLB) 1 0 1 SHD Internal loop back mode which connects internal load across Tip and Ring terminals.

Tip Open/Ground Start (TO) 1 1 0 SHD Signalling mode sets Tip to high impedance state, Ring output still active.

Power Denial (PD) 1 1 1 n/a Loop disconnect mode which forces both Tip and Ring to high impedance.

RING

ILIM

RTD

CDCM

-IN

VZO

VRXM

VRXP

POL

VCC

CDCP

VFB

BGND

TIP

VRSM

VTXP

VTXM

AGND

BSEL

VBL

VBH

DET

VRSP

12 13 14 15 16 17 18

123

ISL5586

4-3

Absolute Maximum Ratings TA=25

oCThermal Information

Maximum Supply Voltages

VCC ..................................... -0.5Vto+7V

VCC -V

BAT ......................................110V

ESD(HumanBodyModel).......................... 500V

Maximum Tip/Ring Negative Voltage Pulse (Note 7). . . . . .VBH-15V

MaximumTip/RingPositiveVoltagePulse(Note7)..........+8V

Operating Conditions

Temperature Range

Industrial.................................-40

oCto85

Positive Power Supply (VCC)............................+5V

Negative Power Supply (VBH,V

BL).............. -100Vto-24V

Thermal Resistance (Typical, Note 1) θJA (oC/W)

PLCCPackage............................. 53

MaximumJunctionTemperaturePlastic.................150

MaximumStorageTemperatureRange.......... -65

oCto150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(PLCC - Lead Tips Only)

Die Characteristics

SubstratePotential ................................. -V

Process...................................... Bipolar-DI

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications Unless Otherwise Specified, TA=-40

oCto85

oC, VBL = -24V, VBH = -100V, VCC =+5V,

AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600Ω,

2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection

resistors = 0Ω. These parameters apply generically to each product offering.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

RINGING PARAMETERS

VRSP Input Impedance (Note 2) 35 - - MΩ

VRSM input impedance (Note 2) 10 - - MΩ

Differential Ringing Gain (Note 3) VRS to 2-Wire, RLOAD =5 REN - 99.5 - V/V

Ringing voltage Total Distortion RL=1.3kΩ,V

T-R =|V

BH|-5 - 0.8 5 %

4-Wire to 2-Wire Ringing Off Isolation Forward Active Mode, Referenced to VRS Input. - 100 - dB

2-Wire to 4-Wire Transmit Isolation Ringing Mode Referenced to the Differential

Ringing Amplitude. -100- dB

Centering Voltage Accuracy Tip, Referenced to VBH/2 + 0.5V -3.0 0.2 3.0 V

Ring, Referenced to VBH/2 + 0.5V -3.0 0.2 3.0 V

AC TRANSMISSION PARAMETERS

Receive Input Impedance, VRXP (Note 2) 379 541 - kΩ

Receive input Impedance, VRXM (Note 2) 100 142 - kΩ

Transmit Output Impedance (Note 2) DC - 0.01 - Ω

Transmit Output Drive Capability (Note 2) Current 0.30 1.0 - mA

Capacitance to Ground - 1.0 100 pF

4-Wire Port Overload Level THD = 1% 3.1 3.5 - VPEAK

2-Wire Port Overload Level THD = 1% 3.1 3.5 - VPEAK

2-Wire Return Loss (Note 2) 200Hz ≤f≤1kHz - 35 - dB

1kHz ≤f≤3.4kHz - 23 - dB

Longitudinal Current Capability per Wire (Note 2) False Detect 20 - - mARMS

False Detect in Low Power Standby 10 - - mARMS

2-Wire Longitudinal Balance (ON-Hook and OFF-Hook)

(Notes 4, 5) 200Hz, 500Hz, 1000Hz 58 61 - dB

3000Hz 53 61 - dB

4-Wire Longitudinal Balance (ON-Hook and OFF-Hook)

(Notes 4, 5) 200Hz, 500Hz, 1000Hz 58 64 - dB

3000Hz 53 62 - dB

4-Wire to 2-Wire Insertion Loss 0dBmo at 1kHz 2.72 2.92 3.12 dB

2-Wire to 4-Wire Insertion Loss 0dBmo at 1kHz -0.2 0 0.2 dB

4-Wire to 4-Wire Insertion Loss 0dBmo at 1kHz 2.72 2.92 3.12 dB

Frequency Response, On Hook, 2-Wire to 4-Wire, 4-Wire

to 2-Wire, 4-Wire to 4-Wire Referenced to 0dBmo at 1004Hz,

400Hz ≤f≤ 2800Hz -0.15 0.03 0.15 dB

Frequency Response, Off Hook

2-Wire to 4-Wire, 4-Wire to 2-Wire, 4-Wire to 4-Wire Referenced to 0dBmo at 1004Hz, f = 400Hz,

2800Hz -0.15 0.03 .15 dB

ISL5586

4-4

Amplitude Tracking, Off Hook, 2-Wire to 4-Wire, 4-Wire to

2-Wire, 4-Wire to 4-Wire +3dBmo to -37dBmo, f = 1004Hz,

Referenced to 0dBmo -0.02- dB

-37 to -50dBmo - 0.05 - dB

-50 to -55dBmo - 0.10 - dB

Amplitude Tracking, ON-Hook 0dBmo to -37dBmo, f = 1004Hz,

Referenced to 0dBmo -0.01- dB

Signal to Distortion, 2-Wire to 4-Wire, 4-Wire to 2-Wire,

4-Wire to 4-Wire, ON-Hook and OFF-Hook Input level 0dBmo to -30dBmo 33 45 - dB

Input Level -30 to -40dBmo 27 40 - dB

Input Level -40 to -45dBmo 22 29 - dB

Signal Frequency Distortion (0Hz to 12kHz) 0dBmo input, 0 Hz ≤f≤ 12kHz 28 45 - dB

Single Frequency Distortion (0Hz to 4kHz) 0dBmo Input, 1004Hz ≤f≤ 1024Hz 40 50 - dB

Intermodulation Distortion, 2-Wire to 4-Wire,

4-Wire to 2-Wire, 4-Wire to 4-Wire

(IEEE Standard 743-1984)

4-Tone Second-Order Intermodulation Products 43 50 - dB

4-Tone Third-order Intermodulation Products 44 62 - dB

Idle Channel Noise, 2-Wire (Note 5) C-Message, Forward Active, Low Battery Enabled - 10.0 13.0 dBrnc

Idle Channel Noise, 4-Wire (Note 5) C-Message, Forward Active, Low Battery Enabled - 10.0 13.0 dBrnc

DC PARAMETERS

OFF-Hook Loop Current Limit Programming Accuracy (1% External Resistor) -8.5 1.0 +8.5 %

Programming Range 15 - 45 mA

OFF-Hook Transient Current Limit Programming Accuracy -10 - +10 %

Programming Range 40 - 100 mA

Loop Current During Low Power Standby Forward Polarity Only (RL=600Ω)-24-mA

Open Circuit Voltage

(|Tip - Ring|)

ForwardandReverseActivemodes

VBL = -16V - 7.0 - VDC

VBL = -24V 13.5 14.5 16.5 VDC

VBH >-60V 43 48 - V

Open Circuit Voltage (|Tip-Ring|) LPS VBH >-60V 43 51 - V

Absolute Open Circuit Voltage (Relative to GND) VRG in FA, VTG in RA, VBH > -60V - -53 -56 VDC

Absolute Open Circuit Voltage VRG in LPS - -52 -56 VDC

TEST ACCESS FUNCTIONS

Loopback Max Battery --52V

LOOP DETECTORS AND SUPERVISORY FUNCTIONS

Switch Hook Programming Range 5-15mA

Switch Hook Programming Accuracy Assumes 1% External Programming Resistor -10 - +10 %

Dial Pulse Distortion -1.0- %

Ring Trip Comparator Threshold 2.3 2.60 2.9 V

Ring Trip Programming Current Accuracy -10 - +10 %

Thermal Shutdown Threshold IC Junction Temperature - 175 - oC

LOGIC INPUTS (F0, F1, F2, BSEL)

Input Low Voltage --0.8V

Input High Voltage 2.0 - - V

Input Low Current (F0, F1, F2) VIL =0.4V - 7.5 20 µA

Input Low Current (BSEL) VIL =0.4V - 1.0 - µA

Input High Current (F0, F1, F2, BSEL) VIH =2.4V - 0.01 - µA

LOGIC OUTPUT (DET)

Output Low Voltage IOL = 5mA - 0.15 0.4 V

Output High Voltage IOH =100µA 2.4 3.2 3.5 V

SUPPLY CURRENTS

Low Power Standby, BSEL = 2.0V, VBH = -75V to -100V ICC -3.25.0mA

IBH - 0.65 0.9 mA

Forward or Reverse,BSEL =.8V ICC -5.06.5mA

IBL -1.52.5mA

Electrical Specifications Unless Otherwise Specified, TA=-40

oCto85

oC, VBL = -24V, VBH = -100V, VCC =+5V,

AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600Ω,

2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection

resistors = 0Ω. These parameters apply generically to each product offering. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ISL5586

4-5

Forward Active, BSEL = 2.0V, VBH = -100V ICC -7.09.0mA

IBL -1.42.0mA

IBH -1.83.0mA

Forward Active, BSEL = 2.0V, VBH =-85V I

CC -6.68.5mA

IBL - 1.35 2.0 mA

IBH -1.602.75mA

Forward Active, BSEL = 2.0V, VBH =-75V I

CC -6.38.0mA

IBL - 1.25 2.0 mA

IBH - 1.45 2.5 mA

Ringing, BSEL = 2.0V, VBH = -100V ICC -7.410.0mA

IBL -1.52.0mA

IBH -2.23.0mA

Ringing, BSEL = 2.0V, VBH =-85V I

CC -6.809.25mA

IBL - 1.36 2.0 mA

IBH -2.13.0mA

Ringing, BSEL = 2.0V, VBH =-75V I

CC -6.48.5mA

IBL - 1.26 2.0 mA

IBH -2.03.0mA

Forward Loopback, BSEL = 0.8V, VBL =-24V I

CC - 10.3 13.5 mA

IBL - 23.0 32.0 mA

Tip Open, BSEL = 2.0V ICC -3.2- mA

IBL -0.1- mA

Power Denial, BSEL = 0.8V or 2.0V ICC -3.46.0mA

IBL -0.220.50mA

ON HOOK POWER DISSIPATION (Note 6)

Forward or Reverse VBL =-24V - 57 - mW

Low Power Standby VBH = -100V - 83 - mW

VBH =-85V - 70 - mW

VBH =-75V - 64 - mW

Ringing VBH = -100V - 294 - mW

VBH =-85V - 236 - mW

VBH =-75V - 206 - mW

OFF HOOK POWER DISSIPATION (Note 6)

Forward or Reverse VBL =-24V,I

LIM =25mA,R

L=300Ω-305- mW

POWER SUPPLY REJECTION RATIO

VCC to 2-Wire, BSEL = 0.8V f = 50kHz - 50 - dB

f = 300Hz ≤f≤ 3400Hz - 45 - dB

f=8kHz≤f≤ 16kHz - 28 - dB

VCC to 4-Wire, BSEL = 0.8V f = 50Hz - 70 - dB

f = 300Hz ≤f≤ 3400Hz - 55 - dB

f=8kHz≤f≤ 16kHz - 40 - dB

VBL to 2-Wire, BSEL = 0.8V f = 50Hz - 25 - dB

f = 300Hz ≤f≤ 3400Hz - 38 - dB

f=8kHz≤f≤ 16kHz - 28 - dB

VBL to 4-Wire, BSEL = 0.8V f = 50Hz - 27 - dB

f = 300Hz ≤f≤ 3400Hz - 36 - dB

f=8kHz≤f≤ 16kHz - 23 - dB

VBH to 2-Wire, BSEL = 2.0V f = 50Hz - 27 - dB

f = 300Hz ≤f≤ 3400Hz - 35 - dB

f=8kHz≤f≤ 16kHz - 23 - dB

Electrical Specifications Unless Otherwise Specified, TA=-40

oCto85

oC, VBL = -24V, VBH = -100V, VCC =+5V,

AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600Ω,

2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection

resistors = 0Ω. These parameters apply generically to each product offering. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ISL5586

4-6

Design Equations

Refer to Figure 14 for programming resistor connections.

Loop Supervision Thresholds

SWITCH HOOK DETECT

The desired switch hook detect threshold current (ISH)issetby

a single external resistor, RSH as follows

The loop current threshold programming range is from 5mA

to 15mA.

RING TRIP DETECT

The ring trip detect threshold (IRT) is set by a single external

resistor, RRT as follows.

IRT should be set between the peak ringing current and the

peak off hook current while still ringing. In addition, the ring

trip current must be set below the transient current limit

including tolerances. The ringing signal filter capacitor CRT,

in parallel with RRT sets the ring trip response time.

LOOP CURRENT LIMIT

The DC loop current limit (ILIM) is programmed by the

external resistor RIL as follows.

The loop current limit programming range is from 15mA to

45mA.

Impedance Matching

The AC source impedance of the SLIC is programmed with

the external impedance network ZSas described next. To

synthesize and match Resistive line terminations the

programming network is simply a resistor (RS) as shown in

Figure 14. For complex line terminations such as the one

illustrated in Figure 1, a complex programming network is

required.

RESISTIVE IMPEDANCE SYNTHESIS

The AC source resistance of the SLIC is synthesized with a

single external resistor RSas follows:

The synthesized resistance (Z0) is determined by the

characteristic line resistance and protection resistors as

shown in Equation 5.

COMPLEX IMPEDANCE SYNTHESIS

A complex network is used in place of RSwhen the termination

impedance of the line is complex as shown in Figure 1.

The component RShas a different design equation than the

RSused for resistive impedance synthesis. The design

equations for each component are provided below where

RP1 and RP2 are the protection resistors and RPis a

component of the programming network.

VBH to 4-Wire, BSEL = 2.0V f = 50Hz - 76 - dB

f = 300Hz ≤f≤ 3400Hz - 55 - dB

f=8kHz≤f≤ 16kHz - 42 - dB

NOTES:

2. TheseparametersarecontrolledviadesignandStatisticalProcessControlandarenotdirectlytested.Theseparametersarecharacterizedupon

initial design release and upon design changes which would affect these characteristics.

3. Input voltage = 0.636VRMS for VBH = -100V, 0.530VRMS for VBH = -85V and 0.460VRMS for -75V devices.

4. Tested per IEEE455-1985, with 368Ω resistors connected to the Tip and Ring terminals.

5. These parameters are tested 100% at room temperature, and are guaranteed but not tested across the full temperature range via statistical

characterization and design.

6. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current limits.

7. Characterized with 2 x 10us and 10 x 1000us first level lightning surge waveform (GR-1089-CORE).

Electrical Specifications Unless Otherwise Specified, TA=-40

oCto85

oC, VBL = -24V, VBH = -100V, VCC =+5V,

AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600Ω,

2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection

resistors = 0Ω. These parameters apply generically to each product offering. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

RSH 615 ISH

⁄=(EQ. 1)

RRT 1800 IRT

⁄=(EQ. 2)

RIL 1760

ILIM

-------------= (EQ. 3)

RSZ0400

----------





×133.3 Z0

()== (EQ. 4)

ZORLRP1RP2

+()–= (EQ. 5)

FIGURE 1. COMPLEX PROGRAMMING NETWORK

2-WIRE TERMINATION

IMPEDANCE (ZL)

PROGRAMMING

NETWORK (ZS)

RS133.3 R1 RP1

–RP2

–()×=(EQ. 6)

RP133.3 R2

×=(EQ. 7)

CPC2133.3⁄=(EQ. 8)

ISL5586

4-7

4-WIRE TO 2-WIRE GAIN

The4-wireto2-wiregain(G

42) is defined as the receive

gain. It is a function of the terminating impedance,

synthesized impedance and protection resistors. The gain is

defined from the Receive input terminals (VRXP,V

RXM)to

the terminating impedance (ZL) on the 2-wire side, and is

illustrated in Figure 12.

When the device source impedance and the protection

resistors equal the terminating impedance, the receive gain

equals 2.92dB and is inverted with respect to the input.

2-WIRE TO 4-WIRE GAIN

The2-wireto4-wiregain(G

24) is the gain from tip and ring to

the transmit differential output. The transmit gain is given by

Equation 11. Note that VTR is defined on the line side of the

protection resistors (reference Figure 13). With ZLset to 600

ohms, the protection resistors set to 50Ω/terminal and

Z0=Z

L-2RP the Transmit gain equals -0.833 (-1.59dB) and

is inverted with respect to the 2-wire input (VTR).

TRANSHYBRID GAIN

The transhybrid gain is defined as the 4-wire to 4-wire gain

(G44) and is given by Equation 12 (Reference Figure 14)).

Transient Current Limit

The drive current capability of the output amplifiers is

determined by an externally programmable output current

limit circuit which is separate from the DC loop current limit

function. The transient current limit is programmed with a

resistor to ground at the TL pin. The current limit circuit

worksin both the source and sink direction, with an internally

fixed offset to prevent the current limit functions from turning

on simultaneously. The current limit function is provided by

sensing line current and reducing the voltage drive to the

load when the externally set threshold is exceeded, hence

forcing a constant source or sink current.

SOURCE CURRENT PROGRAMMING

The source current is externally programmed as shown in

Equation 13.

For example, a source current limit setting of 50mA is

programmed with a 35.6kΩresistor connected from pin 16 of

the device to ground. This setting determines the maximum

amount of current which flows from Tip to Ring during an off

hook event until the DC loop current limit responds. In addition

this setting also determines the amount of current which will

flow from Tip or Ring when external battery faults occur.

SINK CURRENT PROGRAMMING

The sink current limit is internally offset 20% higher than the

externally programmed source current limit setting.

If the source current limit is set to 50mA, the sink current limit

will be 60mA. This setting will determine the amount of current

which flows into Tip or Ring when external ground faults occur.

FUNCTIONAL DESCRIPTION

Each amplifier is designed to limit source current and sink

current. The diagram below shows the functionality of the

circuit for the case of limiting the source current. A similar

diagram applies to the sink current limit with current polarity

changed accordingly.

During normal operation, the errorcurrent (IERR) is zero and

the output voltage is determined by the signal current (ISIG)

multiplied by the 200K feedback resistor. With the current

polarity as shown for ISIG, the output voltage moves positive

with respect to half battery. Assuming the amplifier output is

driving a load at a more negative potential, the amplifier

output will source current.

During excessive output source current flow, the scaled

output current (IO/K) exceeds the reference current (IREF)

forcinganerrorcurrent(I

ERR). With the polarity as shown

the error current subtracts from the signal current, which

reduces the amplifier output voltage. By reducing the output

voltage the source current to the load is decreased and the

output current is limited.

DETERMINING THE PROPER SETTING

Since this feature programs the maximum output current of

the device, the setting must be high enough to allow for

detection of ring trip or programmed off hook loop current,

whichever is greater.

ZOR1 RP1–RP2–()R2 C2+= (EQ. 9)

G42 2.8 ZL

ZO+2R

P+Z

------------------------------------------







–= (EQ. 10)

G24 2ZO

ZO+2R

P+Z

------------------------------------------







–= (EQ. 11)

G44 2.8 ZO

ZO2RPZL

---------------------------------------







–= (EQ. 12)

RTL 1780

ISRC

-------------=(EQ. 13)

ISNK 1.20 ISRC

×=(EQ. 14)

FIGURE 2. CURRENT LIMIT FUNCTIONAL DIAGRAM

TIP or RING

IREF =1.21/TL

IO/K

IERR

ISIG 20

200K

VB/2

ISL5586

4-8

To allow for proper ring trip operation, the transient current

limit setting should be set at least 25% higher than the peak

ring trip current setting. Setting the transient current 25%

higher should account for programming tolerances of both

the ring trip threshold and the transient current limit.

If loop current is larger than ring trip current (low REN

applications) then the transient current limit should be set at

least 35% higher than the loop current setting. The slightly

higher offset accounts for the slope of the loop current limit

function.

Attention to detail should be exercised when programming

the transient current limit setting. If ring trip detect does not

occur while ringing, then re-examine the transient current

limit and ring trip threshold settings.

Low Power Standby Mode

Overview

The low power standby mode (LPS, 000) should be used in

conjunction with the high battery during idle line conditions.

The SLIC is designed to operate from the high battery during

this mode so MTU compliance can be met. Most of the

internal circuitry is powered down, resulting in low power

dissipation. If MTU compliance is not required during idle line

conditions, the device may be operated from the low battery

which will decrease the standby power dissipation.

2-Wire Interface

In the LPS mode, the 2-wire interface is maintained with

internal switches, resistors, and voltage references. The Tip

and Ring amplifiers are turned off to conserve power. The

device will provide MTU compliance, loop current, and loop

supervision. Figure 2 represents the internal circuitry

providing the 2-wire interface when in this mode of operation.

MTU Compliance

Maintenance Termination Unit or MTU compliance places

DC voltage requirements on the 2-wire terminals during idle

line conditions. The minimum idle voltage for compliance is

42.75V. The high side of the MTU range is 56V. The voltage

is expressed as the difference between Tip and Ring.

The Tip voltage is held near ground through a 600Ωresistor

and switch. The Ring voltage is nominally limited to -49V by

the MTU reference. A switch and 600Ωresistor connect the

MTU reference to the Ring terminal. When the high battery

voltage exceeds the MTU reference of -49V, the Ring

terminal will be clamped by the internal reference.The same

Ring relationships apply when operating from the low

battery. For operating battery voltages (VBH) less than or

equal to the internal MTU reference, the Ring voltage will be

approximately 4.5 volts more positive than VBH.

Loop Current

In the LPS mode, the device is capable of providing DC

current to a load through a path of resistors and switches.

The current available for switch hook detect is a function of

the off hook loop resistance (RLOOP). This includes the off

hook phone resistance and copper loop resistance. The

current available during LPS is given by Equation 15.

Internal current limiting of the standby switches will limit the

maximum current to approximately 23mA. The longitudinal

current capability is guaranteed to be greater than or equal to

10mARMS per pin. When longitudinal currents exceed this

level, false off hook detection may occur. The reduction in

longitudinal current capability with respect to the Forward Active

mode is a result of turning off the Tip and Ring amplifiers.

On Hook Power Dissipation

The on hook power dissipation of the SLIC in the LPS mode

is determined by the operating voltages and quiescent

currents and is calculated below.

TABLE 1. DEVICE INTERFACES DURING LPS

INTERFACE ON OFF NOTES

Receive - x AC transmission, impedance

matching and ringing are

disabled during this mode.

Ringing - x

Transmit - x

2-Wire x - Amplifiers disabled.

Loop Detect x - Switch hook.

FIGURE 3. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM

TIP AMP

RING AMP

TIP

RING

MTU REF

GND

600Ω

ILOOP 1–49–()–()600 600 RLOOP

++()⁄=(EQ. 15)

PLPS VBH IBHQ

×VBL IBLQ

×VCC ICCQ

×++=(EQ. 16)

ISL5586

4-9

The quiescent current terms are specified in the electrical

tables for each operating mode. Load power dissipation is

not a factor since this is an on hook mode. Some

applications may specify a standby current. The standby

current may be a charging current required for modern

telephone electronics.

Standby Current Power Dissipation

Any standby line current, ISLC, introduces an additional power

dissipation term PSLC. Equation 17 illustrates the power

contribution is zero when the standby line current is zero.

If the battery voltage is less than -49V (the MTU clamp is

off), the standby line current power contribution reduces to

Equation 18.

Most applications do not specify charging current

requirements during standby. When specified, the typical

charging current may be as high as 5mA.

Forward Active Mode

Overview

The Forward Active mode (FA, 001) is the primary AC

transmission mode of the SLIC. On hook transmission, DC loop

feed and voice transmission are supported during this mode.

The device may be operated from either high or low battery for

on-hook transmission and from low battery for loop feed.

Loop supervision is provided by the switch hook detector at

the DET output. When DET goes low, the low battery should

be selected for DC loop feed and voice transmission.

On-Hook Transmission

The primary purpose of on hook transmission will be to

support caller ID and other advanced signalling features.

The transmission over load level while onhook is 3.1VPEAK.

When operating from the high battery, the DC voltages at Tip

and Ring are MTU compliant. The typical Tip voltage is -4V

and the Ring voltage is a function of the battery voltage for

battery voltages less than -60V as shown in Equation 19.

Feed Architecture

The SLIC design implements a voltage feed current sense

architecture. The voltage across Tip and Ring is controlled

by sensing the load current. Resistors are placed in series

with the Tip and Ring outputs to provide the current sensing

function. The diagram below illustrates the concept.

By monitoring the current at the amplifier outputs, a negative

feedback mechanism sets the output voltage for a defined

load. The amplifier closed loop gains are set by internal

resistor ratios (RA,R

B,R

C) providing all the performance

benefits of matched resistors. The internal sense resistor

RCS, is much smaller than the gain resistors and are

typically 20Ω. The feedback mechanism, KS, represents the

gain configuration providing negative feedback to the loop.

DC Loop Feed

The feedback mechanism for monitoring the DC portion of

the loop current is contained within theloop detector block. A

low pass filter is used in the feedback loop to block voice and

other signals from interfering with the loop current limit

function. The pole of the low pass filter is set by the external

4.7µF capacitor (CDC) and an internal 8KΩ resistor. The DC

feed characteristic of the SLIC will drive Tip and Ring

towards half battery to regulate the DC loop current. For light

loads, Tip will be near -4V and Ring will be near

VVBL + 4.5V. Most applications will operate the device from

low battery while off hook. The following diagram depicts the

DC feed characteristic.

The point on the y-axis labeled VTR(OC) is the open circuit

Tip to Ring voltage and is defined by the feed battery

voltage.

The curve of Figure 5 shows the loop current for a given set

of loop conditions. The loop conditions are determined by

the low battery voltage and the DC loop resistance. The DC

loop resistance is the sum of the protection resistance,

copper resistance (ohms/foot) and the telephone off hook

DC resistance.

PSLC ISLC VBH 49–1I

SLCx1200++()×=(EQ. 17)

PSLC ISLC VBH 1I

SLCx1200++()×=(EQ. 18)

VRING VBH 4.5V+= (EQ. 19)

FIGURE 4. VOLTAGE FEED CURRENT SENSE DIAGRAM

VIN

VOUT

RCS

RBRA

FIGURE 5. DC FEED CHARACTERISTIC

m=(∆VTR/∆IL)=11.1kΩ

ILOOP (mA) ILIM

VTR(OC)

VTR,DC(V)

VTR OC() VBL 9–= (EQ. 20)

ISL5586

4-10

The slope of the feed characteristic and the battery voltage

define the maximum loop current on the shortest possible

loop as the short circuit current ISC.

The term ILIM is the programmed current limit, 1760/RIL.The

line segment IArepresents the constantcurrent region of the

loop current limit function.

The maximum loop resistance for a programmed loop

current is defined as RKNEE.

When RKNEE is exceeded, the device will transition from

constant current feed to constant voltage, resistive feed. The

line segment IBrepresents the resistive feed portion of the

load characteristic.

Power Dissipation

The power dissipated by the SLIC in the Forward Active

mode while on hook is strictly a function of the quiescent

currents for each supply.

Off hook power dissipation is increased above the quiescent

power dissipation by the DC load. If the loop length is less

than or equal to RKNEE, the device is providing constant

current (IA), and the power dissipation is calculated using

Equation 26.

If the loop length is greater than RKNEE, the device is

operating in the constant voltage, resistive feed region. The

power dissipated in this region is calculated using Equation 27.

Since the current relationships are different for constant

current versus constant voltage, the region of device

operation is critical to valid power dissipation calculations.

ReverseActiveMode

Overview

The reverse active mode (RA, 011) provides the same

functionality as the forward active mode. On hook transmission,

DC loop feed, and voice transmission are supported. Loop

supervision is provided by the switch hook detector. The device

may be operated from either high or low battery.

When in the Reverse Active mode the Tip and Ring DC

voltage characteristics exchange roles. That is, Ring is

typically 4V below ground and Tip is typically 4.5V more

positive than battery.

Silent Polarity Reversal

Changing from forward active to reverse active or vice versa

is referred to as polarity reversal. Many applications require

control of the polarity reversal transition time. Requirements

range from minimizing cross talk to protocol signalling.

The SLIC uses an external low voltage capacitor, CPOL,to

set the reversal time. The capacitor is isolated from the AC

loop so that loop stability is not influenced by its selection.

Once CPOL is set, the reversal time will remain nearly

constant over various load conditions.

The internal circuitry used to set the polarity reversal time is

shown in Figure 7. During Forward Active the switch is open

and the current from source I1 charges the external timing

capacitor CPOL. The internal resistor provides a clamping

function for the voltage at the POL node. When the Reverse

Active mode is initiated the switch closes and the difference

current (I2-I1) discharges the timing capacitor. The voltage at

the POL node drives one side of a transistor differential pair

which forces the Forward or Reverse condition on the Tip and

Ring amplifiers. The forward/reverse transition time is given by

Equation 28, where ∆time is the required reversal time.

Polarized capacitors may be used for CPOL. The low voltage

at the POL pin and minimal voltage excursion in the order of

±0.75V, are well suited for polarized capacitors.

FIGURE 6. ILOOP VERSUS RLOOP LOAD CHARACTERISTIC

RLOOP (Ω)RKNEE

ILIM

ILOOP (mA)

ISC IA

2RP

ISC ILIM VTR OC()

2RPILIM

–

1.1e4

------------------------------------------------------+= (EQ. 21)

IAILIM VTR OC()

RLOOPILIM

–

1.1e4

--------------------------------------------------------------+= (EQ. 22)

RKNEE VTR OC()

ILIM

------------------------=(EQ. 23)

IBVTR OC()

RLOOP

------------------------=(EQ. 24)

PFAQ VBH I×BHQ VBL IBLQ

×VCC ICCQ

×++=(EQ. 25)

PFA IA() PFA Q() VBLxIA

()RLOOPxI2A

()–+= (EQ. 26)

PFA IB() PFA Q() VBLxIB

()RLOOPxI2B

()–+= (EQ. 27)

CPOL ∆time

75000

----------------=(EQ. 28)

ISL5586

4-11

Power Dissipation

The powerdissipation equations for forward active operation

also apply to the reverse active mode.

Ringing

Overview

The Ringing mode (RNG, 100) provides linear amplification

to support a variety of ringing waveforms. A programmable

ring trip function provides loop supervision and auto

disconnect upon ring trip. The device is designed to operate

from the high battery during this mode.

Architecture

The SLIC provides linear amplification to the differential

signal applied to the ringing inputs (VRSP,V

RSM). The

differential ringing gain of the device is 100V/V. The circuit

model for the ringing path is shown in Figure 8.

The voltage gain from the differential ringing input to the Tip

output is 50V/V. The resistor ratios provide a gain of 10 and

the current mirror provides again of 5. The voltage gain from

the differential input to the Ring output is -50V/V. The

equations for the Tip and Ring outputs during ringing are

provided below.

When the differential input signal is zero, the Tip and Ring

amplifier outputs are centered at half battery. The device

provides auto centering for easy implementation of

sinusoidal ringing waveforms. Both AC and DC control of the

Tip and Ring outputs is available during ringing. This feature

allows for DC offsets as part of the ringing waveform.

Ringing Input Terminals

The differential terminals feature high input impedance

which allows the use of low value capacitors for AC coupling

the ring signal if necessary. The Ringing input is enabled

only during the ringing mode, therefore a free running

oscillator may be connected at all times.

When operating from a battery of -100V, each amplifier, Tip

and Ring, will swing a maximum of 95VP-P.Hence,the

maximum differential signal swing between VRSP and VRSM

to achieve full scale ringing is approximately 1.9VP-P.

Logic Control

Ringing patterns consist of silent and ringing intervals. The

ringing to silent pattern is called the ringing cadence. During

the silent portion of ringing, the device can be programmed

to any other operating mode. The most likely candidates are

low power standby or forward active. Depending on system

requirements, the low or high battery may be selected.

Loop supervision is provided with the ring tripdetector.The ring

trip detector sensesthe change inloop current when the phone

is taken off hook. The loop detector full-wave rectifies the

ringing current, which is then filtered with external components

RRT and CRT. The resistor RRT sets the trip threshold and the

capacitor CRT sets the trip response time. Most applications will

require a trip response time less than 150ms.

Three very distinct actions occur when the device detects a

ring trip. First, the DET output is latched low. The latching

mechanism eliminates the need for software filtering of the

detector output. The latch is cleared when the operating

mode is changed externally. Second, the Ringing inputs are

disabled, removing the ring signal from the line. Third, the

device is internally forced to the forward active mode.

Power Dissipation

The power dissipation during ringing is dictated mostly by the

load driving requirements and the ringing waveform. The keyto

valid power calculations is the correct definition of average and

RMS currents. The average current defines the high battery

supply current. The RMS current defines the load current.

The cadence provides a time averaging reduction in the

peak power. The total power dissipation consists of ringing

power, Pr, and the silent interval power, Ps.

FIGURE 7. REVERSAL TIMING CONTROL

CPOL

POL

75kΩ

FIGURE 8. LINEAR RINGING MODEL

TIP

RING

R/8

5:1

20 +

-VBH

VRSP VRSM

1.25R

VTVBH

----------- 50 VDIF

×()+= (EQ. 29)

VRVBH

----------- 50 VDIF

×()–= (EQ. 30)

PRNG Prtr

trts

--------------×Psts

trts

--------------×+= (EQ. 31)

ISL5586

4-12

The terms tRand tSrepresent the cadence. The ringing

interval is tRand the silent interval is tS. A typical cadence

ratio tR:tSis 1:2.

The quiescent power of the device in the Ringing mode is

defined in Equation 32.

The total power during the ringing interval is the sum of the

quiescent power and loading power:

For sinusoidal waveforms, the average current, IAVG,is

defined in Equation 34.

The silent interval power dissipation will be determined by

the quiescent power of the selected operating mode.

ForwardLoopBackMode

Overview

The Forward Loop Back mode (FLB, 101) provides test

capability for the SLIC. An internal signal path is enabled

allowing forboth DC and AC verification bythe connection of

an internal 600 ohm resistor across Tip and Ring. This

internal terminating resistor has a tolerance of ±10% at room

temperature. The device is intended to operate from only the

low battery during this mode.

Architecture

When the forward loop back mode is initiated internal

switches connect a 600Ωload across the outputs of the Tip

and Ring amplifiers as shown below.

DC Verification

When the internal signal path is provided, DC current will

flow from Tip to Ring. The DC current will force DET low,

indicating the presence of loop current. In addition to

verifying device functionality, toggling the logic output

verifies the interface to the system controller.

AC Verification

The entire AC loop of the device is active during the forward

loop back mode. Therefore a 4-wire to 4-wire level test

capabilityis provided. Depending on the transhybrid balance

implementation, test coverage is provided by a one or two

step process.

System architectures which cannot disable the transhybrid

function would require a two step process. The first step

would be to send a test tone to the device while on hook and

not in forward loop back mode. The return signal amplitude

would be the test signal amplitude times the gain of the

transhybrid amplifier. Since the device would not be

terminated in the on hook mode, cancellation would not

occur. The second step would be to program the device to

FLB mode and resend the test tone. The return signal would

be much lower in amplitude than the first step, indicating the

device was active and the internal termination attenuated the

return signal.

System architectures which can disable the transhybrid

function would achieve test coverage with a signal step.

Once the transhybrid function is disabled the SLIC can be

programmed to the FLB mode and the test tone can be sent.

The return signal level is determined by the 4-wire to 4-wire

gain of the SLIC times the amplitude of the signal sent.

Tip Open/Ground Start Mode

Overview

The Tip Open mode (TO, 110) is intended for compatibility

with PBX type interfaces. The device does not provide

transmission capability in this mode which is intended for idle

line conditions. Loop supervision is provided by the switch

hook detector and either high or low battery operation is

supported.

Functionality

During Tip Open operation, the Tip switch is disabled and

the Ring switch is enabled. The minimum Tip impedance is

30kΩ. The only active path through the device will be

through the Ring switch.

In keeping with the MTU characteristics of the device, Ring

will not exceed -56V when operating from the high battery.

Though MTU does not apply to Tip Open, safety

requirements are satisfied.

PrQ() VBH IBHQ

×VBL IBLQ

×VCC ICCQ

×++=(EQ. 32)

PrPrQ() VBH IAVG

×VRMS

ZREN RLOOP

------------------------------------------–+= (EQ. 33)

IAVG 2

---



 VRMS 2×

ZREN RLOOP

------------------------------------------=(EQ. 34)

FIGURE 9. FORWARD LOOP BACK INTERNAL TERMINATION

RING AMP

TIP AMP

RING

TIP

600Ω

ISL5586

4-13

Power Denial

Overview

The power denial mode (111) will shutdown the entire device

except for the logic interface. Loop supervision is not

provided. This mode may be used as a sleep mode or to

shut down the SLIC in the presence of fault conditions.

Switching between high and low battery will have no effect

during power denial.

Functionality

During power denial, both the Tip and Ring amplifiers are

disabled, presenting high impedances to the line. The

voltages at both outputs are near ground.

Thermal Shutdown

In the event the safe dietemperature is exceeded due to a fault

condition the device will automatically shut down. The thermal

shutdown threshold is approximately 170ºC.When the device

cools to a temperature below the thermal threshold it will power

back up automatically. If the fault persists the part will continue

to go inand out of thermal shutdown which can be observed as

an oscillation on Tip or Ring. Programming power denial will

shut down the device and stop the self cooling cycle.

Battery Switching

Overview

The integrated battery switch selects between high battery

and low battery operation. The battery switch is controlled with

the logic input BSEL. When BSEL is a logic high, the high

battery (VBH) is selected. A logic low will enable the low

battery (VBL). All operating modes of the SLIC will function

from high or low battery, but it is strongly recommended

Forward Loop Back be enabled only with the low battery.

Functionality

The logic control is independent of the operating mode

decode. Independent logic control provides the most

flexibility and will support all application configurations.

When changing device operating states, battery switching

should occur simultaneously with or prior to changing the

operating mode. In most cases, this will minimize overall

power dissipation and prevent glitches on the DET output.

The only external component required to support the battery

switch is a diode in series with the VBH supply lead. In the

event that high battery is removed, the diode allows the

device to transition to low battery operation.

Low Battery Operation

All off hook operating conditions should use the low battery

to minimize power dissipation. A typical low battery

operating voltage for the SLIC is -24V, however this may be

increased to support longer loop lengths or high loop

current requirements. Standby conditions may also operate

from the low battery if MTU compliance is not required,

further reducing standby power dissipation.

High Battery Operation

Other than ringing, the high battery should be used for

standby conditions which must provide MTU compliance.

During standby operation the power consumption is typically

85mW with -100V battery. If ringing requirements do not

require full 100V operation, then a lower battery will result in

lower standby power.

High Voltage Decoupling

The 100V rating of the SLIC dictates a capacitor of higher

voltage rating be usedfor decoupling.Suggested decoupling

values for all device pins are 0.1µF. If the protection scheme

shown in Figure 15 is implemented the VBH decoupling

capacitor should be increased to 0.47uF. This is done to

minimize the turn-on time of the battrax device during

negative surge transients. Standard surface mount ceramic

capacitors are rated at 100V. For applications driven by low

cost and small size, the decoupling scheme shown in Figure

10 could be implemented.

It is important to place an external diode between the VBH pin

and the decoupling capacitor. Connecting the decoupling

capacitor directly to the VBH pin will degrade the reliability of the

device. Refer to Figure 15 for the proper arrangement. This

applies to both single and stacked and decoupling schemes.

If VBL and VBH are tied together the battery switch function

is overridden. In this case the external diode is not needed

and the decoupling capacitor may be attached directly to

VBH pin.

VBH

VBL

0.22µ0.22µ

ISL5586

FIGURE 10. ALTERNATE DECOUPLING SCHEME

FIGURE 11. IMPEDANCE SYNTHESIS

TIP

RING

-IN

VFB

VZO

1:1

4R 3R

CFB

VSA

IL VTR

V2W

ISL5586

4-14

Impedance and Gain Derivations

The feedback mechanism for monitoring the AC portion of

the loop current consists of two amplifiers, the sense

amplifier (SA) and the transmit amplifier (TA). The AC

feedback signal is used for impedance synthesis. A detailed

model of the AC feed back loop is provided below

Impedance Programming Resistor Derivation

The gain of the transmit amplifier, set by RS, determines the

programmed resistance of the SLIC. For complex line

terminations RSis replaced with a complex network ZS

(Figure 1). The capacitor CFB blocks the DC component of

the loop current. Figure 11 illustrates the impedance

synthesis loop. Note that the ground symbols shown in

Figures 11 through 14 represent AC grounds, not

necessarily actual DC potentials.

The receiver block provides a single-ended to differential

conversion with a voltage gain of 2. The voltage at Tip and

Ring due to the feedback from VZO is shown in Equation 35.

The Feedback amplifier (TA) provides the programmable

gain required for impedance synthesis to the Receiver block.

The output voltage (VZO) is a function of the Sense Amplifier

output voltage and the gain of the feedback amplifier, which

canbesubstitutedforV

ZO.

The sense amplifier shown in Figure 11 is configured as a 4

input differential amplifier with a gain of 3/4. The output

voltage, VSA, is a function of the voltage across the Tip and

Ring sense resistors (20Ωeach) which can also be

expressed in terms of loop current.

Substituting Equation 37 into Equation 35 and rearranging

terms yields Z0, the SLIC’s synthesized 2-wire impedance.

Rearranging and solving for RS,Equation39showsthe

relationship between the impedance programming resistor

and the programmed impedance.

4-WIRE TO 2-WIRE GAIN

The 4-wire to 2-wire gain is defined as the gain from the

differential receive input to the 2-wire load ZL. The gain is a

function of the terminating impedance, synthesized

impedance and protection resistors and is illustrated in

Figure 12. The input current to the receiver block Irx4w

comes from the difference of the VRX input current and the

VZO feedback current. This current is fed to the Tip and Ring

amplifiers and yields the relationship shown in Equation 40.

The voltage VZO, is a function of the sense amplifier output

voltage VSA.

VSA can be expressed in terms of loop current as shown in

Equation 42.

Substituting Equation 42 into Equation 41 gives Equation 43.

The VZ0 term in Equation 40 can now be replaced by

Equation 43 yielding Equation 44.

A loop equation can be derived for the 2-wire side that

replaces VTR as shown in the equation below.

Expressing IL in terms of V2W/ZL, rearranging, and solving

for V2W yields the relationship between the 2-wire voltage

and the output of the Receive amplifier.

The differential voice input is configured for a gain of 1.4.

The relationship between VRX and the voice input is shown

in Equation 47. Substituting for VRX, the 4-2-Wire gain is

shown in Equation 48. Note that the differential voice input is

outside the impedance synthesis loop, so the gain of the

receive amplifier has no effect on the SLIC’s impedance.

When the combination of the device source impedance and

the protection resistors equal the terminating impedance, the

receive gain equals 2.92dB and is inverted with respect to

the 4-wire input.

2-WIRE TO 4-WIRE GAIN

The2-wireto4-wiregain(G

24) is defined as the gain from the

Tip and Ring terminals (VTR)totheV

TX differential output.

VTR 2–VZO

×=(EQ. 35)

VTR 2–VSA

×RS

8KΩ

------------





×=(EQ. 36)

VSA 220IL 34)⁄(×××–= (EQ. 37)

Z0VTR

----------- 420IL3

---××× Rs

8KΩ

------------×60 Rs

8KΩ

------------×== = (EQ. 38)

RS133.3 Z0

×=(EQ. 39)

VTR 2V

rx VZO

–()×–= (EQ. 40)

VZ0 VSA RS

8KΩ

------------×–= (EQ. 41)

VSA IL2203

---×××–= (EQ. 42)

VZ0 IL 2 20 3

---××× RS

8KΩ

------------×–= (EQ. 43)

VTR 2V

×–2IL 2 20 3

---×××





8KΩ

------------





×–= (EQ. 44)

V2W IL 2Rp

×+2Vrx

–IL 4 20 3

---××





8KΩ

------------





×–= (EQ. 45)

V2W 2Vrx ZL

ZLZ02RP

--------------------------------------







×–= (EQ. 46)

Vrx 1.4 VRXP VRXM

–()×1.4 VRX4W

×== (EQ. 47)

V2W

VRX4W

-------------------- 2.8 ZL

ZO+2R

P+Z

------------------------------------------







–= (EQ. 48)

ISL5586

4-15

Note that in Figure 13, VTR is referenced on the line side of the

protection resistors.

On the 2-wire side, solving for IL in terms of VIN gives

Equation 49. Equations 50 and 51 show the relationship of

VIN to the outputs of the Sense Amplifier (VSA)andthe

Feedback Amplifier (VZ0) respectively.

SimplifyingEquation51intermsofZ

0gives the following

equation.

The resulting differential output voltage VTX4W, is shown in

Equation 53.

Note that the gain from VZ0 to the differential output is outside

the impedance synthesis loop and will have no effect on the

SLIC’s programmed impedance.

Substituting Equation 53 into Equation 52 and rearranging

terms gives the gain from the 2-wire source (VIN)tothe

differential output of the Transmit Amplifier.

If the combination of the protection resistors and the

programmed impedance of the SLIC are equal to ZLthe

voltage VTR will be 1/2 VIN. The 2-wire to 4-wire gain is

defined by Equation 55.

4-WIRE TO 4-WIRE GAIN

The 4-Wire to 4-Wire gain is defined in Equation 56 and is

illustrated in Figure 14.The first term is identical to

Equation 48.

The second term is derived in a similar manner as the 2-wire

to 4-wire gain starting with Equation 57.

Moving around the loop from the 2-wire side to the 4-wire

output we solve for VSA and VZO.

The relationship between VZ0 and the 4-wire output is

shown in Equation 53. Substituting Equation 59 into

Equation 53 yields Equation 60,the second term in Equation

56.

FIGURE 12. SCHEMATIC FOR 4-WIRE TO 2-WIRE GAIN DERIVATION

Irx4w

TIP

RING

-IN

VZO

200K

1:1

4R 3R

CFB

VSA

ILVtr

VRXM

VRXP

VRX4W

1.4R

V2W

VFB

VRX

200K 200K

200K

Iz0

IL VIN

ZLZ+02RP

--------------------------------------







=(EQ. 49)

VSA VIN

ZLZ+02RP

--------------------------------------







–220×3

---





××=(EQ. 50)

VZ0 VIN

ZLZ+02RP

--------------------------------------







–220×3

---





×× RS

8KΩ

------------×=(EQ. 51)

VZ0 VIN

ZLZ+02RP

--------------------------------------







–Z0

------×=(EQ. 52)

VTX4W VTXP VTXM VZ0 V–(–Z0)2VZ0

==–= (EQ. 53)

VTX4W

VIN

--------------------Z0

ZLZ+02RP

--------------------------------------







–= (EQ. 54)

VTX4W

VTR

--------------------2Z0

ZLZ+02RP

--------------------------------------







–= (EQ. 55)

VTX4W

VRX4W

-------------------- V2W

VRX4W

-------------------- VTX4W

V2W

--------------------×=(EQ. 56)

V2W IL ZL

×=(EQ. 57)

VSA I–L220×3

---×× V2W

------------40 3

---××== (EQ. 58)

VZ0 V2W

------------ RS

8KΩ

------------





×40 3

---×× V2W

------------ Z0

------×== (EQ. 59)

VTX4W

V2W

--------------------Z0

------=(EQ. 60)

ISL5586

4-16

Equations 48 and 60 can be combined to re-write the 4-wire

to 4-wire gain equation. Simplifying the above yields the 4-wire to 4-wire gain.

VTX4W

VRX4W

-------------------- 2.8 ZL

ZO+2R

P+Z

------------------------------------------







------×–= (EQ. 61)

VTX4W

VRX4W

-------------------- 2.8 Z0

ZO+2R

P+Z

------------------------------------------







–= (EQ. 62)

FIGURE 13. SCHEMATIC FOR 2-WIRE TO 4-WIRE GAIN DERIVATION

-IN

VFB

VRX

VZO

200K

1:1

4R 3R

CFB

VSA +

VRXP

VRXM

VTXP

VTXM

RP1

RP2

VTR

VIN

VTX4W

200K

1.4R

TIP

RING

FIGURE 14. SCHEMATIC FOR 4-WIRE TO 4-WIRE GAIN DERIVATION

-IN

VFB

VRX

VZO

1:1

4R 3R

CFB

VSA

VRXP

VRXM

VTXP

VTXM

RP1

RP2

ZLIL

VTX4W

V2W

-VRX4W

200K

200K 1.4R

1.4R

ISL5586

4-17

Pin Descriptions

PLCC SYMBOL DESCRIPTION

1 TIP TIP Power Amplifier Output.

2 BGND Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.

Internally separate from AGND and SGND but should be connected to the same potential as AGND & SGND.

BL Low Battery Supply Connection.

BH High Battery Supply Connection.

5 BSEL Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery.

6 F2 TTL Mode Control Input - MSB.

7 F1 TTL Mode Control Input.

8 F0 TTL Mode Control Input - LSB.

9 DET Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating mode.

The detected output will either be switch hook or ring trip.

10 VRSP Non-Inverting Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.

11 VRSM Inverting Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.

12 VTXP Transmit Output Voltage - AC couples to CODEC.

13 VTXM Transmit Output Voltage - AC couples to CODEC.

14 AGND Analog Ground Reference. This pin should be externally connected to BGND.

15 POL An External Capacitor on this pin sets the polarity reversal time.

16 VRXP Non-Inverting Analog Receive Voltage - 4-wire analog audio input voltage.

17 VRXM Inverting Analog Receive Voltage - 4-wire analog audio input voltage.

18 VZO Connection Terminal for impedance matching programming resistor

19 -IN Connection Terminal for high pass filter capacitor and impedance matching components.

20 VFB Connection Terminal for high pass filter capacitor and impedance matching components.

21 TL Transient Current Limit Programming Resistor Connection Terminal.

22 VCC Positive Voltage Power Supply, +5V +/-5%.

23 CDCP DC Biasing Filter Capacitor - Positive Terminal.

24 CDCM DC Biasing Filter Capacitor - Negative Terminal.

25 RTD Ring Trip Filter Network Connection Terminal.

26 ILIM Loop Current Limit programming resistor connection terminal.

27 RD Switch Hook Detection threshold programming resistor connection terminal.

28 RING RING Power Amplifier Output.

ISL5586

4-18

Basic Application Circuit

FIGURE 15. SINGLE CHANNEL INTERFACE BETWEEN ISL5586 AND BCM3352

VRXP

VTXP

TIP

VFB

BGNDAGND

RING

VZO

-IN

BSEL

RTD

CDCM

ILIM

DET

POL

RIL CFB

RSH

CRT

RRT

CPOL

CDC

RP1 VCC

VBL

VBH

CPS1

CPS3

CPS2

RTL

RP2

CSH

VTXM

VRSP

VRSM

VRXM

CDCP

ISL5586

B1100CC

F1250T

NOTE: CPS1should be located as close as possible to the

B1100CC to minimize turn-on time. Less than 2 inches is

recommended.

VTX0(-)

VRX0(-)

VRX0(+)

RINGING_OUT(-)

CMLEVEL

RINGING_OUT(+)

VTX0(+)

100K

20K

CX3

CX2

CX1

CT1

CR1

0.068µF0.068µF

CT2

CR2

CR3

BCM3352

SLIC_CTRL0

SLIC_CTRL1

SLIC_CTRL2

SLIC_CTRL3

SLIC_CTRL4

ISL5586

4-19

Interface Diagram

The figure 15 above shows the electrical interface between

the ISL5586 and the BCM3352. Only a single channel is

shown to simplify the diagram. This diagram only shows

electrical interfaces and pertinent external components

Receive Interface

The receive interface of the BCM3352 is directly coupled to

the ISL5586 differential receive input. External filter

capacitors are provided to minimize noise from the

BCM3352. The ISL5586 is designed with a 4-wire to 2-wire

gain of +2.98dB.

Transmit Interface

The differential transmit output of the ISL5586 is AC coupled

to an external passive network. The external passive

network accomplishes many tasks. First, it filters the noise

which may exist on the CMLEVEL output of the BCM3352.

Second, it biases the ground referenced output signals of

the ISL5586 to the CMLEVEL of the BCM3352. Lastly, the

external network attenuates the signal levels coming from

the ISL5586. The ISL5586 is designed with a 2-wire to 4-

wire gain of 0dB and a 4-wire to 4-wire gain of +2.98dB.

Ringing Interface

The ISL5586 onlypassesthe ringing signal on VRSP, VRSM

to Tip and ring only during the ringing mode. Therefore, a

single ringing generator as supplied by the BCM3352 drives

all four sets of ringing inputs in the Broadcom reference

design. The ISL5586 is designed with a differential ringing

gain of 100V/V.

Passive Component Values

The passive component values in the Broadcom reference

design may not be reflected by this document. Please refer

to the Broadcom reference design documentation for the

most recent schematic and COM information.

TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT VALUE TOLERANCE RATING

U1 - Ringing SLIC ISL5586 N/A N/A

RTL 17.8kΩ1% 0.1W

RRT 22.1kΩ1% 0.1W

RSH 40kΩ1% 0.1W

RIL 71.5kΩ1% 0.1W

RS66.5kΩ1% 0.1W

RP1,RP2 0Ω1% 0.1W

CPNot Populated 20% 10V

CRT,C

POL,C

SH 0.47µF20% 10V

CFB 1.0µF20% 10V

CDC 4.7µF20% 10V

CPS1 0.47µF20% >100V

CPS2,C

PS3 0.1µF 20% 100V

CT1,C

T2 4.7µF

CR1,C

R2,C

R3 3300pF

CX1,C

X2,C

X3 150pF

D11N400X Type with Breakdown > 100V.

D2,D31N4935 Type

RP1,R

P2 Protection resistor values are application dependent and will be determined by protection

requirements. Standard applications will use ≥ 49Ωper side.

Design Parameters: Ring Trip Threshold = 81mAPEAK, Switch Hook Threshold = 15mA, Loop Current Limit = 24.6mA, Synthesize Device

Impedance = (3*66.5kΩ)/400 = 498.8Ω, protection resistors = 50Ω, impedance across Tip and Ring terminals = 599Ω. Transient current

limit = 100mA.

ISL5586

4-20

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Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.

Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-

ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No

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ISL5586

Plastic Leaded Chip Carrier Packages (PLCC)

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1

and E1 include mold mismatch and are measured at the extreme

material condition at the body parting line.

4. To be measured at seating plane contact point.

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

-C-

ASEATING

PLANE

0.020 (0.51)

MIN

VIEW “A”

D2/E2

0.025 (0.64)

0.045 (1.14) R

0.042 (1.07)

0.056 (1.42)

0.050 (1.27) TP

EE1

0.042 (1.07)

0.048 (1.22)

PIN (1) IDENTIFIER

0.020 (0.51) MAX

3PLCS 0.026 (0.66)

0.032 (0.81)

0.045 (1.14)

MIN

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)

MIN

VIEW “A” TYP.

0.004 (0.10) C

-C-

D2/E2

N28.45 (JEDEC MS-018AB ISSUE A)

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMINMAXMINMAX

A 0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D 0.485 0.495 12.32 12.57 -

D1 0.450 0.456 11.43 11.58 3

D2 0.191 0.219 4.86 5.56 4, 5

E 0.485 0.495 12.32 12.57 -

E1 0.450 0.456 11.43 11.58 3

E2 0.191 0.219 4.86 5.56 4, 5

N28 286

Rev. 2 11/97