L-700021311 - Agere Systems, Inc.

Data Sheet

August 20, 2003

TSWC03622 SONET/SDH/PDH/ATM

Clock Synthesizer and Protection Switch

1 Introduction

The last issue of this data sheet was September 2002. A

revision history is included in 23 Revision History on page

78. Red change bars have been installed on all text, fig-

ures, and tables that were added or changed. All changes

to the text are highlighted in red. Changes within figures,

and the figure title itself, are highlighted in red, if feasible.

Formatting or grammatical changes have not been high-

lighted. Deleted sections, paragraphs, figures, or tables will

be specifically mentioned.

Throughout this document references are made to the fol-

lowing application notes:

■TSWC01622 Power Supply Grouping and Filtering.

■Clock Requirements for the TSWC03622/TSYN03622

Devices for Ultramapper™ Family Devices.

■TSWC01622/TSYN01622 Loop Filters: Compatible

Components.

■Techniques to Phase Align SYNC8K and CKPDH Out-

puts at 16.384 MHz.

The application notes can be obtained by contacting the

Agere representative, or accessing the web at:

http://www.agere.com/enterprise_metro_access/

system_timing_devices.html

1.1 Features

■Same functionality as TSWC01622 with looser jitter

specifications

■Fully integrated clock synthesis

■Clock or system sync protection switching

■Fast autonomous switching with software override

■Supports a wide choice of SONET/SDH output clock fre-

quencies with jitter quality up to OC-12 as follows:

622.08 MHz 155.52 MHz 77.76 MHz

51.84 MHz 44.736 MHz 38.88 MHz

34.368 MHz 32.768 MHz 24.704 MHz

19.44 MHz 16.384 MHz 8.192 MHz

4.096 MHz 2.43 MHz 2.048 MHz

1.544 MHz

■Five outputs of frequency programmable clocks

■Supports multiple input clock frequencies:

51.84 MHz 38.88 MHz 19.44 MHz

8.192 MHz 6.48 MHz 2.048 MHz

1.544MHz 8kHz

■Generates sync outputs at 8 kHz aligned to an 8 kHz

input clock signal

■Locks to backup reference clock if both the working and

protection reference clocks are lost

■Low skew clock distribution balls

■Compatible with Agere Systems Inc. TDAT04622/

TADM04622 SONET/ATM/POS devices, STSI-144,

TSI-16, TSI-8, TMXF84622 Ultramapper and

TMXF28155 Supermapper ™

■Single 3.3 V supply

■Multiple output technologies—CMOS, LVPECL, or LVDS

■Programmable via external balls or internal resistors via

serial interface

1.2 Applications

■SONET/SDH and PDH add/drop multiplexers, cross con-

nects, switches, and routers

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

Table of Contents

Contents Page

22 Agere Systems Inc.

1 Introduction .........................................................................................................................................................................1

1.1 Features ......................................................................................................................................................................1

1.2 Applications .................................................................................................................................................................1

2 Description .......................................................................................................................................................................... 7

3 Block Diagram .................................................................................................................................................................... 8

4 Pin Information ...................................................................................................................................................................9

4.1 Physical Ball Orientation ............................................................................................................................................12

4.2 Ball Definitions ...........................................................................................................................................................13

5 Functional Overview .........................................................................................................................................................18

6 Description of Transient Switching Behavior ....................................................................................................................19

7 Input Clock Specifications ................................................................................................................................................22

7.1 Input Clock Stability Requirements (Clock A and Clock B) ........................................................................................22

7.2 Input Frequency Selection (FINSEL[3:0]) ..................................................................................................................22

7.3 Input Electrical Level Selection for Clock A and Clock B Input Signals (SELLVDS) .................................................22

7.4 Backup Reference Clock Selection (FBUSEL[3:0]) ...................................................................................................22

7.5 Input Clock Minimum Pulse-Width Specifications (Clock A, Clock B, and CLKBU) ..................................................23

7.5.1 Input Clock Minimum Pulse Width ...................................................................................................................23

7.6 Input Sync Signal Functionality .................................................................................................................................23

8 Output Clock Specifications ..............................................................................................................................................24

8.1 Available Output Clocks ............................................................................................................................................24

9 Jitter Specifications ...........................................................................................................................................................26

10 Synchronization Output at 8 kHz ....................................................................................................................................28

10.1 Sync Output (SYNC8K, SYLVSP/N[1:0], SYPCLKP/N[1:0]) ...................................................................................28

10.2 Sync Duty Cycle Selection (SYDU) .........................................................................................................................28

10.3 Sync Alignment ........................................................................................................................................................28

10.4 Offset Programming (SYOFF[9:0], SYOFFPOS) ....................................................................................................28

11 Skew Specifications ........................................................................................................................................................30

12 Output Specifications During Phase-Locked Condition (Nontransient Condition) ..........................................................35

12.1 Maximum Time Interval Error (MTIE) Specifications ...............................................................................................35

12.2 Time Deviation (TDEV) Specifications ....................................................................................................................36

13 Output Specifications During Transient Condition ..........................................................................................................38

13.1 Maximum Time Interval Error (MTIE) Specifications ...............................................................................................38

14 Other Input and PLL Specifications ................................................................................................................................40

14.1 Input Clock Maximum Rate of Phase Change During Transient .............................................................................40

14.2 External 38.88 MHz VCXO Requirements ..............................................................................................................40

14.3 Loop Filter Components for High-Speed PLL ..........................................................................................................41

14.4 Loop Filter Components for Low-Speed PLL ..........................................................................................................41

14.5 INLOSN ...................................................................................................................................................................43

14.6 RREF .......................................................................................................................................................................43

15 Clock Switching State Machine and Software Interface .................................................................................................44

15.1 Clock Switching State Machine Behavior ................................................................................................................44

15.2 Operation .................................................................................................................................................................44

15.3 Software Interfacing .................................................................................................................................................46

15.4 Loss of Clock Criteria ..............................................................................................................................................46

15.5 Interrupt Generation (INT[8:0]) ................................................................................................................................46

16 Serial Interface and Internal Bus ....................................................................................................................................47

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Table of Contents (continued)

Contents Page

Agere Systems Inc. 3

17 TSWC03622 Registers Map ...........................................................................................................................................49

17.1 Control Block Registers ...........................................................................................................................................51

17.2 Input Clock Block Registers .....................................................................................................................................52

17.3 Switch State Machine Block Registers ....................................................................................................................54

17.4 PDH Output Block Registers ...................................................................................................................................56

17.4.1 Fractional Dividers Registers, 40h—66h ........................................................................................................56

17.4.2 General Configuration Registers, 80h—83h ..................................................................................................57

17.5 SDH/Sync Generation Block Registers ...................................................................................................................61

17.6 LVPECL Output Syncs and Clocks .........................................................................................................................66

17.7 CMOS Output Syncs and Clocks ............................................................................................................................66

17.8 LVDS Output Syncs and Clocks ..............................................................................................................................67

18 Absolute Maximum Ratings ............................................................................................................................................72

18.1 Handling Precautions ..............................................................................................................................................72

18.2 Operating Conditions ...............................................................................................................................................72

18.3 Powerup Conditions ................................................................................................................................................72

19 Electrical Characteristics ................................................................................................................................................73

19.1 LVPECL, LVDS, CMOS, Input, and Output Balls ....................................................................................................73

20 Timing Characteristics ....................................................................................................................................................75

21 Packaging Diagram ........................................................................................................................................................76

21.1 208-Plastic Ball Grid Array (17 x 17)-0.63 mm Ball Size (4-Layer—Bottom View) ..................................................76

22 Ordering Information .......................................................................................................................................................77

23 Revision History ..............................................................................................................................................................78

23.1 Navigating Through an Adobe Acrobat Document ..................................................................................................78

23.2 Changes ..................................................................................................................................................................78

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

Table of Contents (continued)

Figures Page

44 Agere Systems Inc.

Figure 3-1. TSWC03622 Block Diagram ................................................................................................................................8

Figure 4-1. TSWC03622 208-Ball PBGA (Top View) .............................................................................................................9

Figure 6-1. Transient Behavior for Small Phase Differences in Input Clocks.......................................................................20

Figure 6-2. Transient Behavior for Large Phase Differences in Input Clocks.......................................................................21

Figure 7-1. Input Clock Minimum Pulse-Width Requirement................................................................................................23

Figure 9-1. Phase Noise Characteristic for Differential Output Clock CK51 Using LSPLL Filter..........................................27

Figure 9-2. Phase Noise Characteristic for Differential Output Clock CK77 Using LSPLL Filter..........................................27

Figure 11-1. PECL Sync to PECL Clock Skew Case: Sync Aligned to 622 MHz Clock.......................................................30

Figure 11-2. PECL Sync to PECL Clock Skew Case: Sync Aligned to 155 MHz Clock.......................................................31

Figure 11-3. LVDS Sync to LVDS Clock Skew Case: Sync Aligned to 622 MHz Clock.......................................................32

Figure 11-4. LVDS Sync to LVDS Clock Skew Case: Sync Aligned to 155 MHz Clock.......................................................33

Figure 11-5. CMOS Clock to CMOS Sync Skew Case: Sync Aligned to SONET CMOS Output Clock ..............................34

Figure 12-1. MTIE Wander Generation in Locked Condition................................................................................................35

Figure 12-2. Measured MTIE Wander Generation Performance..........................................................................................36

Figure 12-3. Wander Generation in Locked Condition .........................................................................................................37

Figure 12-4. Measured TDEV Wander Generation Performance.........................................................................................37

Figure 13-1. MTIE Wander Generation During Transient Condition ....................................................................................38

Figure 13-2. Measured MTIE Performance at Two Different Phase Offsets ........................................................................39

Figure 14-1. High-Speed Loop Filter Recommended Circuit................................................................................................41

Figure 14-2. Recommended Low-Speed Phase Lock Loop (LSPLL) Filter Circuit for Smaller Phase Offsets ....................42

Figure 14-3. Recommended Low-Speed Phase-Lock Loop (LSPLL) Filter Circuit for All Phase Offsets ............................42

Figure 15-1. Clock Protection Control Circuit State Diagram ...............................................................................................44

Figure 16-1. TSWC03622 Serial Interface ...........................................................................................................................47

Figure 16-2. Serial Interface WRITE Frame Format.............................................................................................................47

Figure 16-3. Serial Interface READ Frame Format ..............................................................................................................48

Figure 16-4. Serial Interface Timing .....................................................................................................................................48

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Table of Contents (continued)

Tables Page

Agere Systems Inc. 5

Table 4-1. Ball Assignments for 208-Ball PBGA by Ball Number Order ...............................................................................10

Table 4-2. Physical Ball Orientation (Bumps Down) .............................................................................................................12

Table 4-3. Clock Inputs and Related Signals........................................................................................................................13

Table 4-4. Analog and PLL Related Signals .........................................................................................................................13

Table 4-5. Output Clocks and Related Signals .....................................................................................................................14

Table 4-6. Control and Related Signals ................................................................................................................................15

Table 4-7. Serial Interface Signals........................................................................................................................................16

Table 4-8. Test and Reserved Signals ..................................................................................................................................16

Table 4-9. No-Connect Signals.............................................................................................................................................16

Table 4-10. Power Signals....................................................................................................................................................17

Table 7-1. Input Clock A and Clock B Frequency Selection .................................................................................................22

Table 7-2. Backup Clock Frequency Configuration ..............................................................................................................22

Table 8-1. SDH Output Clock Selection (SDHSEL[3:0]).......................................................................................................24

Table 8-2. PDH Output Clock Selection (PDHSEL[3:0]).......................................................................................................25

Table 9-1. Output Clock Jitter Specifications ........................................................................................................................26

Table 10-1. Sync Duty Cycle Selection (SYDU) ...................................................................................................................28

Table 10-2. SYNC Offset Programming................................................................................................................................29

Table 10-3. Enhanced SYNC Offset Programming ..............................................................................................................29

Table 11-1. PECL Sync to PECL Clock Skew Parameters ...................................................................................................30

Table 11-2. PECL Sync to PECL Clock Skew Parameters...................................................................................................31

Table 11-3. LVDS Sync to LVDS Clock Skew Parameters ...................................................................................................32

Table 11-4. LVDS Sync to LVDS Clock Skew Parameters ...................................................................................................33

Table 11-5. CMOS Sync to CMOS Clock Skew Parameters (15 pF, 1 kW)..........................................................................34

Table 12-1. Wander Generation (Nontransient)—MTIE........................................................................................................35

Table 12-2. Wander Generation (Nontransient)—TDEV.......................................................................................................36

Table 13-1. Wander Generation (Transient)—MTIE .............................................................................................................38

Table 14-1. High-Speed Loop Filter Recommended Values.................................................................................................41

Table 14-2. Recommended Low-Speed Loop Filter Values for Smaller Phase Offsets........................................................41

Table 14-3. Recommended Low-Speed Loop Filter Values for All Phase Offsets................................................................42

Table 15-1. Interrupt Generation (INT[8:0]) Active-High .......................................................................................................46

Table 17-1. TSWC03622 Registers ......................................................................................................................................49

Table 17-2. Hardware Reset for All TSWC03622 Blocks .....................................................................................................51

Table 17-3. Software Override..............................................................................................................................................52

Table 17-4. Loss of Clock Block Software Override and Reset ............................................................................................52

Table 17-5. FINSEL[3:0] Register.........................................................................................................................................52

Table 17-6. FBUSEL[3:0] Register .......................................................................................................................................53

Table 17-7. Loss of Clock Threshold ....................................................................................................................................53

Table 17-8. Loss of Clock Hysteresis ...................................................................................................................................53

Table 17-9. Switch Block Control Register ...........................................................................................................................54

Table 17-10. Switch Block State Machine Register ..............................................................................................................54

Table 17-11. Squelch ............................................................................................................................................................55

Table 17-12. Lockout Threshold ...........................................................................................................................................55

Table 17-13. Switch Time-Out Settings ................................................................................................................................56

Table 17-14. PDH Control Register 1 ...................................................................................................................................57

Table 17-15. PDH Clock Outputs for the 16 Preset Configurations (Bit 81h(3) = 0).............................................................57

Table 17-16. PDH Control Register 2 ...................................................................................................................................58

Table 17-17. Enhanced Software Mode Fractional Divider Selection...................................................................................58

Table 17-18. Software Mode Fractional Divider Selection....................................................................................................59

Table 17-19. Fractional Dividers Operation Mode ................................................................................................................60

Table 17-20. SDH/Sync Control Register .............................................................................................................................61

Table 17-21. SDHSEL Register ............................................................................................................................................62

Table 17-22. Sync Duty Cycle ..............................................................................................................................................62

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

Table of Contents (continued)

Tables Page

66 Agere Systems Inc.

Table 17-23. Output Sync Duty Cycle...................................................................................................................................62

Table 17-24. Sync Offset ......................................................................................................................................................63

Table 17-25. Sync Source ....................................................................................................................................................64

Table 17-26. SONET/SDH Clock Enable..............................................................................................................................65

Table 17-27. LVPECL Output Clock Status When Influenced by Programmable Duty Cycle on Syncs...............................66

Table 17-28. LVPECL Output Clock Status When Influenced by Programmable Duty Cycle on Syncs...............................66

Table 17-29. LVDS Output Clock Status When Influenced by Programmable Duty Cycle on Syncs ...................................67

Table 17-30. Sync Duty Cycle ..............................................................................................................................................67

Table 17-31. CMOS SONET Clock Edge Selection .............................................................................................................68

Table 17-32. Enhanced Sync Offset .....................................................................................................................................68

Table 17-33. Sync Rising Edge Position...............................................................................................................................69

Table 17-34. Sync Falling Edge Position ..............................................................................................................................69

Table 17-35. Sync Delta .......................................................................................................................................................70

Table 17-36. Sync Delta Rise ...............................................................................................................................................70

Table 17-37. Interrupt Status Register..................................................................................................................................71

Table 18-1. Absolute Maximum Ratings ...............................................................................................................................72

Table 18-2. ESD Protection Characteristics .........................................................................................................................72

Table 18-3. Recommended Operation Conditions................................................................................................................72

Table 19-1. LVDS Output dc Characteristics ........................................................................................................................73

Table 19-2. LVDS Input dc Characteristics ...........................................................................................................................73

Table 19-3. CMOS Input dc Characteristics .........................................................................................................................74

Table 19-4. CMOS Output dc Characteristics.......................................................................................................................74

Table 19-5. LVPECL Output dc Characteristics....................................................................................................................74

Table 20-1. LVDS Input ac Timing Characteristics ...............................................................................................................75

Table 20-2. LVDS Output ac Timing Characteristics.............................................................................................................75

Table 20-3. CMOS Input ac Timing Characteristics..............................................................................................................75

Table 22-1. Ordering Information..........................................................................................................................................77

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 7

2 Description

The Agere Systems TSWC03622 is designed for a wide variety of synchronous timing applications. It serves as a clock

synthesizer and low skew clock fan-out device generating clocks at frequencies up to 622.08 MHz that are synchronized to

the system reference clock. It also serves as an intelligent clock protection switch with fast autonomous selection based on

the presence of the two input clocks. Alternatively, clock switching can be controlled entirely through a software interface by

the user. The TSWC03622 also delivers an output sync signal that is aligned to the input clock. If 8 kHz system sync sig-

nals are applied as the clock A and clock B inputs, the TSWC03622 will generate an output sync signal that is phase

aligned to the selected input sync. A programmable phase offset is provided to allow the user to offset the output sync rela-

tive to the input sync. The output sync can be used for global alignment of cells or frames in SONET/SDH/PDH cross con-

nects or ATM switch applications. The device allows flexible choices of LVDS or LVCMOS input technologies and LVDS,

LVPECL, or LVCMOS output technologies.

The TSWC03622 is intended for clock distribution and protection switching on a line card, a switch card, or a shelf timing

card. Along with the wide variety of input and output frequencies, a unique feature of the device is a guaranteed correct

number of output clock cycles between output sync pulses before, during, and after a clock selection switching event. The

number of clock cycles between sync pulses remains correct even during a switch between working and protection clock

sources that have an arbitrary phase relationship between them. The TSWC03622 also solves the skew problem associ-

ated with timing distribution over cable or backplane traces of different lengths.

The TSWC03622 can be programmed via external balls, or through a serial interface. Enhanced functionality is available

through the serial interface, including programmable clock outputs through fractional synthesis and the ability to enable or

disable each output individually.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

88 Agere Systems Inc.

3 Block Diagram

Note: The grayed out portions of the figure indicate that they are test features.

Figure 3-1. TSWC03622 Block Diagram

SDHSEL[3:0]

CK19

CK38

CK51

CK77

CK155N[1:0]

CK155P[1:0]

PCK155N[1:0]

PCK155P[1:0]

CK622N

CK622P

PCK622N

PCK622P

SYPCLN[1:0]

SYPCLP[1:0]

SYLVSN[1:0]

SYLVSP[1:0]

SYNC8K

SYDU

SYOFFPOS

SYOFF[9:0]

TSTCLKN

TSTCLKP

VC[P:N]

LF[P:N]

INLOSN

LSVCO

LF0

RREF

DIVIDE

LOC38

DIVIDE

SYNC

OFFSET

BASED ON SDHSEL

SONET

CLOCK

GEN.

DIVIDE

VCO

LOCBU

CONTROL

AND

SWITCH

STATE

MACHINE

PDH

CLOCK

GEN.

SERIAL I/F

CONTROL

PHASE

COMPARE

LOCA

DIV_M

CLKAP

CLKAN

CLKA

CLKBP

CLKBN

CLKB

SELLVDS

CLKBU

FBUSEL[3:0]

SELCLK

SELBUN

AUTOSWN

REVERTN

SWCONTN

ENSQLN

ENLON

LORSTN

RESETN

SWSTATE[1:0]

INT[8:0]

CKPDH5

CKPDH4

CKPDH3

CKPDH2

CKPDH1

PDHSEL[3:0]

TSTMODE

SERCLK

SERENBLN

SERDAT

DIV_N

ENTSTCLK

VCXO

38.88 MHz

LOCB

DIV_M

FINSEL[3:0]

SYCLKB

SYCLKA ENABLE/

DISABLE LF0Z

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 9

4 Pin Information

2360 (F)

Figure 4-1. TSWC03622 208-Ball PBGA (Top View)

234 67891011121314151615

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

1010 Agere Systems Inc.

Note: — refers to no ball. NC means do not connect any traces to this solder ball.

Table 4-1. Ball Assignments for 208-Ball PBGA by Ball Number Order

Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name

A1 GND C1 PCK155P0 E1 SYPCLN0 G1 VDDPECL

A2 CK155N0 C2 CK38 E2 FINSEL0 G2 VDDPECL

A3 CK155P0 C3 CKPDH1 E3 FINSEL3 G3 VDDPECL

A4 GND C4 CKPDH3 E4 SYNC8K G4 CK77

A5 SYLVSN0 C5 CKPDH5 E5 —G5 —

A6 SYLVSP0 C6 VDDLVDS E6 —G6 —

A7 GND C7 GND E7 —G7 GND

A8 CK622N C8 GND E8 —G8 GND

A9 CK622P C9 GND E9 —G9 GND

A10 GND C10 GND E10 —G10 GND

A11 SYLVSN1 C11 VDDSDH E11 —G11 —

A12 SYLVSP1 C12 SYOFF2 E12 —G12 —

A13 GND C13 SYOFF5 E13 SYOFF9 G13 NC

A14 CK155N1 C14 SYOFF8 E14 VDDHSPD G14 INLOSN

A15 CK155P1 C15 VDDTCLK E15 VDDLSVCO G15 LFN

A16 GND C16 TSTCLKN E16 LSVCO G16 VCN

B1 PCK155N0 D1 VDDPECL F1 SYPCLP0 H1 PCK622N

B2 CK19 D2 VDDSDH F2 VDDPECL H2 VDDPECL

B3 VDDPDH D3 GND F3 GND H3 FINSEL2

B4 CKPDH2 D4 GND F4 CK51 H4 FINSEL1

B5 VDDPDH D5 CKPDH4 F5 —H5 —

B6 GND D6 VDDPDH F6 —H6 —

B7 GND D7 VDDLVDS F7 —H7 GND

B8 GND D8 RREF F8 —H8 GND

B9 GND D9 VDDLVDS F9 —H9 GND

B10 GND D10 SYOFF0 F10 —H10 GND

B11 GND D11 SYOFF1 F11 —H11 —

B12 GND D12 SYOFF3 F12 —H12 —

B13 GND D13 SYOFF4 F13 SYOFFPOS H13 GND

B14 SYOFF6 D14 SYOFF7 F14 VDDHSPD H14 GND

B15 TSTMODE D15 SYDU F15 VDDHSVCO H15 LFP

B16 TSTCLKP D16 GND F16 GND H16 VCP

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 11

Table 4-1. Ball Assignments for 208-Ball PBGA by Ball Number Order (continued)

Note: — refers to no ball. NC means do not connect any traces to this solder ball.

Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name

J1 PCK622P L1 SYPCLN1 N1 VDDPECL R1 PCK155P1

J2 VDDPECL L2 SDHSEL0 N2 SERDAT R2 SERCLK

J3 VDDPECL L3 SDHSEL3 N3 SERENBLN R3 GND

J4 GND L4 SDHSEL1 N4 GND R4 GND

J5 —L5 —N5 INT8 R5 PDHSEL0

J6 —L6 —N6 INT5 R6 INT7

J7 GND L7 —N7 INT4 R7 INT3

J8 GND L8 —N8 VDDFF R8 GND

J9 GND L9 —N9 INT1 R9 GND

J10 GND L10 —N10 INT0 R10 INT2

J11 —L11 —N11 SWSTATE1 R11 GND

J12 —L12 —N12 SELLVDS R12 LORSTN

J13 GND L13 FBUSEL3 N13 GND R13 GND

J14 VDDHSDIV L14 FBUSEL2 N14 ENSQLN R14 GND

J15 VDDHSVCO L15 SELCLK N15 RESETN R15 GND

J16 NC L16 FBUSEL1 N16 SWCONTN R16 GND

K1 VDDPECL M1 SYPCLP1 P1 PCK155N1 T1 VDDPECL

K2 VDDPECL M2 VDDCNTL P2 PDHSEL3 T2 VDDCLKBU

K3 GND M3 VDDCNTL P3 PDHSEL2 T3 CLKBU

K4 SDHSEL2 M4 SDH_HW P4 GND T4 PDHSEL1

K5 —M5 —P5 GND T5 GND

K6 —M6 —P6 INT6 T6 CLKB

K7 GND M7 —P7 MON8KB T7 CLKBN

K8 GND M8 —P8 SYCLKB T8 CLKBP

K9 GND M9 —P9 VDDFF T9 GND

K10 GND M10 —P10 SYCLKA T10 CLKAP

K11 —M11 —P11 MON8KA T11 CLKAN

K12 —M12 —P12 SWSTATE0 T12 CLKA

K13 FBUSEL0 M13 GND P13 ENLON T13 GND

K14 VDDHSDIV M14 AUTOSWN P14 VDDLSPLL T14 LF2

K15 LF0Z M15 REVERTN P15 VDDLSPLL T15 LF1

K16 NC M16 SELBUN P16 VDDCNTL T16 LF0

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

1212 Agere Systems Inc.

4.1 Physical Ball Orientation

Table 4-2. Physical Ball Orientation (Bumps Down)

1 2 345678910111213141516

AGND CK155N0 CK155P0 GND SYLVSN0 SYLVSP0 GND CK622N CK622P GND SYLVSN1 SYLVSP1 GND CK155N1 CK155P1 GND

BPCK155N0 CK19 VDDPDH CKPDH2 VDDPDH GND GND GND GND GND GND GND GND SYOFF6 TSTMODE TSTCLKP

CPCK155P0 CK38 CKPDH1 CKPDH3 CKPDH5 VDDLVDS GND GND GND GND VDDSDH SYOFF2 SYOFF5 SYOFF8 VDDTCLK TSTCLKN

DVDDPECL VDDSDH GND GND CKPDH4 VDDPDH VDDLVDS RREF VDDLVDS SYOFF0 SYOFF1 SYOFF3 SYOFF4 SYOFF7 SYDU GND

ESYPCLN0 FINSEL0 FINSEL3 SYNC8K SYOFF9 VDDHSPD VDDLSVCO LSVCO

FSYPCLP0 VDDPECL GND CK51 SYOFFPOS VDDHSPD VDDHSVCO GND

GVDDPECL VDDPECL VDDPECL CK77 GND GND GND GND NC INLOSN LFN VCN

HPCK622N VDDPECL FINSEL2 FINSEL1 GND GND GND GND GND GND LFP VCP

JPCK622P VDDPECL VDDPECL GND GND GND GND GND GND VDDHSDIV VDDHSVCO NC

KVDDPECL VDDPECL GND SDHSEL2 GND GND GND GND FBUSEL0 VDDHSDIV LF0Z NC

LSYPCLN1 SDHSEL0 SDHSEL3 SDHSEL1 FBUSEL3 FBUSEL2 SELCLK FBUSEL1

MSYPCLP1 VDDCNTL VDDCNTL SDH_HW GND AUTOSWN REVERTN SELBUN

NVDDPECL SERDAT SERENBLN GND INT8 INT5 INT4 VDDFF INT1 INT0 SWSTATE1 SELLVDS GND ENSQLN RESETN SWCONTN

PPCK155N1 PDHSEL3 PDHSEL2 GND GND INT6 MON8KB SYCLKB VDDFF SYCLKA MON8KA SWSTATE0 ENLON VDDLSPLL VDDLSPLL VDDCNTL

RPCK155P1 SERCLK GND GND PDHSEL0 INT7 INT3 GND GND INT2 GND LORSTN GND GND GND GND

TVDDPECL VDDCLKBU CLKBU PDHSEL1 GND CLKB CLKBN CLKBP GND CLKAP CLKAN CLKA GND LF2 LF1 LF0

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 13

4.2 Ball Definitions

This section describes each of the device pins.

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

Table 4-3. Clock Inputs and Related Signals

Ball Symbol*Type†Level Name/Description

T10,

T11

CLKAP

CLKAN

IDLVDS Input Clock A. Used when LVDS level is desired for interfacing to

input clock A source.

T12 CLKA IDCMOS Input Clock A. Used when CMOS level is desired for interfacing to

input clock A source.

T8,

CLKBP

CLKBN

IDLVDS Input Clock B. Used when LVDS level is desired for interfacing to

input clock B source.

T6 CLKB IDCMOS Input Clock B. Used when CMOS level is desired for interfacing to

input clock B source.

N12 SELLVDS IUCMOS Select Clock Level (LVDS/CMOS). Selects the LVDS or the CMOS

input balls as the clock A and B sources:

0 = CMOS (CLKA, CLKB).

1 or no connection = LVDS (CLKAP/N, CLKBP/N).

E3, H3,

H4, E2

FINSEL[3:0] IUCMOS Input Frequency Select. Program to indicate the input frequency of

the clock A and B sources.

T3 CLKBU IDCMOS Backup Clock. CMOS level input backup clock source.

L13, L14,

L16, K13

FBUSEL[3:0] IUCMOS Backup Clock Frequency Select. Program to indicate the input fre-

quency of the backup clock source. Set to 0000.

P10 SYCLKA IDCMOS Sync Input A. CMOS synchronization input used to align output

8 kHz syncs to a system synchronization signal.

P8 SYCLKB IDCMOS Sync Input B. CMOS synchronization input used to align output

8 kHz syncs to a system synchronization signal.

Table 4-4. Analog and PLL Related Signals

Ball Symbol*Type†Level Name/Description

E16 LSVCO ICMOS 38.88 MHz VCXO. Connection to external VCXO output.

T14, T15 LF2, LF1 Analog —Connect to Ground.

T16 LF0 Analog —38.88 MHz PLL Loop Filter.

K15 LF0Z IUCMOS 38.88 MHz PLL Loop Filter Enable. CMOS logic high enables LF0.

CMOS logic low sets output LF0 to high-impedance state.

H15,

G15

LFP

LFN

Analog —High-Speed PLL Loop Filter. Connect to external loop filter compo-

nents and also connect LFP to VCP and LFN to VCN.

H16,

G16

VCP

VCN

Analog —High-Speed VCO Control Voltage. Connect to external loop filter com-

ponents and connect VCP to LFP and VCN to LFN.

G14 INLOSN IUCMOS Input Loss of Signal. Active-low input signal forces control voltage on

high-speed oscillator to the lowest end of the oscillator frequency range:

0 = force lowest-frequency operation in high-speed oscillator.

1 or no connection = normal operation.

D8 RREF Analog —Resistor Reference. LVDS output voltage reference resistor. Insert a

1.5 kΩ resistor from RREF to VDDLVDS.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

1414 Agere Systems Inc.

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

Table 4-5. Output Clocks and Related Signals

Ball Symbol*Type†Level Name/Description

A9,

CK622P

CK622N

OLVDS 622.08 MHz Output Clock.

J1,

PCK622P

PCK622N

OLVPECL 622.08 MHz Output Clock.

A15, A3

A14, A2

CK155P[1:0]

CK155N[1:0]

OLVDS 155.52 MHz Output Clock.

R1, C1

P1, B1

PCK155P[1:0]

PCK155N[1:0]

OLVPECL 155.52 MHz Output Clock.

G4 CK77 OCMOS 77.76 MHz Output Clock.

F4 CK51 OCMOS 51.84 MHz Output Clock.

C2 CK38 OCMOS 38.88 MHz Output Clock.

B2 CK19 OCMOS 19.44 MHz Output Clock.

L3, K4, L4, L2 SDHSEL[3:0] IDCMOS SDH Clock Output Selection.

E4 SYNC8K OCMOS 8 kHz Output Sync.

A12, A6

A11, A5

SYLVSP[1:0]

SYLVSN[1:0]

OLVDS 8 kHz Sync Buffers [1:0].

M1, F1

L1, E1

SYPCLP[1:0]

SYPCLN[1:0]

OLVPECL 8 kHz Sync Buffers [1:0].

E13, C14, D14,

B14, C13, D13,

D12, C12, D11,

D10

SYOFF[9:0] IDCMOS Sync Offset. Programs the magnitude of the offset of the output

syncs relative to an input 8 kHz clock/sync.

F13 SYOFFPOS IUCMOS Sync Offset Positive or Negative. Selects the direction of the

sync offset:

1 = positive offset. The output sync is delayed in time.

0 = negative offset. The output sync is advanced in time.

D15 SYDU IUCMOS Sync Duty Cycle. Selects the duty cycle of the output sync sig-

nals:

1 = 50% duty cycle.

0 = sync logic high time equal to one period of the

highest-frequency active SONET output clock.

C5 CKPDH5 OCMOS Selectable PDH Output Clock.

D5 CKPDH4 OCMOS Selectable PDH Output Clock.

C4 CKPDH3 OCMOS Selectable PDH Output Clock.

B4 CKPDH2 OCMOS Selectable PDH Output Clock.

C3 CKPDH1 OCMOS Selectable PDH Output Clock.

P2, P3, T4, R5 PDHSEL[3:0] IDCMOS PDH Clock Output Selection.

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 15

Table 4-6. Control and Related Signals

Ball Symbol Type †Level Name/Description

L15 SELCLK IUCMOS Select Clock. Select clock A or clock B (when SELBUN = 1):

1 = select clock A.

0 = select clock B.

This signal is overridden by SELBUN when SELBUN is active.

M16 SELBUN IUCMOS Select Backup Clock. Active-low signal selects CLKBU:

0 = select CLKBU, overrides SELCK.

1 = allow SELCLK to select clock A or clock B.

M14 AUTOSWN IUCMOS Autoswitching Enabled. Active-low signal allows the user to enable autono-

mous switching from the currently selected clock:

0 = autonomous switching is enabled. (Software control must be disabled

(SWCONTN = 1).)

1 = autonomous switching is disabled.

M15 REVERTN IUCMOS Revertive Switching Enabled. Active-low signal determines if the user would

like to revert to the original reference source after a fault clears:

1 = state machine is nonreverting such that the switch will not return to the orig-

inal clock after the fault condition ceases to exist.

0 = state machine is reverting such that the switch will return to the original

state after the error condition ceases to exist and at least 256 ms have

passed since the switch.

N16 SWCONTN IUCMOS Software Control. Active-low signal allows the user to explicitly choose which

clock input to use. Activating this input causes SELCLK and SELBUN to over-

ride any fault checking before switching:

0 = software control is enabled. Device is in manual switching mode and, when

instructed, switches to a clock even if it is in a loss of clock state (overrides

AUTOSWN setting).

1 = software control is disabled. User cannot switch to a clock in a loss of clock

state.

N14 ENSQLN IUCMOS Enable Squelch. Active-low signal enables automatic squelching of the clock

and sync outputs whenever a fault is encountered. When squelching occurs, all

output clock and sync signals will be held at a logic-low output level.

If the device is not in software control mode (SWCONTN = 1), the outputs will be

squelched if squelch is enabled and all input clocks (clock A, clock B, CLKBU)

are lost:

1 = automatic squelching of the outputs is disabled.

0 = automatic squelching of the outputs is enabled.

If the device is in the software override mode (SWCONTN = 0), then ENSQLN

can be used to manually squelch the device clock outputs:

1 = normal device clock output operation.

0 = manually squelch the device clock outputs.

N15 RESETN IUCMOS Reset. Active-low asynchronous reset.

P13 ENLON IUCMOS Enable Lockout. Active-low signal allows the user to provide a lockout function

to prevent excessive switching between references:

1 = free to switch for any fault.

0 = lockout the autonomous switch whenever the internal lockout flag is active

due to excessive switching.

R12 LORSTN IUCMOS Lockout Trigger Reset. Active-low signal resets the lockout counter to prevent

locking out the protection switch:

0 = clear the lockout counter.

1 = normal lockout counter operation.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

1616 Agere Systems Inc.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

N11, P12 SWSTATE

[1:0]

OCMOS Switch State. Reflects whether the device is currently selecting clock A, clock

B, or the backup clock:

00 = clock A active.

01 = clock B active.

10 = backup clock active (previous clock source was clock A).

11 = backup clock active (previous clock source was clock B).

N5, R6,

P6, N6,

N7, R7,

R10, N9,

N10

INT[8:0] OCMOS Interrupts. Active-high interrupts define fault conditions. See Table 15-1 on

page 46 for individual interrupt definitions.

Table 4-7. Serial Interface Signals

Ball Symbol Type†Level Name/Description

R2 SERCLK IUCMOS Serial Interface Clock. Serial interface clock that can operate up to 25 MHz.

N3 SERENBLN IUCMOS Serial Interface Enable. This signal must be low during register access.

N2 SERDAT I/OUCMOS Serial Data. This is a bidirectional ball for writing and reading software registers.

Table 4-8. Test and Reserved Signals

Ball Symbol*Type†Level Name/Description

B15 TSTMODE IDCMOS Test Mode. Internal test observation signal used in test mode. Do not connect or

apply any signal to this ball.

B16,

C16

TSTCLKP

TSTCLKN

IDLVDS Test Clock Input. Do not connect or apply any signal to these balls.

P11 MON8KA OCMOS Monitor 8 kHz from Clock A. Internal test observation signal. Do not connect or

apply any signal to this ball. (If input clock A is setup and applied correctly, this

signal should measure exactly 8 kHz.)

P7 MON8KB OCMOS Monitor 8 kHz from Clock B. Internal test observation signal. Do not connect or

apply any signal to this ball. (If input clock B is setup and applied correctly, this

signal should measure exactly 8 kHz.)

M4 SDH_HW IDCMOS Internal Signal. Internal test signal. Do not connect or apply any signal to this

ball. (When set to a CMOS logic high, the SDH block takes information directly

from the external leads and does not use information from the internal bus (reg-

isters).)

Table 4-9. No-Connect Signals

Ball Symbol*Type†Level Name/Description

G13, J16, K16 NC — — Not connected.

Table 4-6. Control and Related Signals (continued)

Ball Symbol Type †Level Name/Description

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 17

* Differential pairs are indicated by P and N suffixes. For nondifferential signals, N at the end of the symbol name designates active-low.

† I = input, O = output. IU indicates an internal 50 kΩ pull-up resistor on this ball. ID indicates an internal 50 kΩ pull-down resistor on this ball.

Table 4-10. Power Signals

For information on power supply grouping and filtering, refer to the TSWC01622 Power Supply Grouping and Filtering Ap-

plication Note.

Ball Symbol*Type†Level Name/Description

C11, D2 VDDSDH Power — —

D1, F2, G1, G2, G3, H2, J2, J3, K1,

K2, N1, T1

VDDPECL Power — —

D9, C6, D7 VDDLVDS Power — —

M2, M3, P16 VDDCNTL Power — —

T2 VDDCLKBU Power — —

N8, P9 VDDFF Power — —

P14, P15 VDDLSPLL Power — —

K14, J14 VDDHSDIV Power — —

J15, F15 VDDHSVCO Power — —

E15 VDDLSVCO Power — —

E14, F14 VDDHSPD Power — —

D6, B5, B3 VDDPDH Power — —

C15 VDDTCLK Power — —

A1, A4, A7, A10, A13, A16, B6, B7, B8, B9,

B10, B11, B12, B13, C7, C8, C9, C10, D3,

D4, D16, F3, F16, G7, G8, G9, G10, H7, H8,

H9, H10, H13, H14, J4, J7, J8, J9, J10, J13,

K3, K7, K8, K9, K10, M13, N4, N13, P4, P5,

R3, R4, R8, R9, R11, R13, R14, R15, R16,

T5, T9, T13

GND Ground — —

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

1818 Agere Systems Inc.

5 Functional Overview

The TSWC03622 is designed to manage clock generation and timing distribution in SONET/SDH compliant line card solu-

tions up to OC-12 data rates. Its output clocks are designed to enable hitless clock switching between a primary and sec-

ondary clock source and meet relevant output clock jitter generation specifications and maximum time interval error (MTIE)

during a switching transient. It supports a range of common input frequencies from 8 kHz to 51.84 MHz. A backup fre-

quency source is also supported that can be used as a frequency reference when both primary and secondary input clocks

are lost. During a switch from either the primary or the secondary clock inputs to the backup reference input, the

TSWC03622 output clocks do not guarantee compliance with SONET MTIE specifications. An integrated digital state

machine monitors the presence of all input clock signals and can provide autonomous clock switching under fault condi-

tions. Several programmable options are available that determine the behavior of clock switching, including complete soft-

ware control of the switching events. Programming of the TSWC03622 can be accomplished through external ball control

or through internal registers, via a serial interface. A range of SONET and PDH clock frequencies are generated with

155 MHz and 622 MHz clocks available on multiple low-skew LVDS and LVPECL output buffers in order to provide fan-out

and clock distribution sources for multiple chips within the system. An 8 kHz sync signal with a user-programmable offset is

generated and is available on CMOS, LVDS, and LVPECL output buffers. The duty cycle of the 8 kHz output sync signal is

selectable as either 50% or as the width of a single clock pulse determined by the maximum selected SONET/SDH related

output frequency.

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 19

6 Description of Transient Switching Behavior

The TSWC03622 is designed for application in systems that utilize a number of different timing and data distribution archi-

tectures. Because the frequency and phase alignment of timing distribution signals, as well as the architectures used for

frame alignment and data buffering all vary for different system architectures and product implementations, the characteris-

tics of the TSWC03622’s switching behavior must be properly exploited by the system architecture. A description of the

switching transient behavior is provided here.

In general, two timing signals will be distributed as the clock A and clock B inputs to the TSWC03622. These inputs may

range in frequency from 8 kHz to 51.84 MHz. In some cases, the timing source that generates clock A and clock B is

designed such that the two clocks are coupled. Therefore, the relative phase of clock A and clock B will be small. In other

cases, the phases of clock A and clock B will be uncontrolled with respect to each other and the phase difference between

the two clocks could be up to a full period of the input frequency. When the input frequency is relatively high, the phase dif-

ference can only be a few tens of nanoseconds due to the small time period of one clock cycle. In the cases where the input

frequency is relatively low and the two timing sources are not cross coupled, the phase difference can be up to many tens

of microseconds due to the large time period of one clock cycle. When the input frequency is relatively low but the two tim-

ing sources have been cross coupled and the skew has been well controlled as the signals are distributed, the phase differ-

ence may be controlled within just a few tens of nanoseconds.

Some system architectures rely on the fact that there will be a small phase difference between the primary and secondary

timing signals, and therefore, they do not provide extensive data buffering or alignment capabilities elsewhere in the sys-

tem. They rely on a hitless phase step when a switch occurs between clock A and clock B followed by a slow adjustment or

bleed out of the phase step during a transient period. The phase bleed out adjustment must, however, comply with MTIE

and TDEV requirements during a transient switching event as defined in relevant standards.

System architectures that use low-frequency signals for timing distribution but do not cross couple the timing sources may

have a large phase difference between clock A and clock B at the time a clock switch is initiated. In this case, the output

clocks must still have a hitless phase step at the moment the switch occurs. However, SONET MTIE requirements do not

generally allow the subsequent phase bleed out to completely adjust for the entire phase difference. Bleeding out the entire

phase difference at a rate consistent with MTIE and TDEV transient requirements would cause the transient condition to

exist for a duration longer than allowed in the standards. Therefore, systems that distribute low-frequency timing signals

with arbitrary skew must provide extensive data buffering or alignment capabilities elsewhere in the system.

The TSWC03622 provides hitless phase switching with clock inputs of arbitrary phase difference at frequencies from 8 kHz

to 51.84 MHz. However, a complete adjustment or bleed out of the phase will occur only for phase differences less than

approximately 250 ns. For all input phase differences of greater than this, the transient will cease after the maximum phase

has been adjusted (maximum 250 ns). Figure 6-1 shows the TSWC03622 switching transient behavior for the condition of

small phase differences between input clocks. Figure 6-2 shows the TSWC03622 switching transient behavior for the con-

dition of large phase differences between input clocks.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

2020 Agere Systems Inc.

* This diagram shows the phase relationship of the clock outputs and the sync outputs. In the case of PDH clock outputs, the timing relationship between

clock and sync is not necessarily as shown here since the phase relationship between the PDH clock outputs and an 8 kHz sync is not specified.

Figure 6-1. Transient Behavior for Small Phase Differences in Input Clocks

PDH/SDH*

tPHASE < APPROX 250 Qs

CLOCK-A

CLOCK-B

SYNC OUTPUTS

PDH/SDH

SYNC OUTPUTS

PDH/SDH

SYNC OUTPUTS

PDH/SDH

SYNC OUTPUTS

INPUT CLOCKS

OUTPUT CLOCKS/SYNCS PRIOR TO SWITCH

OUTPUT CLOCKS/SYNCS AT INSTANT OF SWITCH

OUPUT CLOCKS/SYNCS DURING TRANSIENT

OUTPUT CLOCKS/SYNCS AT END OF

SELECTED

STANDBY

CLOCK OUTPUTS

FROM CLOCK-A TO CLOCK-B HITLESS PHASE SWITCH

PHASE MOVEMENT MEETS MTIE/TDEV

TRANSIENT OUTPUTS ALIGNED TO CLOCK-B

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 21

* This diagram shows the phase relationship of the clock outputs and the sync outputs. In the case of PDH clock outputs, the timing relationship between

clock and sync is not necessarily as shown here since the phase relationship between the PDH clock outputs and an 8 kHz sync is not specified.

Figure 6-2. Transient Behavior for Large Phase Differences in Input Clocks

PDH/SDH*

tPHASE > APPROX 250 Qs

CLOCK-A

CLOCK-B

SYNC OUTPUTS

PDH/SDH

SYNC OUTPUTS

PDH/SDH

SYNC OUTPUTS

PDH/SDH

SYNC OUTPUTS

INPUT CLOCKS

SELECTED

STANDBY

CLOCK OUTPUTS

tPHASE = 250 ns (MAX)

OUTPUT CLOCKS/SYNCS PRIOR TO SWITCH

OUTPUT CLOCKS/SYNCS AT INSTANT OF SWITCH

OUPUT CLOCKS/SYNCS DURING TRANSIENT

OUTPUT CLOCKS/ SYNCS AT END OF TRANSIENT

FROM CLOCK-A TO CLOCK-B HITLESS PHASE SWITCH

PHASE MOVEMENT MEETS MTIE/TDEV

MAXIMUM PHASE BLEED

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

2222 Agere Systems Inc.

7 Input Clock Specifications

7.1 Input Clock Stability Requirements (Clock A and Clock B)

The clock A and clock B inputs to the TSWC03622 must be compliant with all requirements for a SONET minimum clock

(SMC) as defined in Telcordia ™ GR-253-CORE Section 5.4.4.2 (Issue 3, 9/2000), or for an ITU node clock as defined in

G.812, in order for the TSWC03622 to meet its output clock specifications and transient phase requirements.

7.2 Input Frequency Selection (FINSEL[3:0])

The input clock signal frequencies that are supported on the clock A and clock B inputs, as well as the appropriate fre-

quency selection control ball programming, are given in Table 7-1. Input frequency selection can be performed by using

external balls FINSEL[3:0] or by programming register 0x21 bits 3:0 (with SDH_HW ball low).

7.3 Input Electrical Level Selection for Clock A and Clock B Input Signals (SELLVDS)

When SELLVDS = 0, the CLKA and CLKB CMOS level input buffers are selected as the clock A and clock B inputs. When

SELLVDS = 1 (or no connection is made to the SELLVDS ball), the CLKAP/N and CLKBP/N LVDS level input buffers are

selected as the clock A and clock B inputs.

7.4 Backup Reference Clock Selection (FBUSEL[3:0])

The TSWC03622 provides the ability to switch to a backup clock under certain fault conditions. When the backup clock is

selected, the transient phase response of the TSWC03622 is not guaranteed to meet any requirements associated with a

switching event between the A and B clock inputs. The backup is intended to offer a frequency control reference only and is

not intended to meet any of the requirements of a system holdover state. CLKBU functions at a clock rate of 8 kHz. To con-

figure CLKBU for operation, set FBUSEL[3:0] to 0000 as shown in Table 7-2. If a different backup clock rate is required,

please contact your Agere Systems representative. Backup reference frequency configuration can be performed by using

external balls FBUSEL[3:0] or by programming register 0x22 bits 3:0 (with SDH_HW ball low).

* If a different backup clock rate is required, please contact the Agere Systems representative.

† Tolerance needed for the TSWC03622 to maintain frequency lock with specified VCXO. This tolerance is not intended to represent a system require-

ment.

Table 7-1. Input Clock A and Clock B Frequency Selection

Input Frequency Clock A and Clock B FINSEL3 FINSEL2 FINSEL1 FINSEL0

8kHz NC 0 0 0

1.544 MHz NC 0 0 1

2.048 MHz NC 0 1 0

6.480 MHz NC 0 1 1

8.192 MHz NC 1 0 0

19.44 MHz NC 1 0 1

38.88 MHz NC 1 1 0

51.84 MHz NC 1 1 1

Table 7-2. Backup Clock Frequency Configuration

Input Frequency

CLKBU*

Tolerance (ppm)†FBUSEL3 FBUSEL2 FBUSEL1 FBUSEL0

8kHz ±20 0000

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 23

7.5 Input Clock Minimum Pulse-Width Specifications (Clock A, Clock B, and CLKBU)

In order for the TSWC03622 to guarantee functionality and that all transient timing specifications are met, the input clock

must maintain a minimum pulse width tPW = 8 ns for input frequencies greater than 8 kHz; for an input frequency of 8 kHz,

a 50% ± 5% duty cycle is required, as shown in Figure 7-1.

7.5.1 Input Clock Minimum Pulse Width

2363 (F)

Figure 7-1. Input Clock Minimum Pulse-Width Requirement

7.6 Input Sync Signal Functionality

If an 8 kHz (or a slower multiple of 8 kHz) is input, then the 8 kHz output signals (SYNC8K, SYLVSP/N[1:0], and

SYPLP/N[1:0]) will be aligned to the active SYCLK with a small phase offset due to the delay through the chip.

CLOCK-A, CLOCK-B,

tPW

OR BACKUP CLOCK

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

2424 Agere Systems Inc.

8 Output Clock Specifications

8.1 Available Output Clocks

The TSWC03622 supports the generation of the SONET/SDH and PDH frequencies given in Table 9-1, as well as the abil-

ity to program frequency output rates up to 65.536 MHz on CKPDH[1:3] and 38.88 MHz on CKPDH[4:5], using fractional

synthesis. Not all PDH frequencies listed in Ta b l e 8 - 2 are available simultaneously. Table 8-1 and Tab le 8- 2 illustrate the

combination of output clock frequencies available simultaneously based on the PDHSEL[3:0] and SDHSEL[3:0] control

words.

There are several levels of programming the PDH1—PDH5 outputs. The PDHSEL[3:0] control word can be programmed

using external balls PDHSEL[3:0] (with mode bits 0x81 bits 4:3 set to 00, which is the default state) or by programming reg-

ister 0x80 bits 15:12 (with mode bits 0x81 bits 4:3 set to 10). Additionally, each PDH output can be programmed individually

using registers 0x82 and 0x83 (with mode bits 0x81 bits 4:3 set to 01 or 11). If the mode for any PDH output is set to

0B1110, then any frequency can be programmed to the output, up to 65.536 MHz on CKPDH[1:3] and 38.88 MHz on

CKPDH[4:5], using the outputs respective registers in the range 0x40 to 0x66. To program these registers, please contact

Agere to get an automated program that provides programming instructions based on the desired frequency output.

The SDHSEL[3:0] control word can be programmed using external balls SDHSEL[3:0] or by programming register 0xA1

bits 3:0 (with 0xA0 bit 1 high and SDH_HW ball low). Individual SONET/SDH output syncs and clocks can also be enabled

or disabled individually using registers 0xA4 and 0xA5 respectively. Additionally, the CK77, CK51, CK38, and CK19 clocks

can be aligned such that either the positive or the negative edge is aligned to an input 8 kHz signal using register 0xA7

(with 0XA0 bits 1 and 2 low).

* Z = high impedance.

† If SYDU = 0, duty cycle = 50%. If SYDU = 1, sync logic high time equal to one period of a 155.52 MHz clock (6.43 ns).

‡ If SYDU = 0, duty cycle = 50%. If SYDU = 1, sync logic high time equal to one period of a 622.08 MHz clock (1.6075 ns).

Table 8-1. SDH Output Clock Selection (SDHSEL[3:0])

Clock/Sync

Output Name

SDHSEL[3:0] State Value and Associated Output Signals*

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CK622P/N Z622.08

MHz

622.08

MHz

Z622.08

MHz

Z622.08

MHz

Z Z Z Z Z Z Z Z Z

PCK622P/N Z622.08

MHz

Z622.08

MHz

Z622.08

MHz

0 Z 622.08

MHz

Z Z Z Z Z Z Z

CK155P/N[1] 155.52

MHz

ZZZ155.52

MHz

Z Z 155.52

MHz

Z Z Z Z Z Z Z Z

CK155P/N[0] 155.52

MHz

Z155.52

MHz

Z155.52

MHz

Z Z 155.52

MHz

Z Z Z Z Z Z Z Z

PCK155P/N[1] 155.52

MHz

155.52

MHz

ZZZ155.52

MHz

Z Z Z 155.52

MHz

Z Z Z Z Z Z

PCK155P/N[0] 155.52

MHz

155.52

MHz

Z155.52

MHz

Z155.52

MHz

Z Z Z 155.52

MHz

Z Z Z Z Z Z

CK77 Z77.76

MHz

ZZZZZZZZ77.76

MHz

77.76

MHz

Z Z Z Z

CK51 51.84

MHz

ZZZZZZZZZ51.84

MHz

Z51.84

MHz

Z Z Z

CK38 Z ZZZZZZZZZ38.88

MHz

Z Z 38.88

MHz

Z Z

CK19 19.44

MHz

ZZZZZZZZZ19.44

MHz

ZZZ19.44

MHz

SYNC8K Z8.0 kHz ZZZZZZZZ8.0

kHz

8.0

kHz

8.0

kHz

8.0

kHz

8.0

kHz

SYLVSP/N[1] 8.0 kHz

†

Z8.0 kHz

‡

Z8.0 kHz

†

Z Z 8.0 kHz

†

Z Z Z Z Z Z Z Z

SYLVSP/N[0] 8.0 kHz

†

8.0 kHz

‡

8.0 kHz

†

Z8.0 kHz

†

Z8.0 kHz

†

8.0 kHz

†

Z Z Z Z Z Z Z Z

SYPCLP/N[1] Z8.0 kHz

†

Z8.0 kHz

†

Z8.0 kHz

†

Z Z Z 8.0 kHz

†

Z Z Z Z Z Z

SYPCLP/N[0] 8.0 kHz

†

8.0 kHz

†

Z8.0 kHz

†

Z8.0 kHz

†

Z Z 8.0 kHz

‡

8.0 kHz

†

Z Z Z Z Z Z

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 25

* Z = high impedance.

Table 8-2. PDH Output Clock Selection (PDHSEL[3:0])

Clock/Sync

Output Name

PDHSEL[3:0] State Value and Associated Output Signals*

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CKPDH5 2.43

MHz

Z1.544

MHz

1.544

MHz

ZZZ2.43

MHz

ZZZZZZZZ

CKPDH4 1.544

MHz

Z2.048

MHz

2.048

MHz

1.544

MHz

1.544

MHz

Z Z Z Z Z Z Z Z Z Z

CKPDH3 2.048

MHz

Z24.704

MHz

24.704

MHz

2.048

MHz

Z2.048

MHz

Z4.096

MHz

8.192

MHz

Z Z Z Z Z Z

CKPDH2 32.768

MHz

Z32.768

MHz

32.768

MHz

Z Z Z Z Z Z 16.384

MHz

Z32.768

MHz

Z Z Z

CKPDH1 44.736

MHz

Z34.368

MHz

44.736

MHz

ZZZZZZZ24.704

MHz

Z34.368

MHz

44.736

MHz

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

2626 Agere Systems Inc.

9 Jitter Specifications

The clock frequencies listed in Table 9-1 are normally available at their respective output balls under the indicated condi-

tions. The jitter specifications listed apply whenever input clock A is selected or input clock B is selected, as well as during

any transients due to a switching event between clock A and clock B. The jitter specifications are met if the input clocks

comply with the input clock stability requirements. For representative jitter measurements for the CKPDH1—CKPDH5 out-

puts when used with the Agere Systems TMXF84622 device, consult the Clock Requirements for the TSWC03622/

TSYN03622 Devices for Ultramapper Family Devices Application Note.

* CK19 and CK38 signals are divided down from the CK77 output and have similar phase noise (jitter) performance as the CK77 output.

† For applications requiring lower generated jitter, please contact the Agere Systems representative.

Table 9-1. Output Clock Jitter Specifications

Parameter Ball Output

Frequency

Typ (RMS Only) Max Unit Measurement

Bandwidth

Jitter

Generation

CK19* 19.44 MHz — — — —

CK38* 38.88 MHz — — — —

CK51 51.84 MHz 0.03 (see Figure 9-1)<0.2

<2.0

mUIRMS

mUIp-p

12 kHz—40 kHz (OC-1)

0.06 (see Figure 9-1) <0.4

<4.0

mUIRMS

mUIp-p

12 kHz—400 kHz (OC-1)

0.05 (see Figure 9-1) <0.4

<4.0

mUIRMS

mUIp-p

12 kHz—130 kHz (OC-3)

0.11 (see Figure 9-1) <0.6

<6.0

mUIRMS

mUIp-p

12 kHz—1.3 MHz (OC-3)

CK77 77.76 MHz 0.09 (see Figure 9-2)<0.3

<3.0

mUIRMS

mUIp-p

12 kHz—500 kHz (OC-12)

0.20 (see Figure 9-2) <0.625

<6.25

mUIRMS

mUIp-p

12 kHz—5 MHz (OC-12)

CK155P/N,

PCK155P/N

155.52 MHz —<0.6

<6.0

mUIRMS

mUIp-p

12 kHz—130 kHz (OC-3)

—<1.0†

<10†

mUIRMS

mUIp-p

12 kHz—1.3 MHz (OC-3)

CK622P/N,

PCK622P/N

622.08 MHz —<3.8†

<36†

mUIRMS

mUIp-p

12 kHz—500 kHz (OC-12)

—<4.0†

<40†

mUIRMS

mUIp-p

12 kHz—5 MHz (OC-12)

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 27

Figure 9-1. Phase Noise Characteristic for Differential Output Clock CK51 Using LSPLL Filter

Figure 9-2. Phase Noise Characteristic for Differential Output Clock CK77 Using LSPLL Filter

Note: See Figure 14-3 for LSPLL filter diagram.

-140

-130

-120

-110

-100

-90

-80

1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07

Frequency From Carrier (Hz)

SSB Magnitude (dBc/Hz)

-140

-130

-120

-110

-100

-90

-80

1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07

Frequency From Carrier (dBc/Hz)

SSB Magnitude (dBc/H

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

2828 Agere Systems Inc.

10 Synchronization Output at 8 kHz

10.1 Sync Output (SYNC8K, SYLVSP/N[1:0], SYPCLKP/N[1:0])

The TSWC03622 generates an output 8 kHz synchronization signal for use in frame and cell alignment in systems that

require this capability. Typically, the output sync is meaningful only in systems that distribute 8 kHz synchronization signals

as the timing references on clock A and clock B. In these cases, the alignment of the output sync to the input sync (8 kHz

on clock A and clock B inputs) is a critical aspect of system synchronization. When higher-speed clocks are distributed, the

alignment of the sync with respect to the input clock becomes arbitrary. Sync outputs can be configured along with the

SONET/SDH clock outputs with the SDHSEL[3:0] control word. The SDHSEL[3:0] control word can be programmed using

external balls SDHSEL[3:0] or by programming register 0xA1 bits 3:0 (with 0xA0 bit 1 high and SDH_HW ball low). Individ-

ual SONET/SDH output syncs can also be enabled or disabled individually using register 0xA4.

10.2 Sync Duty Cycle Selection (SYDU)

There are several methods of controlling the sync output duty cycle. In the first method, the SDHSEL[3:0] output frequency

is used. In this method, the duty cycle of the 8 kHz sync signals is selectable as either 50% or as the width of a single

SONET clock pulse width. When the duty cycle is selected to be a single clock pulse width, the pulse width of the respec-

tive sync-signal is determined to be equal to one period of the highest-frequency active SONET output of similar output

technology type (for example, the CMOS SYNC8K output will have the pulse width of the highest-frequency active SONET

CMOS output). The frequencies of the active PDH clocks are not considered. Sync duty cycle selection can be performed

using external ball SYDU or by programming register 0xA2 bit 0 (with register 0xA0 bit 2 high and SDH_HW ball low).

A second method is used when the sync outputs are individually enabled through register 0xA4. In this method, pulse-width

options remain selectable as either 50% or as the width of a single SONET clock pulse width. Pulse widths are selected

using register 0xA4 in conjunction with register 0xA6.

The last method is to adjust the falling edge of the sync outputs using register 0xB2, which, in effect, adjusts the duty cycle.

(The rising edge can be adjusted using the sync offset programming explained below.)

10.3 Sync Alignment

When 8 kHz synchronization signals are applied as input timing on clock A and clock B, the output sync is phase aligned to

the input sync to. Adjustments of this delay may be made using the TSWC03622 sync offset programmability feature.

10.4 Offset Programming (SYOFF[9:0], SYOFFPOS)

Some system applications require the 8 kHz synchronization to be offset according to the demands of the system architec-

ture. The TSWC03622 provides the capability of offsetting the output sync in increments of 1.6075 ns (one 622.08 MHz

clock).

The sync offset will apply to all output syncs (SYN8K, SYLVSP/N[1:0], SYPCLP/N[1:0]) simultaneously. There are two

types of offset capability on the TSWC. The first has the capability to offset up to ±1.644 µs with a resolution of 1.6075 ns

(±1023 periods of a 622.08 MHz clock with a resolution of one period of the 622.08 MHz clock). This offset can be per-

formed using external balls SYOFF[9:0] and SYOFFPOS or by programming register 0xA3 bits 10:0 (with register 0xA0

bit 3 high and SDH_HW ball low). Programming of the sync offset is described in Table 10-2.

Table 10-1. Sync Duty Cycle Selection (SYDU)

SYDU SYNC8K Duty Cycle

150%

0High for one period of highest-frequency active SONET clock output

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 29

The second type of sync offset is an enhanced capability that enables the sync to be offset over the entire 125 µs period (in

the same increments of 1.6075 ns). This is accomplished using 16 bits of offset and a positive/negative directional control.

This functionality is available by programming registers 0xA8 and 0xA9 (with register 0xA0 bit 3 low and SDH_HW ball

low). The programming is similar to the first offset type and is shown in Table 10-3.

Note: There is a limit to the size of the offset so that the offset is not greater than one 125 µs period.

Table 10-2. SYNC Offset Programming

Ball Function

SYOFF[9:0] Sets the magnitude of the sync offset value in increments of 1/622.08 MHz or 1.6075 ns:

SYOFF[9:0] = 0000000000 equals zero offset.

. . .

SYOFF[9:0] = 1111111111 equals 1.644 µs (1023/622.08 MHz) offset.

SYOFFPOS Sets the sign or direction of the sync offset:

SYOFFPOS = 1 is a positive offset. The output sync is delayed in time.

SYOFFPOS = 0 is a negative offset. The output sync is advanced in time.

Table 10-3. Enhanced SYNC Offset Programming

Ball Function

SYOFF[16:0] Sets the magnitude of the sync offset value in increments of 1/622.08 MHz or 1.6075 ns:

SYOFF[16:0] = 0 0000 0000 0000 0000 equals zero offset.

. . .

SYOFF[16:0] = 1 0010 1111 0110 0000 equals 125 µs (77760/622.08 MHz) offset.

SYOFFPOS Sets the sign or direction of the sync offset:

SYOFFPOS = 1 is a positive offset. The output sync is delayed in time.

SYOFFPOS = 0 is a negative offset. The output sync is advanced in time.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

3030 Agere Systems Inc.

11 Skew Specifications

2364 (F)

Figure 11-1. PECL Sync to PECL Clock Skew Case, Syncs Aligned to 622 MHz Clock

Table 11-1. PECL Sync to PECL Clock Skew Parameters

A single clock pulse sync output shown.

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

PCK622P/N

SYPCLP/N[1:0]

t100 Clock Falling to Sync Rising 00.5 0.235 ns

PCK622P/N t101/t103 Clock Duty Cycle 45 55 50 %

PCK622P/N

SYPCLP/N[1:0]

t102 Clock Falling to Sync Falling 00.5 0.220 ns

PCK622P/N

t100

SYPCLP/N[1:0]

t102

t103

t101

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 31

2365 (F)

Figure 11-2. PECL Sync to PECL Clock Skew Case: Sync Aligned to 155 MHz Clock

Table 11-2. PECL Sync to PECL Clock Skew Parameters

A single clock pulse sync output shown.

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

PCK155P/N[0]

SYPCLP/N[0]

t200 Clock Falling to Sync Rising –1.0 0–0.735 ns

PCK155P/N[0] t201/t203 Clock Duty Cycle 45 55 50 %

PCK155P/N[0]

SYPCLP/N[0]

t202 Clock Falling to Sync Falling –1.0 0–0.745 ns

PCK155P/N[1]

SYPCLP/N[1]

t210 Clock Falling to Sync Rising –1.0 0–0.720 ns

PCK155P/N[1] t211/t213 Clock Duty Cycle 45 55 50 %

PCK155P/N[1]

SYPCLP/N[1]

t212 Clock Falling to Sync Falling –1.0 0–0.700 ns

PCK155P/N[0]

t200

SYPCLP/N[0]

t202

t203

t201

PCK155P/N[1]

t210

SYPCLP/N[1]

t212

t213

t211

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

3232 Agere Systems Inc.

2366 (F)

Figure 11-3. LVDS Sync to LVDS Clock Skew Case: Sync Aligned to 622 MHz Clock

Table 11-3. LVDS Sync to LVDS Clock Skew Parameters

A single clock pulse sync output shown.

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

CK622P/N

SYLVSP/N[1:0]

t300 Clock Falling to Sync Rising 00.5 0.185 ns

CK622P/N t301/t303 Clock Duty Cycle 45 55 51 %

CK622P/N

SYLVSP/N[1:0]

t302 Clock Falling to Sync Falling 00.5 0.205 ns

CK622P/N

t300

SYLVSP/N[1:0]

t302

t303

t301

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 33

2367 (F)

Figure 11-4. LVDS Sync to LVDS Clock Skew Case: Sync Aligned to 155 MHz Clock

Table 11-4. LVDS Sync to LVDS Clock Skew Parameters

A single clock pulse sync output shown.

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

CK155P/N[0]

SYLVSP/N[0]

t400 Clock Falling to Sync Rising –1.0 0–0.745 ns

CK155P/N[0] t401/t403 Clock Duty Cycle 45 55 50 %

CK155P/N[0]

SYLVSP/N[0]

t402 Clock Falling to Sync Falling –1.0 0–0.750 ns

CK155P/N[1]

SYLVSP/N[1]

t410 Clock Falling to Sync Rising –1.0 0–0.725 ns

CK155P/N[1] t411/t413 Clock Duty Cycle 45 55 50 %

CK155P/N[1]

SYLVSP/N[1]

t412 Clock Falling to Sync Falling –1.0 0–0.745 ns

CK155P/N[0]

t400

SYLVSP/N[0]

t402

t403

t401

CK155P/N[1]

t410

SYLVSP/N[1]

t412

t413

t411

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

3434 Agere Systems Inc.

Figure 11-5. CMOS Clock to CMOS Sync Skew Case: Sync Aligned to SONET CMOS Output Clock

Table 11-5. CMOS Sync to CMOS Clock Skew Parameters (15 pF, 1 kΩ)

Parameters are not tested, but are a result of device characterization data. A single clock pulse sync output shown.

Applicable

Balls

Symbol Skew Parameter Min Max Typ Unit

CK19, SYNC8K t500 Clock Rising to Sync Rising –0.50 0.50 0.15 ns

CK19, SYNC8K t502 Clock Rising to Sync Falling 0.00 1.50 0.80 ns

CK38, SYNC8K t500 Clock Rising to Sync Rising –0.50 0.50 0.05 ns

CK38, SYNC8K t502 Clock Rising to Sync Falling 0.00 1.50 0.60 ns

CK51, SYNC8K t500 Clock Rising to Sync Rising –0.50 0.50 –0.05 ns

CK51, SYNC8K t502 Clock Rising to Sync Falling 0.00 1.50 0.50 ns

CK77, SYNC8K t500 Clock Rising to Sync Rising –0.50 0.50 –0.20 ns

CK77, SYNC8K t502 Clock Rising to Sync Falling 0.00 1.50 0.50 ns

t500

t502

t501

t503

CK19, CK38,

CK51, CK77

SYNC8K

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 35

12 Output Specifications During Phase-Locked Condition (Nontransient Condition)

12.1 Maximum Time Interval Error (MTIE) Specifications

During the phase-locked condition, the TSWC03622 output clocks will meet wander generation as given in

Table 12-1 and shown in Figure 12-1. When in the locked condition, the MTIE performance will be dominated by the MTIE

of the incoming timing signals on clock A and clock B. The TSWC03622 will not add significantly to the MTIE performance.

Measured performance data is shown in Figure 12-2.

2368 (F)

Figure 12-1. MTIE Wander Generation in Locked Condition

Table 12-1. Wander Generation (Nontransient)—MTIE

Observation Interval

(s)

TSWC03622 Max

(ns)

GR-253-CORE

Figure 5-17 (9/2000) (ns)

GR-1244-CORE

Figure 5-2 (6/95) (ns)

ITU-T

G.813 Option 2

Table 4 (8/96) (ns)

S < 0.1 NA NA NA NA

0.1 < S < 1.0 20 20 40 20

1 < S < 10 20 x S 0.48 20 x S 0.48 40 x S 0.40 20 x S 0.48

10 < S < 100 60 60 100 60

100 < S < 1000 60 —100 60

S > 1000 100 —100 —

100

1000

1 10 100 1000

0.1

OBSERVATION INTERVAL (s)

GR-253 CORE

ITU-T G.813 OPTION 2

GR-1244 CORE

MTIE (ns)

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

3636 Agere Systems Inc.

Figure 12-2. Measured MTIE Wander Generation Performance

12.2 Time Deviation (TDEV) Specifications

During the phase-locked condition, the TSWC03622 output clocks will meet TDEV as given in Table 12-2 and shown in Fig-

ure 12-3. When in the locked condition, the TDEV performance will be dominated by the incoming timing signals on clock A

and clock B and the TSWC03622 will not add significantly to the TDEV performance. Measured performance data is shown

in Figure 12-4.

Table 12-2. Wander Generation (Nontransient)—TDEV

Integration Interval

(s)

TSWC03622 Max

(ns)

GR-253-CORE

Figure 5-18 (9/2000) (ns)

GR-1244-CORE

Figure 5-1 (6/95) (ns)

ITU-T

G.813 Option 2

Table 5 (8/96) (ns)

0.1 < τ < 2.5 3.2 x τ –0.5 3.2 x τ –0.5 3.2 x τ –0.5 3.2 x τ –0.5

2.5 < τ < 40 22 2 2

40 < τ < 1000 0.32 x τ 0.5 0.32 x τ 0.5 0.32 x τ 0.5 0.32 x τ 0.5

τ > 1000 10 10 10 —

1000 < τ < 10,000 10 — — 10

100

1000

0.01 0.10 1.00 10.00 100.00 1000.00

MTIE (ns)

Time (sec)

GR-253-CORE/ITU-T G.183 Opt 2

MTIE Requirement

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 37

2369 (F)

Figure 12-3. Wander Generation in Locked Condition

Figure 12-4. Measured TDEV Wander Generation Performance

100

1 10 100 1000

0.1

OBSERVATION INTERVAL (s)

GR-253 CORE

TDEV (ns)

10000

ITU-T G.813 OPTION 2

AND GR-1244 CORE

0.01

0.1

100

0.1 1 10 100 1000 10000 100000

Observation Interval (s)

TDEV (ns)

GR-253-CORE/GR-1244-CORE/G.813 Opt. 2

TDEV Requirement

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

3838 Agere Systems Inc.

13 Output Specifications During Transient Condition

13.1 Maximum Time Interval Error (MTIE) Specifications

During the transient condition, the TSWC03622 output clocks will meet wander generation as given in Table 13-1 and

shown in Figure 13-1.

* Requirement 5-10 also indicates that the maximum phase slope or discontinuity be less than 81 ns for any measurement period of 1.326 ms.

2370 (F)

Figure 13-1. MTIE Wander Generation During Transient Condition

Table 13-1. Wander Generation (Transient)—MTIE

Observation Interval

(s)

TSWC03622 Max

(ns)

GR-253-CORE

Figure 5-19 (9/2000) (ns)

GR-1244-CORE

R5-10 (6/95)* (ns)

ITU-T

G.813 Option 2

Table 14 (8/96) (ns)

τ < 0.014 1000 NA 1000 NA

0.014 < τ < 0.16 7.6 + 885τ7.6 + 885τ1000 7.6 + 885τ

0.16 < τ < 0.5 7.6 + 885τ7.6 + 885τ1000 7.6 + 885τ

0.5 < τ < 2.33 300 + 300τ300 + 300τ1000 300 + 300τ

2.33 < τ < 280 1000 1000 1000 1000

1000

10000

0.1 1 10 10000.01

OBSERVATION INTERVAL (s)

MTIE (ns)

100

GR-1244 CORE

ITU-T G.813 OPTION 2

AND GR-253 CORE

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 39

Figure 13-2. Measured MTIE Performance at Two Different Phase Offsets

0.01 0.10 1.00

TIME (s)

100

1000

MTIE (ns)

GR-253-CORE

FIGURE 5-19 (1/99)

∆φ ≥ 250 ns

∆φ = 10 ns

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

4040 Agere Systems Inc.

14 Other Input and PLL Specifications

14.1 Input Clock Maximum Rate of Phase Change During Transient

In order for the TSWC03622 to guarantee functionality and that all transient MTIE specifications are met, the clock A and

clock B inputs must have an instantaneous maximum rate of change consistent with the ITU G.812 requirements for a node

clock and Telcordia GR-253-CORE Section 5.4.4.2 (Issue 3, 9/2000).

14.2 External 38.88 MHz VCXO Requirements

The following is a brief specification for the 38.88 MHz VCXO unit:

■Supply voltage: 3.30 V ± 5%

■Control voltage range: 0.3 V minimum, 2.7 V maximum

■Temperature range (ambient): –40 °C to +85 °C

■Output buffer:

— Technology: CMOS (3.30 V)

— Duty cycle: 45/55%

— Transient times: 1 ns maximum (20% to 80%)

■Frequency (nominal): 38.88 MHz

■APR: ±20 ppm

Note: The APR must include the effects of temperature, supply voltage, shock, vibration, aging, and manufacturing (i.e.,

withstanding two solder reflows).

■Linearity: ±20% (best linear fit 0.3 V to 2.7 V)

■Transfer function: monotonic, positive slope

■Center voltage: VDD/2 (nominal 1.65 V)

■Modulation bandwidth: 10 kHz at 38.88 MHz

■Input leakage current: <1 µA

■Input resistance: >3 MΩ

■Reference signal for control voltage: ground

■Phase jitter: 1 ps (RMS) maximum 12 kHz to 20 MHz (alternate spec may be expressed in dBc if required)

■Start-up time: 2 ms at maximum control voltage

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 41

14.3 Loop Filter Components for High-Speed PLL

The recommended loop filter is shown in Figure 14-1. Connect the filter components and also connect LFP to VCP and

connect LFN to VCN. The component values can be varied to adjust the loop dynamic response. Table 14-1 provides a set

of recommended values to meet output jitter generation requirements in Ta b l e 9 - 1 .

Figure 14-1. High-Speed Loop Filter Recommended Circuit

14.4 Loop Filter Components for Low-Speed PLL

The recommended loop filter for phase offsets of clock A and clock B of less than ±30 ns (including all input frequencies for

19.44 MHz, 38.88 MHz, and 51.84 MHz) is shown in Figure 14-2 and Table 14-2. If the phase offset of clock A and clock B

is unknown or will be greater than ±30 ns, then the recommended filter is shown in Figure 14-3 and corresponding compo-

nent values are shown in Table 14-3.

Analog switches are included in both circuits to reduce the lock time at start-up. This part of the circuitry is only active when

the LSPLL is out of lock; it will not become active during a clock switch. In the filter for smaller phase offsets, the addition of

the analog switch will reduce the nominal lock time from tens of seconds to less than 6 seconds. In the filter for larger

phase offsets, the nominal lock time is reduced from a few minutes to less than 40 seconds.

Note: For information on requirements for the various loop filter components and recommended solutions, consult the

TSWC01622/TSYN01622 Loop Filters: Compatible Components Application Note.

* Capacitors C1, C2, and C3 should be either ceramic or nonpolar.

† 1% resistors are recommended for R1 and R2 because the low-speed PLL filter has high sensitivity to these resistors. However, if these 1% resistors

are not available, the 5% resistors indicated in parentheses are compatible and will make the loop filter function correctly.

Table 14-1. High-Speed Loop Filter Recommended Values

Components Recommended Values

C1*

0.1 µF to 1.0 µF ± 10%

R1 3.9 kΩ ± 5%

* Capacitor C1 should be either ceramic or nonpolar.

Table 14-2. Recommended Low-Speed Loop Filter Values for Smaller Phase Offsets

Components Recommended Values

C1* 10 µF ± 20%

C2, C3 * 4.7 µF ± 10%

R1†392 kΩ ± 1% (390 kΩ ± 5%)

R2†1.21 kΩ ± 1% (1.2 kΩ ± 5%)

R3 20 kΩ to 110 kΩ ± 5% (lower value yields faster lock time)

R4 383 kΩ ± 1% (390 kΩ ± 5%)

U1‡Analog switch

VCXO1 See VCXO requirements

LFP

LFN

VCN

VCP

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

4242 Agere Systems Inc.

Figure 14-2. Recommended Low-Speed Phase-Lock Loop (LSPLL) Filter Circuit for Smaller Phase Offsets

* Capacitors C1, C2, C3, C4, and C5 should be either ceramic or nonpolar.

† 1% resistors are recommended for R1, R2, R3, and R6 because the low-speed PLL filter has high sensitivity to these resistors. However, if these 1%

resistors are not available, the 5% resistors indicated in parentheses are compatible and will make the loop filter function correctly.

‡For information on requirements for the various loop filter components and recommended solutions, consult the TSWC01622/TSYN01622 Loop Filters:

Compatible Components Application Note.

Figure 14-3. Recommended Low-Speed Phase-Lock Loop (LSPLL) Filter Circuit for All Phase Offsets

Table 14-3. Recommended Low-Speed Loop Filter Values for All Phase Offsets

Components Recommended Values for All Clock A and Clock B Phase Offsets (See Figure 14-3.)

C1* 1000 pF ± 10%

C2, C3, C4, C5* 47 µF ± 20%

R1†4.99 kΩ ± 1% (5.1 kΩ ± 5%)

R2†2.49 kΩ ± 1% (2.4 kΩ ± 5%)

R3†750 kΩ ± 1% (750 kΩ ± 5%)

R4 20 kΩ ± 5%

R5 10 kΩ ± 5%

R6†2.21 kΩ ± 1% (2.2 kΩ ± 5%)

R7†383 kΩ ± 1% (390 kΩ ± 5%)

R8†110 kΩ ± 5%

U1‡Analog switch

VCXO1 See VCXO requirements

LF0

INT5

VCXO1

LSVCO

OUT

LF0

C4 VCX01

OUT

INT5

LSVCO

VDDLSPLL

LF0Z

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 43

14.5 INLOSN

The INLOSN signal will force the high-speed PLL to drift towards a lower clamped frequency, preventing an excessive high-

frequency clock output under invalid input signal conditions. INLOSN may be used to limit the internal clock frequency

ensuring proper state machine and control behavior under severe clock fault conditions.

14.6 RREF

RREF should be tied to VDDLVDS through a 1.5 kΩ resistor.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

4444 Agere Systems Inc.

15 Clock Switching State Machine and Software Interface

15.1 Clock Switching State Machine Behavior

The TSWC03622 is designed to perform fast, automatic protection switching between primary and secondary clock inputs

to the device. The clock switching control circuit implements the following functional requirements:

■Autonomously switch from the selected clock to the other clock if the selected clock fails.

■Manually switch to any clock input.

■Provide a lockout control to prevent excessive autonomous switching.

■Provide an override to allow revertive switching, but force the minimum time for reversion to 256 ms from the time the

switch was initially made.

■Provide a squelch function to bring the device clock outputs to a logic low state (squelched) if clock A, clock B, and

CLKBU signals all have a fault.

15.2 Operation

The operation of the clock protection switching control circuit depends on the device inputs and internally generated control

signals. This control is performed by a finite state machine containing three states, and there are two modes of operation:

autonomous switching (circuit makes decision on what action to take) and nonautonomous switching (external controller

makes decision on what action to take). However, in either mode of operation, the control circuit will enforce a time-out

period between switching events to allow the internal phase-locked loops time to acquire phase lock to the currently

selected reference clock. The state diagram of the control circuit state machine is shown in Figure 15-1.

2371 (F)

Figure 15-1. Clock Protection Control Circuit State Diagram

The device will select the reference clocks based upon the internal state: reference A if in state A, reference B if in state B,

and reference BU if in state BU. The autonomous mode of operation is selected by setting the device signal AUTOSWN to

a logic low. In this mode, after the initial reset of the device, the state machine is in state A selecting reference clock A. If

the internal loss of clock detector on clock A indicates the absence of clock A, the initial clock reference selected depends

on the condition of the SELCLK, SELBUN, and ENSQLN device signals and the status of the internal loss of clock detec-

tors for clock B and clock BU. If the user selects clock BU as the wanted reference, the state machine will check the status

of clock BU. If it is present, the device will switch to the back-up reference for the initial phase-lock. However, if the backup

reference is absent, the device will check the status of reference B, and if B is present, it will switch to reference B to initially

phase-lock to; and if the user selected clock B as the desired reference, the device would check the status of the reference

B loss of clock detector. If clock B is present, the device will switch to reference B for initial phase-lock, and if clock B is

absent, the device would check for clock BU.

BUB

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 45

If no reference is present and the ENSQLN signal is low, the device will select the reference desired as determined by the

SELCLK and SELBUN signals and will force the output clock and sync signals to a logic low level. Upon selecting a refer-

ence clock to initially lock to (defaults to reference A) and if the clock is present, the state machine initiates a time-out

period to allow the device to phase-lock to the selected reference clock. While waiting for the time-out period, the device

will activate the switch in progress interrupt, indicate if the selected reference agrees with the wanted reference on the con-

sistent interrupt, and output the selected reference on the SWSTATE signals.

After the initial start-up of the clock protection switch control circuit, the state machine will monitor the SELCLK and

SELBUN signals and the internal loss of clock flags. If the user initially wants a reference other than the one selected, the

state machine will check the status of the desired reference, and it will switch to the desired reference if it is present. This

will then initiate a new time-out period to allow the new reference to phase-lock. The circuit will prioritize clocks A and B

over clock BU such that if B is selected and disappears, A is checked first for switching before deciding to switch to clock

BU.

If the selected clock disappears, the state machine will autonomously switch to another reference that is present. If the

REVERTN signal is low, the state machine will automatically return to the originally selected reference after the time-out

period has expired. This could cause an oscillation between references, and to limit the length of this oscillation, the state

machine has a counter to count the number of transitions between references. If the ENLON signal is low, the state

machine will allow three transitions to occur before prohibiting further switching. To resume switching, the internal transition

counter is cleared by pulsing the LORSTN signal low. This allows external control of the time period monitored by the tran-

sition counter.

The nonautonomous mode is selected by forcing the AUTOSWN signal high or a no-connection on this signal. The start-up

condition causes the device to initially be selecting reference A. If A is absent, the device checks the reference desired (ref-

erence selected by SELCLK and SELBUN signals) for presence, and if it is present, the device immediately switches to this

reference. If the desired reference is absent, the device will look at the ENSQLN signal for direction. If ENSQLN is low, the

state machine will select the desired reference and squelch the output clock and sync signals, and if ENSQLN is high or not

connected, the state machine will remain in the state selecting reference A. If reference A is present, the state machine will

initiate the time-out period, and on the expiration of the time-out period, it will check for the presence of the desired clock. If

the desired clock is present, the device will switch to the desired clock and initiate another time-out period. If the desired

clock is absent, the state machine will remain in state A, and the state consistency interrupt will be active.

After the initial start-up of the device, the clock protection switch control circuit will monitor the SELCLK, SELBUN, and

ENSQLN signals and the loss of clock interrupts for changes. If the loss of clock interrupt on the currently selected refer-

ence goes active, the device will either do nothing or squelch the output clock and sync signals depending on the ENSQLN

condition. If ENSQLN is low, the device output clock and sync signals will be forced low. If the desired clock reference

changes and the time-out period has expired, the state machine will check the status of the desired reference loss of clock

interrupt. If the interrupt is low, the state machine will switch to the desired reference and initiate another time-out period.

Because there are times when a switch to a faulty (absent) reference is desired, the state machine has an override in the

form of the SWCONTN signal. Whenever the SWCONTN signal is low, all fault checking done prior to a switch is ignored;

i.e., the device will unconditionally switch to the reference desired on SELCLK and SELBUN. This override also allows the

user to squelch the output clock and sync signals manually by bringing the ENSQLN signal low.

There are three interrupts generated by the clock protection switch circuit: clock switch in progress, user-selected clock is

not consistent with the internal clock selection, and a lockout condition exists due to excessive number of switching events.

The clock switch in progress interrupt is active whenever a switching event occurs, and it will remain active until the time-

out period after the actual switch expires. The consistency interrupt is active whenever the internal clock selection dis-

agrees with the user desired selection. If a switch request comes from an external source through the SELCLK and SEL-

BUN signals before the internal time-out period has expired, then a consistency interrupt will be generated. This can be

prevented by monitoring the clock switch in progress interrupt. If the desired clock reference is absent, the consistency

interrupt will be generated, and if the state machine has locked out further switching events, the consistency interrupt will

be generated. The lock-out interrupt is generated whenever the number of switching events exceed three clock switches.

The time period for this count is controlled externally by the period between pulses on the LORSTN signal.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

4646 Agere Systems Inc.

15.3 Software Interfacing

The clock protection switching circuit is configured by an external controller via software. Whenever interaction with this

software is needed, the following guidelines should be followed:

■The software must provision the device as desired, appropriately setting SELCLK, SELBUN, AUTOSWN, REVERTN,

SWCONTN, ENSQLN, and ENLON upon powerup and after the initial reset completes.

■The external controller may either use an active edge of one of the interrupts or a polling method (monitoring

SWSTATE[1:0], INT[8:0]) to determine the input clock status and the occurrence of an autonomous switch.

■Whenever an autonomous switch occurs as indicated by the SWSTATE[1:0] flag, the software polls the INT[8:0] signals

to determine the cause of switching and validates the selection.

■Whenever a nonautonomous fault occurs as indicated by the INT[8:0] flag, the software polls the INT[8:0] signals and

selects the proper action to perform.

■After validation of an autonomous switch, the software must pulse AUTOSWN high and reinitialize the clock selection

inputs SELCLK and SELBU to match the SWSTATE[1:0] output signals.

If a lockout occurs, the software must pulse LORSTN low to clear the lockout.

15.4 Loss of Clock Criteria

Loss of clock detectors continuously monitor the condition of clock A, clock B, and CLKBU. A loss of clock condition is

declared when transitions are absent on the clock input for between 2 and 3 periods of the input frequency. This level is

programmable via register 0x23. The hysteresis for coming out of the loss of clock condition is also programmable in regis-

ter 0x2E.

15.5 Interrupt Generation (INT[8:0])

Interrupts are available on external balls INT[8:0] and via the serial interface in register 0xE0. Table 15-1 defines the condi-

tions under which interrupts are generated for the external balls INT[8:0]. All of these interrupts are available in register

0xE0 with the addition of another interrupt that indicates when squelch is active or inactive.

Interrupts 4 and 7 are not meant to be alarms, but more of a status report. INT4 indicates that a switch between any of the

clocks is occurring.

INT7 indicates to the user that the active clock is the not the clock that the user has selected. For example, in autonomous

mode, the default selected state is clock A (cannot be changed), so if clock A is not present and clock B or BU is the work-

ing clock, INT7 will be active. Another example is in manual mode with SWCONTN active (SWCONTN active prevents a

bad clock from be switched to). If the user selects a clock that is not present (and the original clock is still present), the

TSWC will not go to that clock; thus, the selected clock is not consistent with the internal clock selection state.

Table 15-1. Interrupt Generation (INT[8:0]) Active-High

INT Condition

8Lockout condition exists due to excessive number of switching events

7User-selected clock not consistent with internal clock selection state

6Loss of lock—high-speed PLL

5Loss of lock—38.88 MHz PLL

4Clock switch in progress

3Loss of external VCXO clock

2Loss of CLKBU

1Loss of CLKB

0Loss of CLKA

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 47

16 Serial Interface and Internal Bus

The TSWC’s internal registers can be programmed via a serial interface. This serial interface allows reading or writing any

of the registers. Internally, the TSWC uses two different lines to transmit and receive data from the outside. Those two lines

must be multiplexed by an input/output buffer to the single serial line (simplex communication). The serial line will be driven

by the external controller except when a read process is requested. In that case, the TSWC will drive the line during the

time it needs to transmit the requested data. During a period when no read nor write process is requested, SERDAT is

pulled internally to a CMOS logic high. As shown on Figure 16-1, there are three external pins related to the serial interface:

the serial interface clock SERCLK, the serial interface data line SERDAT, and the serial interface enable SERENBLN.

Figure 16-1. TSWC03622 Serial Interface

The serial interface frames are composed of 32 bits. The two first bits are used to indicate the beginning of the frame (01).

Then the address is transmitted in the next 8 bits, followed by 6 bits indicating if it is a read or write request. Finally, the

16 bits of data are transmitted by the external controller (write) or by the TSWC (read process). In case of a read process,

the last 17 bits of the frame are driven by the TSWC, following a bit where no device is driving the line, leaving it in high

impedance. As soon as the data has been transmitted, the external user continues to drive the line to a high logic state

waiting for the next frame to transmit. A representation of a WRITE is shown in Figure 16-2, and a READ, in Figure 16-3.

The transmission for both the data and address bits starts with the most significant bit.

Figure 16-2. Serial Interface WRITE Frame Format

EXTERNAL

CONTROLLER

INTERFACE

CONTROLLER

OUT

TSWC03622

SERDAT

SERCLK

SERENBLN

0 1 010010

SERDAT

SERCLK

SERENBLN

8-bit Address 16-bit Data

A7 A6 A5 A4 A3 A2 A0A1 D15 D14 D13 D12 D11 D10 D8D9 D7 D6 D5 D4 D3 D2 D0D10 1 010010

SERDAT

SERCLK

SERENBLN

8-bit Address 16-bit Data

A7 A6 A5 A4 A3 A2 A0A1 D15 D14 D13 D12 D11 D10 D8D9 D7 D6 D5 D4 D3 D2 D0D1

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

4848 Agere Systems Inc.

Figure 16-3. Serial Interface READ Frame Format

Timing for the serial interface is shown in Figure 16-4. During a read, the address and read request bits are clocked on a

rising edge, and the data that is clocked out (by the TSWC) transitions off the clock's rising edge. The signal coming from

the TSWC, that is interpreting this serial stream, should use the following falling edge to avoid a race condition.

Figure 16-4. Serial Interface Timing

Note: The maximum serial interface clock frequency is 25 MHz and the minimum clock period is 40 ns.

1 A7A6A5A4A3A2 A0A1 1000Z00

SERDAT

SERCLK

SERENBLN

8-bit Address 16-bit Data

Driven by External Controller Driven by TSWC01622

D15 D14 D13 D12 D11 D10 D8D9 D7 D6 D5 D4 D3 D2 D0D11 A7A6A5A4A3A2 A0A1 1000Z00

SERDAT

SERCLK

SERENBLN

8-bit Address 16-bit Data

Driven by External Controller Driven by TSWC01622

D15 D14 D13 D12 D11 D10 D8D9 D7 D6 D5 D4 D3 D2 D0D1

Note: These waveforms are not to scale.

T => 40 nS

T/2

DATA EYE

CLOCK

T => 40 ns

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 49

17 TSWC03622 Registers Map

Table 17-1 summarizes all the TSWC registers.

Table 17-1. TSWC03622 Registers

Address

Hex

TSWC03622 Block Description Bits Reset

00 Control Hardware reset for all TSWC03622 blocks. 15:8 0xFFFF

01 Control Software override. 0 0xFFFF

02—1F — Not used. — —

20 Clock Input Loss of clock block software override and reset. 1:0 0xFFFF

21 Clock Input FINSEL[3:0]. 3:0 0x000F

22 Clock Input FBUSEL[3:0]. 3:0 0x000F

23 Clock Input Loss of clock threshold. 15:0 0x0002

24 Clock Input For test purposes, set to 0x0002. 15:0 0x0002

25 Clock Input For test purposes, set to 0x0002. 15:0 0x0002

26 Clock Input For test purposes, set to 0x0002. 15:0 0x0002

27 Clock Input For test purposes, set to 0x0002. 15:0 0x0002

28 Clock Input For test purposes, set to 0x0003. 15:0 0x0003

29 Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2A Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2B Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2C Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2D Clock Input For test purposes, set to 0x0001. 15:0 0x0001

2E Clock Input Loss of clock hysteresis. 15:0 0x0004

2F — Not used. — —

30 Sw. State Mach Switch block control. 8:0 0xFFFF

31 Sw. State Mach Switch block state machine. 7:0 0x00FF

32 Sw. State Mach LOCNT—lock-out counter. 15:0 0x0003

33 Sw. State Mach TOCNT—time-out counter. 15:0 0x0800

34 Sw. State Mach IFREQ—divide by 19440 counter. 15:0 0x4BEF

35—3F — Not used. — —

40 PDH Outputs Programmable output variable R0 for channel 1. 9:0 0x0000

41 PDH Outputs Programmable output variable R1 for channel 1. 9:0 0x0000

42 PDH Outputs Programmable output variable R2 for channel 1. 9:0 0x0000

43 PDH Outputs Programmable output variable R3 for channel 1. 9:0 0x0000

44 PDH Outputs Programmable output variable R4 for channel 1. 9:0 0x0000

45 PDH Outputs Programmable output variable R5 for channel 1. 9:0 0x0000

46 PDH Outputs Programmable output variable R6 for channel 1. 2:0 0x0000

47 — Not used. — —

48 PDH Outputs Programmable output variable R0 for channel 2. 9:0 0x0000

49 PDH Outputs Programmable output variable R1 for channel 2. 9:0 0x0000

4A PDH Outputs Programmable output variable R2 for channel 2. 9:0 0x0000

4B PDH Outputs Programmable output variable R3 for channel 2. 9:0 0x0000

4C PDH Outputs Programmable output variable R4 for channel 2. 9:0 0x0000

4D PDH Outputs Programmable output variable R5 for channel 2. 9:0 0x0000

4E PDH Outputs Programmable output variable R6 for channel 2. 2:0 0x0000

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

5050 Agere Systems Inc.

4F — Not used. — —

50 PDH Outputs Programmable output variable R0 for channel 3. 9:0 0x0000

51 PDH Outputs Programmable output variable R1 for channel 3. 9:0 0x0000

52 PDH Outputs Programmable output variable R2 for channel 3. 9:0 0x0000

53 PDH Outputs Programmable output variable R3 for channel 3. 9:0 0x0000

54 PDH Outputs Programmable output variable R4 for channel 3. 9:0 0x0000

55 PDH Outputs Programmable output variable R5 for channel 3. 9:0 0x0000

56 PDH Outputs Programmable output variable R6 for channel 3. 2:0 0x0000

57 — Not used. — —

58 PDH Outputs Programmable output variable R0 for channel 4. 9:0 0x0000

59 PDH Outputs Programmable output variable R1 for channel 4. 9:0 0x0000

5A PDH Outputs Programmable output variable R2 for channel 4. 9:0 0x0000

5B PDH Outputs Programmable output variable R3 for channel 4. 9:0 0x0000

5C PDH Outputs Programmable output variable R4 for channel 4. 9:0 0x0000

5D PDH Outputs Programmable output variable R5 for channel 4. 9:0 0x0000

5E PDH Outputs Programmable output variable R6 for channel 4. 2:0 0x0000

5F — Not used. — —

60 PDH Outputs Programmable output variable R0 for channel 5. 9:0 0x0000

61 PDH Outputs Programmable output variable R1 for channel 5. 9:0 0x0000

62 PDH Outputs Programmable output variable R2 for channel 5. 9:0 0x0000

63 PDH Outputs Programmable output variable R3 for channel 5. 9:0 0x0000

64 PDH Outputs Programmable output variable R4 for channel 5. 9:0 0x0000

65 PDH Outputs Programmable output variable R5 for channel 5. 9:0 0x0000

66 PDH Outputs Programmable output variable R6 for channel 5. 2:0 0x0000

67—7F — Not used. — —

80 PDH Outputs PDH control register 1. 15:12, 0 0x0001

81 PDH Outputs PDH control register 2. 9:0 0x0000

82 PDH Outputs Enhanced software mode fractional divider selection, modes for

C0, C1, C2, and C3.

15:0 0x0000

83 PDH Outputs Enhanced software mode fractional divider selection, modes for

C4, C5, C6, and C7.

15:12 0x0000

84 PDH Outputs Reserved. — —

85 PDH Outputs Reserved. — —

86—9F — Not used. — —

A0 SDH/SYNC Outputs SDH/Sync control. 3:0 0x000F

A1 SDH/SYNC Outputs SDHSEL register. 3:0 0x0000

A2 SDH/SYNC Outputs Duty cycle register. 0 0x0001

A3 SDH/SYNC Outputs Sync offset and direction. 10:0 0x0000

A4 SDH/SYNC Outputs Sync enables. 11:0 0x0000

A5 SDH/SYNC Outputs Clock enables. 9:0 0x0000

A6 SDH/SYNC Outputs Individual duty cycle changes. 2:0 0x0007

A7 SDH/SYNC Outputs Clock edge selection. 3:0 0x000F

A8 SDH/SYNC Outputs Sync offset when software override. 15:0 0x0000

A9 SDH/SYNC Outputs Additional sync offset when software override. 1:0 0x0000

Table 17-1. TSWC03622 Registers (continued)

Address

Hex

TSWC03622 Block Description Bits Reset

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 51

17.1 Control Block Registers

AA—AF — Not used. — —

B0 SDH/SYNC Outputs RISE[15:0]. 15:0 0x2FC0

B1 SDH/SYNC Outputs RISE(16). 0 0x0001

B2 SDH/SYNC Outputs FALL. 15:0 0x97E0

B3 SDH/SYNC Outputs DELTA. 3:0 0x0016

B4 SDH/SYNC Outputs Not used. — 0x0016

B5 SDH/SYNC Outputs Not used. — 0x0016

B6 SDH/SYNC Outputs DELTARISE. 4:0 0x000B

B7 — Not used. — 0x0000

B8 SDH/SYNC Outputs For test purposes, read only. 0 0x0001

B9 SDH/SYNC Outputs For test purposes, read only. 15:0 0x2FAA

BA SDH/SYNC Outputs For test purposes, read only. 0 0x0000

BB SDH/SYNC Outputs For test purposes, read only. 15:0 0x97CA

BC—DF — Not used. — —

E0 Control Interrupt register. 8:0 0x0060

Table 17-2. Hardware Reset for All TSWC03622 Blocks

Address

(Hex)

Bit Name Description Reset

Value

0x00 15 RHSLOLN High-speed PLL powerdown.

1 = Block active.

0 = Block powered down.

14 RLOSCLKN Loss-of-clock block powerdown.

1 = Block active.

0 = Block powered down.

13 RSWSTATN Switch state machine powerdown.

1 = Block active.

0 = Block powered down.

12 RESETFFN Feed-forward counters powerdown.

1 = Block active.

0 = Block powered down.

11 RLSPLLN Low-speed PLL powerdown.

1 = Block active.

0 = Block powered down.

10 RSYNCN SDH/sync generation block powerdown.

1 = Block active.

0 = Block powered down.

9 RPDHCLKN PDH block powerdown.

1 = Block active.

0 = Block powered down.

8 RCONFIGN Control block reset.

1 = Block active.

0 = Block reset for one 155.52 MHz clock cycle.

7:0 — Unused: program to one. 00000000

Table 17-1. TSWC03622 Registers (continued)

Address

Hex

TSWC03622 Block Description Bits Reset

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

5252 Agere Systems Inc.

Register 00h contains power downs for all the TSWC blocks. Setting a bit to a low level in this register will power down the

corresponding block. The block will remain powered down until the bit is again set to high, except for bit 00h(8), which

resets the control block only for one 155 MHz clock cycle. This register is initialized to all zeros, and bits 00h[7:0] are not

used. The reset register can be written at any time to reset a specific block, although the software reset implemented in

each block can also be used. After a general hardware reset, the control block will be setting the reset register bits to high

level following a certain reset sequence. If a block is powered down and it is desired to power it up, a hardware reset is nec-

essary.

Register 01h contains the software override bit, which must be set to low prior to any write operation. If bit 01h(0) is high,

the control block will not write any register except for 01h itself. This register is initialized to all ones, although bits 01h[15:1]

are not used, so right after initialization no write process is allowed. Bit 01h(0) must be set low.

17.2 Input Clock Block Registers

The loss of clock block monitors the input clocks CLKA, CLKB, and CLKBU, and the 38.88 MHz clock generated by the

external VCXO.

are active-low level, so register 20h is initialized to all ones. If bit 20h(1) is low, the input clock block will be operating in soft-

ware mode, enabling all the programming capabilities and allowing access to the full flexibility of the block.

Table 17-3. Software Override

Address

(Hex)

Bit Name Description Reset

0x01 15:1 — Unused: program to one. 111111111111111

0 OVERRIDE Software override bit.

1 = Software programming disabled (hardware mode).

0 = Software programming enabled (software mode).

Table 17-4. Loss of Clock Block Software Override and Reset

Address

(Hex)

Bit Name Description Reset

20 15:2 — Unused: program to one. 11111111111111

1 SWOVRDN Reserved. 1

0 SWRSTN Input clock block powerdown.

1 = Block active.

0 = Block powered down.

Table 17-5. FINSEL[3:0] Register

Address

(Hex)

Bit Name Description Reset

21 15:4 — Unused: program to one. 111111111111

3:0 FINSEL[3:0] Clock A and clock B input frequency select.

(Bit 3 is a don’t care.)

1111, 0111 = 51.84 MHz.

1110, 0110 = 38.88 MHz.

1101, 0101 = 19.44 MHz.

1100, 0100 = 8.192 MHz.

1011, 0011 = 6.480 MHz.

1010, 0010 = 2.048 MHz.

1001, 0001 = 1.544 MHz.

1000, 0000 = 8 kHz.

1111

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 53

must indicate the input clocks frequency (FINSEL for CLKA and CLKB). This register is initialized to all ones. It can be writ-

ten at any time via serial interface (even in hardware mode), but only in hardware mode will any change in these registers

reprogram the fractional dividers by rewriting registers 24h—2Dh.

must indicate the input clocks frequency (FBUSEL for CLKBU). This register is initialized to all ones. It can be written at any

time via serial interface (even in hardware mode), but only in hardware mode will any change in these registers reprogram

the fractional dividers by rewriting registers 24h—2Dh.

Register 23h is used to program the threshold time; that is, the number of absent input cycles needed to raise the loss of

clock interrupt. This values is shared by all the loss of clock detectors. The minimum value for this register is a value of 2. If

a lower value is written, the threshold will be set to a values of 2.

Register 2Eh is used to program the hysteresis time; that is, the number of input clock cycles needed to erase the loss of

clock flag once the clock is back. This values is shared by all the loss of clock detectors. The minimum value for this regis-

ter is a value of 4. If a lower value is written, the hysteresis will be set to a values of 4.

Table 17-6. FBUSEL[3:0] Register

Address

(Hex)

Bit Name Description Reset

22 15:4 — Unused: program to one. 111111111111

3:0 FBUSEL[3:0] Backup clock input frequency select.

(Bit 3 is a don’t care.)

CLKBU functions at a clock rate of 8 kHz. If a different

backup clock rate is required, please contact the Agere

Systems representative.

1000, 0000 = 8 kHz.

1111

Table 17-7. Loss of Clock Threshold

Address

(Hex)

Bit Name Description Reset

23 15:0 THRESHOLD Loss of clock threshold value (number of missing consecu-

tive clock cycles needed to trigger loss of clock interrupt).

0000000000000010

Table 17-8. Loss of Clock Hysteresis

Address

(Hex)

Bit Name Description Reset

2E 15:0 HYSTERESIS Loss of clock hysteresis value (number of consecutive clock

cycles needed to erase loss of clock interrupt, once clock is

back).

0000000000000100

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

5454 Agere Systems Inc.

17.3 Switch State Machine Block Registers

The address space for the clock protection switch control circuit is 30h-34h.

Bits 30h[8:3] are used for test purposes, and they must be high in normal operation mode, specially bit 30h(3), which is the

test mode bit.

Table 17-9. Switch Block Control Register

Address

(Hex)

Bit Name Description Reset

30 15:9 — Unused: program to ones. 1111111

8 LOCBUN For test purposes, set to 1. 1

7 LOCBN For test purposes, set to 1. 1

6 LOCAN For test purposes, set to 1. 1

5 BUSYBN For test purposes, set to 1. 1

4 BUSYAN For test purposes, set to 1. 1

3 TESTN For test purposes, set to 1. 1

2 Reserved — 1

1 SWOVRDN Software override bit.

1 = Hardware mode (registers 32, 33, and 34 use their default values).

0 = Software mode (user can overwrite registers 32, 33, and 34).

0 SWRSTN Switch block software powerdown.

1 = Block active.

0 = Switch control circuits powered down except for microprocessor interface.

Table 17-10. Switch Block State Machine Register

Address

(Hex)

Bit Name Description Reset

31 15:8 — Unused. 00000000

7 ENSQLN Squelch enable.

1 = Squelch disabled.

0 = Squelch enabled (squelch active conditions are listed in Table 17-11).

6 LORSTN Lockout reset.

1 = Counting switching events if 31h(5) = 0.

0 = Reset.

5 ENLON Enable lockout.

1 = Lockout disabled.

0 = Lockout enabled.

4 SWCONTN Protection switch control circuit operation mode.

111 = Protected manual mode (SELCLK/SELBUN selects clock. User cannot

switch to a bad clock).

110 = Autonomous nonrevertive mode.

100 = Autonomous revertive mode.

0xx = Unprotected manual mode (SELCLK/SELBUN selects clock. User can

switch to a bad clock.)

3 REVERTN 1

2AUTOSWN 1

1 SELBUN Input clock selection.

11: Clock A.

10: Clock B.

0x: Backup clock.

0SELCLK 1

Conditions for use of this register: 01h(0) = 0.

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 55

Register 31h is initialized to all ones. Positions [15:8] will always read as zeros. This register is updated by the TSWC con-

trol block based on the input pins state, although they can also be modified via serial interface. This register will therefore

reflect the input pins with the same name given that the TSWC control block updates register 31h via internal bus. The

TSWC03622 will use the respective external balls for control when register 01h bit 0 is high, and it will use the configuration

from register 31h when register 01h bit 0 is low. All bits in register 31h are active-low.

Bit 31h(5) is the lock-out enable ENLON, and bit 31h(6) is the lock-out reset LORSTN. If ENLON is low, the lock-out is

enabled, so only a certain number of switches are allowed (only in autonomous mode), as indicated by register 32h. Once

that limit has been reached, no more switches are allowed. The lock-out only works in autonomous mode of operation; in

protected or unprotected manual mode, unlimited number of clock switches are allowed no matter what the value of

ENLON is. In autonomous mode, if the number of switches reaches the limit and the device is locked out, the lock-out

count can be reset by setting bit LORSTN low, allowing new clock switches before the device is locked out again. If ENLON

is high, the device will never be locked out, and unlimited number of clock switches in autonomous mode will be allowed.

Bit 31h(7) is the squelch enable ENSQLN. Setting this bit low, the SDH and PDH output clocks will be squelched if one of

the next conditions are met.

As indicated in the previous table, when operating in external control mode, the squelch enable is used to squelch the out-

put clocks, whereas for the other operation modes the squelch enable allows squelching when the special conditions are

met.

This register indicates the maximum number of clock switches that are allowed before the circuit is locked out (autonomous

mode only). In order to write this register, bit 30h(1) must be set low previously. Whenever bit 30h(1) is high, register 32h

will take the default value, which is the same as initialization. That value is 0000000000000011 (three). That means that in

default mode, only three switches are allowed. At the third clock switch, the lock-out flag is risen and any extra clock switch

will be prohibited. If bit 30h(1) is low, register 32h can be written with a value ranging from zero to 65535.

In order to enable the lock out feature, the enable bit 31h(5) must be set low (ENLON) and the reset bit 31h(6) must be set

high (LORSTN), although the device can only be locked out in autonomous mode (AUTOSWN = 0, SWCONTN = 1).

Despite that the lock-out is only effective in autonomous mode, the lock-out counter keeps count of the number of clock

switches in any mode of operation. This means that if the circuit is being used in manual mode and several switches have

been made so that the limit has been reached, and the circuit is switched to autonomous mode, no clock switch will be

allowed, since the circuit will be locked out. A software reset is suggested when switching the circuit to a different mode of

operation.

Setting the lock out reset low (LORSTN = 0) or bit 31h(5) high (ENLON = 1) will disable the lock out feature.

Table 17-11. Squelch

Mode of Operation Conditions Needed to Squelch the Output Clocks when ENSQLN = 0

Autonomous (revertive or nonrevertive) The output clocks will be squelched if the three input clocks CLKA, CLKB, and

CLKBU are lost.

(LOCA = 1 and LOCB = 1 and LOCBU = 1.)

Protected Manual Mode The output clocks will be squelched if one of the next three conditions are met:

■Clock A is being used as reference, but it is lost (LOCA = 1).

■Clock B is being used as reference, but it is lost (LOCB = 1).

■Clock BU is being used as reference, but it is lost (LOCBU = 1).

Unprotected Manual Mode The output clocks will be squelched always if ENSQLN is low, no matter what

the conditions of the input clocks are.

Table 17-12. Lockout Threshold

Address

(Hex)

Bit Name Description Reset

32 15:0 LOCNT Maximum number of clock switches allowed before the

TSWC03622 enter lockout (autonomous mode only).

0000000000000011

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

5656 Agere Systems Inc.

These registers are used to program the time-out feature used to avoid any clock switch before a certain time after the last

clock switch, unless a fault in the current reference requires a clock switch. The time-out period is needed by the LSPLL to

lock to the new reference clock after a clock switch, and is active in manual and automatic mode.

In order to write registers 33h and 34h, bit 30h(1) must be low. Whenever bit 30h(1) is high, registers 33h and 34h will be

loaded with the default value, which is the same as at initialization, that is, 2047 for 33h and 19440 for 34h.

last clock switch. That clock will be obtained by dividing the 155.52 MHz clock by the number indicated in register 34h. The

default value of register 34h is 19439, which gives an internal clock frequency of 8 kHz (155.52 MHz/19440 = 8 kHz).

Register 33h indicates the number of internal clock cycles of the time-out period. After a clock switch, an internal counter

will be initialized with the value indicated by register 33h, and will start to down-count each internal clock edge (whose fre-

quency can be programmed by register 34h). The time-out period will be expired when that counter reaches zero. The

default value of this register is 2048.

The phase of the internal clock used to measure the time-out period is independent on when the clock switch occurs, so the

actual time-out period is between the number indicated by register 33h and the number indicated by register 33h plus one.

Calling R33 the number indicated by register 33h and R34 the number indicated by register 34h, the time-out period τ will

take the next value (in seconds):

R34/155520000 x (R33–1) < < R34/155520000 x R33

For the default value, the time out period will be limited by:

255.75 ms < < 255.875 ms

In order to reduce the possible range for the time-out period, it is suggested to increase R33 as much as possible keeping

the product of R33 and R34 constant (that means a high frequency for the internal clock). For example, the next range

would be obtained for R33 = 32752 and R4 = 1215; the time-out period would be in the range from 255.867 ms to

255.875 ms.

It is also suggested to software reset the circuit before registers 33h and 34h are written.

17.4 PDH Output Block Registers

17.4.1 Fractional Dividers Registers, 40h—66h

The PDH fractional dividers enable each of the five PDH CMOS output clocks to be fully programmable. Registers

40h—66h contain the parameters to set the respective frequencies. Setting the frequencies is enable in registers

80h—83h.

Each fractional divider includes seven registers. Those registers are located at consecutive addresses. The address of

each register can be specified by the base address of the corresponding fractional divider and the relative offset.

Base address

Fractional Divider 1 40h

Fractional Divider 2 48h

Fractional Divider 3 50h

Fractional Divider 4 58h

Fractional Divider 5 60h

Table 17-13. Switch Time-Out Settings

Address

(Hex)

Bit Name Description Reset

33 15:0 TOCNT Time-out counter: indicates the number of internal clock cycles

of the time out period.

0000011111111111

34 15:0 IFREQ Programs the period of an internal clock, which is used to

measure the time elapsed since the last clock switch.

0100101111110000

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 57

To calculate the values for the respective dividers, a software program is available to automate the process. Please contact

your Agere Systems representative to get a copy of the program.

All registers are initialized to all zero at reset.

17.4.2 General Configuration Registers, 80h—83h

Registers 80h—83h are the general configuration registers that control the operation mode of the PDH block. The first two

registers 80h and 81h, control the general behavior of the PDH block, whereas registers 82h and 83h control the five frac-

tional dividers used to generate the PDH rates.

Register 80h contains the software reset bit 80h(0) and the four PDHSEL[3:0] bits, used to select one of the sixteen preset

configurations when 81h[4:3] = 10 (basic software control), generating the most needed PDH rates. Bit 80h(0) is the soft-

ware reset, used to power down the PDH block except for the microprocessor used to read and write registers. The micro-

processor can only be reset by hardware reset. Register 80h is initialized with all bits low except for 80h(0), which is high.

Bits [10:1] can written and read as they were written, but they are not used by the PDH block.

Table 17-14. PDH Control Register 1

Address

(Hex)

Bit Name Description Reset

80 15:12 PDHSEL Software PDH output clock select. See Table 17-15 for preset configura-

tions. To use this register, 81h(4:3) must be set to 10.

0000

11:1 — Reserved. 00000000000

0 SWRSTN PDH block software powerdown.

1 = Block active.

0 = PDH output block powered down except for microprocessor interface.

Table 17-15. PDH Clock Outputs for the 16 Preset Configurations (Bit 81h(3) = 0)

PDHSEL Clock 1 Clock 2 Clock 3 Clock 4 Clock 5

0000 Disabled

0001 44.736 MHz Disabled

0010 34.368 MHz Disabled

0011 Disabled 32.768 MHz Disabled

0100 24.704 MHz Disabled

0101 Disabled 16.384 MHz Disabled

0110 Disabled 8.192 MHz Disabled

0111 Disabled 4.096 MHz Disabled

1000 Disabled 2.43 MHz

1001 Disabled 2.048 MHz Disabled

1010 Disabled 1.544 MHz Disabled

1011 Disabled 2.048 MHz 1.544 MHz Disabled

1100 44.736 MHz 32.768 MHz 24.704 MHz 2.048 MHz 1.544 MHz

1101 34.368 MHz 32.768 MHz 24.704 MHz 2.048 MHz 1.544 MHz

1110 Disabled

1111 44.736 MHz 32.768 MHz 2.048 MHz 1.544 MHz 2.43 MHz

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

5858 Agere Systems Inc.

Registers 82h and 83h indicate the operation mode of each fractional divider when bit 81h(3) is high. There are 4 bits for

each fractional divider. These registers are reset to all zeros. Each fractional divider can be operated in sixteen different

modes. These modes are described in Table 17-18.

Table 17-16. PDH Control Register 2

Address

(Hex)

Bit Name Description Reset

81 15:10 — Reserved. 000000

9:8 DIV2N For Test Purposes Only. Program to 00. 00

7:5 CKMXSEL For Test Purposes Only. Program to 000. 000

4:3 MODESEL 00—Hardware Control. This mode allows to control the PDH block through

the external PDHSEL[3:0] pins in case the TSWC control block fails. These

pins reach the PDH block, so the PDH block behavior is independent of the

TSWC control block. This mode offers sixteen presets, which generate the

most needed PDH frequencies. Every one of those configurations programs

each fractional divider to work in one of the sixteen modes listed in

Table 17-18.

10—Basic Software Control. This mode is intended to be used in conjunc-

tion with the TSWC control block. The PDH block operates in the same way as

in hardware control offering the same sixteen presets, but this time instead of

reading the external pins directly, the four PDHSEL[3:0] bits are read from reg-

ister 80h (four most significant bits). This register is written by the control block

at initialization or when any change is made on the external pins, as the con-

trol block monitors the external pins in a continuous basis. Register 80h can

also be written via serial interface (software override).

X1—Enhanced Software Control. This mode can only be used by program-

ming the PDH block via serial interface. This third alternative allows individual

selection of the operating mode for each fractional divider. Registers 82h and

83h contain the 20 bits needed to specify the operating mode for each of the

five fractional dividers (4 bits per fractional divider).

2:0 DELAY For Test Purpose Only. Program to 00. 000

Table 17-17. Enhanced Software Mode Fractional Divider Selection

Address

(Hex)

Bit Name Description Reset

82 15:12 FD 1 Mode PDH1 fractional divider mode, see text below and Table 17-18 to program

value.

0000

11:8 FD 2 Mode PDH2 fractional divider mode, see text below and Table 17-18 to program

value.

0000

7:4 FD 3 Mode PDH3 fractional divider mode, see text below and Table 17-18 to program

value.

0000

3:0 FD 4 Mode PDH4 fractional divider mode, see text below and Table 17-18 to program

value.

0000

83 15:12 FD 5 Mode PDH5 fractional divider mode, see text below and Table 17-18to program

value.

0000

11:0 — Reserved. 000000000000

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 59

In mode 14, the fractional divider can be programmed through the registers located inside the fractional divider (see Sec-

tion 17.4.1, Fractional Dividers Registers, 40h—66h, on page 56).

Fractional dividers one through three use the 622.08 MHz clock as input, whereas fractional dividers four and five use the

155.52 MHz clock. Based on the previous table, the input frequency to each fractional divider, and the division factor indi-

cated in Table 17-19, the sixteen presets will generate the output clocks (each clock is generated by the fractional divider

with the same number) shown in Table 17-15.

Table 17-18. Software Mode Fractional Divider Selection

Mode Mode Bits [3:0] Divides By

0 0000 13 + 211/233

1 0001 18 + 18/179

2 0010 18 + 63/64

3 0011 25 + 35/193

4 0100 37 + 31/32

5 0101 75 + 15/16

6 0110 100 + 140/193

7 0111 64

8 1000 151 + 7/8

9 1001 303 + 3/4

10 1010 256

11 1011 402 + 174/193

12 1100 32

13 1101 Reserved

14 1110 Programmable

15 1111 Power down

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

6060 Agere Systems Inc.

Table 17-19 summarizes the operation mode for the five fractional dividers when bit 80h(3) is low. In that case, the PDH

block offers sixteen preset configurations that can be selected by the external pins (when 81h(4) = 0) or writing register 80h

(when 81h(4) = 1).

Table 17-19. Fractional Dividers Operation Mode

Table 17-19 shows the fractional dividers as a function of the external pins PDHSEL[3:0] or bits 80h[15:12] (bit 81h(3) must

be low.

PDHSEL[3:0] or Bits 80h[15:12] FD 1 FD 2 FD 3 FD 4 FD 5

0000 1515151515

0001 0 15 15 15 15

0010 1 15 15 15 15

0011 15 2 151515

0100 3 15 15 15 15

0101 15 4 151515

0110 15 5 151515

0111 15 15 8 15 15

1000 15151515 7

1001 1515 9 1515

1010 15 15 15 6 15

1011 15 15 9 6 15

1100 02356

1101 12356

1110 1515151515

1111 02967

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 61

17.5 SDH/Sync Generation Block Registers

Table 17-20. SDH/Sync Control Register

Bit 0 is the software reset used to reset the SDH/Sync block.

Bits 1, 2, and 3 are overrides (active-low level). When the SDH_HW pin is high, the values used as SDHSEL, DUTY, and

SYNCOFFSET are read from the external pins. When that pin is low, those values will be set via serial interface. If bits 1, 2,

and 3 are high, the values will be read from the same registers as if the TSWC was in pin control; that is, SDHSEL is stored

in register A1h, DUTY is in register A2h, and SYNCOFFSET is in register A3h.

When bit A0h(1) is low (SDH_HW = 0), the enables for the output clocks will be taken from register A5, which is a bit-to-

enable register.

If bit A0h(2) is low (SDH_HW = 0), the duty cycle is specified by register A6h, which allows different duty cycles for the

three kinds of output syncs.

Setting bit A0h(3) to a low level and SDH_HW = 0 allows the user to specify the offset in the output sync with registers A8h

and A9h. Those registers give a wider range to position the output sync than the external pins or register A3h. By using

these registers, the user may be able to place the output sync in any position of the 8 kHz cycle.

Address

(Hex)

Bit Name Description Reset

A0 15:4 — Reserved. 000000000000

3 SYNC OFFSET OVERRIDE Sync offset override.

1 = Sync offset read from register A3h.

0 = Sync offset read from registers A8h and A9h (which

has a wider range than external pins, covering a com-

plete 8 kHz cycle).

Conditions for use of this feature: SDH_HW pin low.

2 DUTY CYCLE OVERRIDE Duty cycle override.

1 = Duty cycle read from register A2h.

0 = Duty cycle read from A6h (which allows for different

duty cycles for the three kinds of output syncs).

Conditions for use of this feature: SDH_HW pin low.

1 SDHSEL OVERRIDE SDHSEL override.

1 = Output clocks enables read from SDHSEL, read from

0 = Output clocks enables read from register A5h.

Conditions for use of this feature: SDH_HW pin low.

0 SRESETN SDH/Sync block software powerdown.

1 = Active.

0 = Powered Down except for microprocessor interface.

Conditions for use of this feature: SDH_HW pin low.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

6262 Agere Systems Inc.

This is the SDHSEL[3:0] register used to select one of the 16 presets when the SDH_HW pin is low and bit A0h(1) is high

(basic software enables configuration). Each of the 16 presets controls the clock and sync enables as the SDHSEL[3:0]

external pins do when the SDH_HW pin is high. This register is initialized at 0000, selecting the preset number zero, which

disables all clock and sync outputs.

Register A2h is the duty cycle register, where bit A2h(0) is the duty cycle bit. That bit is used to select the duty cycle of the

output syncs only when the SDH_HW pin is low and the duty cycle override bit A0h(2) is high (basic software duty cycle

configuration). It works as the external pin SYDU when pin SDH_HW is high. If the duty cycle bit is high, the duty cycle of

all output syncs will be 50%, although it can be programmed to take a different value through the algorithm control registers

B0h, B1h, and B2h. If the duty cycle bit is zero, each output sync will have the default pulse width, depending on the

selected sync for each output.

The duty cycle bit is initialized to one, so the output syncs will have 50% duty cycle.

Table 17-21. SDHSEL Register

Address

(Hex)

Bit Name Description Reset

A1 15:4 — Reserved. 000000000000

3:0 SDHSEL SDH clock and sync selection.

See SDH output clock selection (SDHSEL[3:0]) in data sheet.

Conditions for use of this feature: A0h(1) = 1 and SDH_HW

pin low.

0000

Table 17-22. Sync Duty Cycle

Address

(Hex)

Bit Name Description Reset

A2 15:1 — Reserved. 000000000000000

0 Duty Cycle Sync duty cycle.

1 = 50%.

0 = Pulse width per Table 17-23.

Conditions for use of this feature: A0h(2) = 1 and SDH_HW pin low.

Table 17-23. Output Sync Duty Cycle

Sync Output Pulse Width

PECL0/PECL1, LVDS0/LVDS1 One cycle of the 155 MHz or 622 MHz clock.

CMOS One cycle of the 77.76 MHz, 51.84 MHz, 38.88 MHz, or 19.44 MHz.

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 63

This is the sync offset and direction register used in the same way as the external pins SYOFF[9:0] and SYOFFPOS. This

A3h[9:0] are the sync offset, and bit A3h(10) is the direction. In order to get a positive delay, that is, to delay the output sync

with respect to the negative edge of the input sync, bit A3h(10) must be high. Register A3h is reset to all zero.

Table 17-24. Sync Offset

Address

(Hex)

Bit Name Description Reset

A3 15:11 — Reserved. 00000

10 SYOFFPOS Positive of negative offset bit.

1 = Positive.

0 = Negative.

Conditions for use of this feature: A0h(3)=1 and SDH_HW pin low.

9:0 SYOFF Sync offset.

Value of this offset indicates number of 1/622.08 (~1.6) ns increments.

Conditions for use of this feature: A0h(3) = 1 and SDH_HW pin low.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

6464 Agere Systems Inc.

* In Version 1.0 and 1.1 of the TSWC03622, there is an errata with bit 11 of register A4h. This register can be written, but does not respond correctly to a

read. When this bit is read, it will return a 0, regardless of the true value in the register.

This register is used with register A5h for enhanced software enables configuration; that means that it will only be used

when the SDH_HW pin is low and bit A0h(1) is low (override enables). It controls the output sync enables, so it selects the

output sync pulse width when the duty cycle bit is low (not 50%). This register is initialized to zero.

Table 17-25. Sync Source

Address

(Hex)

Bit Name Description Reset

A4 15:12 — Reserved. 0000

11* SYPCL6221 LVPECL Sync Enable.

These registers [11:8] control the enables and sources of the LVPECL syncs. Bits

10 and 8 control SYPCLP/N[0], and bits 11 and 9 control SYPCLP/N[1] as follows:

SYPCLP/N[0]

X0X0 = Disabled.

X0X1 = Enabled, pulse width based on SYNC155, as defined in A6h(1).

X1X0 = Enabled, pulse width based on SYNC622, as defined in A6h(0).

X1X1 = Disabled.

SYPCLP/N[0]

0X0X = Disabled.

0X1X = Enabled, pulse width based on SYNC155, as defined in A6h(1).

1X0X = Enabled, pulse width based on SYNC622, as defined in A6h(0).

1X1X = SYPCLP/N[1] disabled.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

10 SYPCL6220 0

9 SYPCL1551 0

8 SYPCL1550 0

7SYNC8K78

CMOS Sync Enable. These registers [7:4] control the enable and source of the

CMOS Sync. The pulse width is based on A6h(2).

If A6h(2) is high, the pulse width is based on the configuration below.

0001, 0010, 0100, or 1000: pulse width is 50% of sync period.

other = Disabled.

If A6h(2) is low, the pulse width is based on the configuration below.

0001 = One cycle of the 19.44 MHz clock.

0010 = One cycle of the 38.88 MHz clock.

0100 = One cycle of the 51.84 MHz clock.

1000 = One cycle of the 77.76 MHz clock.

other = Disabled.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

6SYNC8K51 0

5SYNC8K38 0

4SYNC8K19 0

3 SYLVS6221 LVDS Sync Enable.

These registers [3:0] control the enables and sources of the LVDS syncs. Bits 2 and

0 control SYLVSP/N[0], and bits 3 and 1 control SYLVSP/N[1] as follows:

SYLVSP/N[0]

X0X0 = Disabled.

X0X1 = Enabled, pulse width based on SYNC155, as defined in A6h(1).

X1X0 = Enabled, pulse width based on SYNC622, as defined in A6h(0).

X1X1 = Disabled.

SYLVSP/N[1]

0X0X = Disabled.

0X1X = Enabled, pulse width based on SYNC155, as defined in A6h(1).

1X0X = Enabled. pulse width based on SYNC622, as defined in A6h(0).

1X1X = Disabled.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

2 SYLVS6220 0

1 SYLVS1551 0

0 SYLVS1550 0

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 65

This register controls the individual SDH clock enables when the SDH_HW pin is low and bit A0h(1) = 0 (enhanced soft-

ware enables configuration). A low zero means that the corresponding output clock will be disabled.

Recall that regarding the 155.52 MHz and 622.08 MHz clocks, only the enable signals are generated by the SDH block.

The clocks are generated by other circuits external to the SDH block. Register A5h is initialized to zero (all clocks disabled).

When A0h[2] is low, the sync outputs (SYNC8K, SYPCL[1:0], and SYLVS[0:1]) duty cycles will be programmed from regis-

ters A4h and A6h. In register A6h, if any of the used bits are set low, then the pulse widths for the selected syncs will be set

by the respective control in register A4h. If a respective sync output is programmed to have a duty cycle less then 50% per

the previous conditions, then the clock outputs per Table 17-27 through Table 17-29 will be active, regardless of the clock

enable status in register A5h.

Table 17-26. SONET/SDH Clock Enable

Address

(Hex)

Bit Name Description Reset

A5 15:10 — Reserved. 000000

9 PECL622 Enable for the 622.08 MHz PECL differential output (PECL622).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

8 PECL1551 Enable for the 155.52 MHz PECL differential output (PECL1551).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

7 PECL1550 Enable for the 155.52 MHz PECL differential output (PECL1550).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

6 CK78 Enable for the 77.76 MHz single-ended CMOS output.

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

5 CK51 Enable for the 51.84 MHz single-ended CMOS output.

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

4 CK38 Enable for the 38.88 MHz single-ended CMOS output.

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

3 CK19 Enable for the 19.44 MHz single-ended CMOS output.

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

2 LVDS622 Enable for the 622.08 MHz LVDS differential output (LVDS622).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

1 LVDS1551 Enable for the 155.52 MHz LVDS differential output (LVDS1551).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

0 LVDS1550 Enable for the 155.52 MHz LVDS differential output (LVDS1550).

1 = Enabled, 0 = Disabled.

Conditions for use of this feature: A0h(1) = 0 and SDH_HW pin low.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

6666 Agere Systems Inc.

17.6 LVPECL Output Syncs and Clocks

17.7 CMOS Output Syncs and Clocks

Table 17-27. LVPECL Output Clock Status When Influenced by Programmable Duty Cycle on Syncs

Setting in

Hex

Setting in Binary PCK155P/N0 PCK155P/N1 PCK622P/N

Bit 11 Bit 10 Bit 9 Bit 8

0 0 0 0 0 Set by A5h[7] Set by A5h[8] Set by A5h[8]

1 0 0 0 1 Active Set by A5h[8] Set by A5h[8]

2 0 0 1 0 Set by A5h[7] Active Set by A5h[8]

3 0 0 1 1 Active Active Set by A5h[8]

4 0 1 0 0 Set by A5h[7] Set by A5h[8] Active

5 0 1 0 1 Active Set by A5h[8] Active

6 0 1 1 0 Set by A5h[7] Active Active

7 0 1 1 1 Active Active Active

8 1 0 0 0 Set by A5h[7] Set by A5h[8] Active

9 1 0 0 1 Active Set by A5h[8] Active

A 1 0 1 0 Set by A5h[7] Active Active

B 1 0 1 1 Active Active Active

C 1 1 0 0 Set by A5h[7] Set by A5h[8] Active

D 1 1 0 1 Active Set by A5h[8] Active

E 1 1 1 0 Set by A5h[7] Active Active

F 1 1 1 1 Active Active Active

Table 17-28. LVPECL Output Clock Status When Influenced by Programmable Duty Cycle on Syncs

Setting

in Hex

Setting in Binary CK19 CK38 CK51 CK77

Bit 7 Bit 6 Bit 5 Bit 4

0 0 0 0 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

1 0 0 0 1 Active Set by A5h[4] Set by A5h[5] Set by A5h[6]

2 0 0 1 0 Set by A5h[3] Active Set by A5h[5] Set by A5h[6]

3 0 0 1 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

4 0 1 0 0 Set by A5h[3] Set by A5h[4] Active Set by A5h[6]

5 0 1 0 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

6 0 1 1 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

7 0 1 1 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

8 1 0 0 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Active

9 1 0 0 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

A 1 0 1 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

B 1 0 1 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

C 1 1 0 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

D 1 1 0 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

E 1 1 1 0 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

F 1 1 1 1 Set by A5h[3] Set by A5h[4] Set by A5h[5] Set by A5h[6]

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 67

17.8 LVDS Output Syncs and Clocks

This register is used to control the individual syncs duty cycle when the SDH_HW pin is low and bit A0h(2) = 0 (enhanced

software duty cycle configuration). Only the three least significant bits are used, since there are only three types of output

syncs (SYC155, SYNC622, and CMOS). A high duty cycle bit selects the duty cycle of the corresponding sync to be 50%.

If the bit is low, the sync pulse width will be equal to one 622.08 MHz clock cycle for SYNC622 and one 155.52 MHz clock

cycle for SYNC155; and for the CMOS sync, the pulse width can be programmed to be one clock cycle of the 77.76 MHz,

51.84 MHz, 38.88 MHz, or 19.44 MHz clock. Register A6 is initialized to 111, that is, all 50% duty cycle.

Table 17-29. LVDS Output Clock Status When Influenced by Programmable Duty Cycle on Syncs

Setting in

Hex

Setting in Binary CK155P/N0 CK155P/N1 CK622P/N

Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 Set by A5h[0] Set by A5h[1] Set by A5h[2]

1 0 0 0 1 Active Set by A5h[1] Set by A5h[2]

2 0 0 1 0 Set by A5h[0] Active Set by A5h[2]

3 0 0 1 1 Active Active Set by A5h[2]

4 0 1 0 0 Set by A5h[0] Set by A5h[1] Active

5 0 1 0 1 Active Set by A5h[1] Active

6 0 1 1 0 Set by A5h[0] Active Active

7 0 1 1 1 Active Active Active

8 1 0 0 0 Set by A5h[0] Set by A5h[1] Active

9 1 0 0 1 Active Set by A5h[1] Active

A 1 0 1 0 Set by A5h[0] Active Active

B 1 0 1 1 Active Active Active

C 1 1 0 0 Set by A5h[0] Set by A5h[1] Active

D 1 1 0 1 Active Set by A5h[1] Active

E 1 1 1 0 Set by A5h[0] Active Active

F 1 1 1 1 Active Active Active

Table 17-30. Sync Duty Cycle

Address

(Hex)

Bit Name Description Reset

A6 15:3 — Reserved. 0000000000000

2 DUTY CYCLE

SYNCCMOS

Set duty cycle for the CMOS sync.

1 = 50%.

0 = Pulse width as set by A4h(7:4).

Conditions for use of this feature: A0h(2) = 0 and

SDH_HW pin low.

1 DUTY CYCLE SYNC155 Set Duty Cycle for the SYNC155.

1 = 50%

0 = One 155.52 MHz clock cycle

Conditions for use of this feature: A0h(2) = 0 and

SDH_HW pin low.

0 DUTY CYCLE SYNC622 Set Duty Cycle for the SYNC622.

1 = 50%.

0 = One 622.08 MHz clock cycle.

Conditions for use of this feature: A0h(2) = 0 and

SDH_HW pin low.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

6868 Agere Systems Inc.

This is the edge selection for the four SDH clocks generated by the SDH block. A high-bit means that the corresponding

clock’s rising edge will be synchronized to the negative edge of the input sync (actually it will lead the sync by 1—2 cycles

of a 622 MHz clock). If the edge selection bit is low, the falling edge of the corresponding clock will be aligned to the input

sync. This register is set to 1111 at reset, aligning the rising edges of the clocks to the input sync.

These registers are used to increase the possible offset between the input and output syncs. They will be used in enhanced

software offset configuration (pin SDH_HW = 0 and bit A0h(3) = 0), giving 17 bits for the absolute value of the offset as

opposed to the 10 bits available in hardware and basic software offset configuration. Those 17 bits are the 16 bits of regis-

ter A8h and bit A9h(0), which is the most significant bit of the offset. Bit A9h(1) is the direction of the offset (1 means that

the output sync will be delayed from the input sync). These registers are initialized to zero. In order to write registers A8h

and A9h, first A8h must be written. However, register A8h will not be actually written until register A9h is also written.

Table 17-31. CMOS SONET Clock Edge Selection

Address

(Hex)

Bit Name Description Reset

A7 15:4 — Reserved. 000000000000

3 CK78 Edge selection for the 77.76 MHz clock.

1 = Rising edge of corresponding clock aligned to input sync.

0 = Falling edge of corresponding clock aligned to input sync.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

2 CK51 Edge selection for the 51.84 MHz clock.

1 = Rising edge of corresponding clock aligned to input sync.

0 = Falling edge of corresponding clock aligned to input sync.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

1 CK38 Edge selection for the 38.88 MHz clock.

1 = Rising edge of corresponding clock aligned to input sync.

0 = Falling edge of corresponding clock aligned to input sync.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

0 CK19 Edge selection for the 19.44 MHz clock.

1 = Rising edge of corresponding clock aligned to input sync.

0 = Falling edge of corresponding clock aligned to input sync.

Conditions for use of this feature: A0h(2) = 0 and A0h(1) = 0.

Table 17-32. Enhanced Sync Offset

Address

(Hex)

Bit Name Description Reset

A8 15:0 SSYNCOFFSET Enhanced sync offset.

Bits A9h(0) (MSB) and A8h(15:0) contain the sync offset

value, calculated in increments of 1/622.08 (~1.6) ns. To

be used with A9h[1:0] - SSYOFFPOS.

Bit A9h(1): Denotes whether enhanced offset is positive

or negative:

1 = Positive.

0 = Negative.

Bits A9h(15:2): Reserved.

Conditions for use of this feature: A0h(3) = 0 and

SDH_HW pin low.

0000000000000000

A9 15:2 — 00000000000000

1 SYOFFPOS 0

0 SSYNCOFFSET(16) 0

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 69

These registers contain the value RISE used by the algorithm to calculate the position of the rising edge of the output sync.

These two registers together offer 17 bits to define the value of RISE. Bit B1h(0) is the most significant bit. At initialization,

these registers have the value B1h(0) and Bh0 = 1001011111100000 = 77,760.

These registers are also used in conjunction with register B6h to generate the parameter tcnt, used by the high-speed sync

generation block. It is not recommended that rise position of the sync outputs be adjusted in this fashion, since the fre-

quency of the sync outputs may be affected. It is recommended instead to use the offset functionality in registers A8h and

A9h to control the rise of the sync outputs and then use register B2h to control the fall position.

Register B2h is used to store the value of the parameter FALL used by the sync generation algorithm. This register can be

modified to obtain any desired duty cycle on the output syncs. It is initialized at 1001011111100000 = 38,880. Given that

value, with the initial value of registers B0h and B1h, the output syncs will have 50% duty cycle when the corresponding

duty cycle bit is high.

Table 17-33. Sync Rising Edge Position

Address

(Hex)

Bit Name Description Reset

B0 15:0 RISE Sync rising edge position.

Bits B1h(0) (MSB) and B0h(15:0) contain the sync rising edge position,

calculated in increments of 1/622.08 (~1.6) ns.

Bits B1h(15:1): Reserved.

by the internal state machine after one of the following actions occur:

1. The SDH_HW pin is high and the user changes the SYOFF or

SYOFFPOS pins.

2. SDH_HW is low, A0(3) is high and the user writes to register A3.

3. SDH_HW is low, A0(3) is low and the user changes A8h or A9h.

0x2FC0

B1 15:1 — 0000000000000

0 RISE(16) 1

Table 17-34. Sync Falling Edge Position

Address

(Hex)

Bit Name Description Reset

B2 15:0 FALL Sync falling edge position.

Contains the sync falling edge position, calculated in increments of 1/622.08 (~1.6) ns.

Sync outputs must be set to 50% duty cycle for this feature. This can be set by the fol-

lowing: with A0h(2) high, set A2h(0) high; with A0h(2) low, set respective bits of A6h

high and for CMOS specifically, A4h[7:4] must be set either to 0001, 0010, 0100, or

1000.

nal state machine after one of the following actions occur:

■The SDH_HW pin is high and the user changes the SYOFF or SYOFFPOS pins.

■SDH_HW is low, A0(3) is high, and the user writes to register A3.

■SDH_HW is low, A0(3) is low, and the user changes A8h or A9h.

0x97E0

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

7070 Agere Systems Inc.

This register gives an extra offset to compensate the delay due to the circuits. This offset is always negative, as opposed to

the regular offset defined by registers A3h or A8h/A9h, which can be positive or negative (positive offset increases the

delay of the output sync in relation to the negative edge of the input sync). This register is initialized to 10110 = 22. That

value compensates the delay between the negative edge of the input sync and the positive edge of the output sync when

the regular offset is zero. Without this extra offset, the output sync would be delayed twenty-two 622 MHz clock cycles.

The 5 bits of register B6h are used in conjunction with registers B0h/B1h to calculate the value of the parameter tcnt used

by the sync generation algorithm (tcnt = RISE-B6h). The value of B6h will be subtracted from the value of registers B0h/

B1h to calculate tcnt. The initial value at reset is 01011 = 11. As it can be seen in the previous algorithm description, this

value is needed to generate the proper value for tcnt.

It is not recommended that rise position of the sync outputs be adjusted in this fashion, since the frequency of the sync out-

puts may be affected. It is recommended instead to use the offset functionality in registers A8h and A9h to control the rise

of the sync outputs and then use register B2h to control the fall position.

Table 17-35. Sync Delta

Address

(Hex)

Bit Name Description Reset

B3 15:5 — Reserved. 00000000000

4:0 DELTA Compensation for the delay between the negative edge of the input sync and the

positive edge of the output sync when the regular offset is zero. Value of this off-

set indicates number of 1/622.08 (~1.6) ns increments. Register B0h—B6h will

only be recalculated (and affect the sync outputs) by the internal state machine

after one of the following actions occur:

■The SDH_HW pin is high and the user changes the SYOFF or SYOFFPOS

pins.

■SDH_HW is low, A0(3) is high, and the user writes to register A3.

■SDH_HW is low, A0(3) is low, and the user changes A8h or A9h.

10110

Table 17-36. Sync Delta Rise

Address

(Hex)

Bit Name Description Reset

B6 15:5 — Reserved. 00000000000

4:0 DELTARISE The 5 bits of register B6h are used in conjunction with registers B0h/B1h to

calculate the value of the parameter tcnt used by the sync generation algo-

rithm (tcnt = RISE–B6h). The value of B6h will be subtracted from the value

of registers B0h/B1h to calculate tcnt.

by the internal state machine after one of the following actions occur:

■The SDH_HW pin is high and the user changes the SYOFF or

SYOFFPOS pins.

■SDH_HW is low, A0(3) is high, and the user writes to register A3.

■SDH_HW is low, A0(3) is low, and the user changes A8h or A9h.

01011

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 71

The interrupt register E0h is a read-only and clear-on-read register that reflects the status of the TSWC interrupts. When-

ever there is an interrupt, the corresponding bit will be set high and will remain high until the register is read, even if the

event that generated the interrupt is over. However, the interrupt external pins reflect the interrupts only while they are

active, so the corresponding pin goes low as soon as the event has finished.

Table 17-37. Interrupt Status Register

Address

(Hex)

Bit Name Description Reset

E0 15:10 — Reserved. 111111

9 SQUELCH The output clocks have been squelched due to a problem.

1 = Squelch inactive.

0 = Squelch active.

8 LOCKOUT The TSWC will not allow any more clock switches.

1 = Lockout condition exist.

0 = Lockout condition does not exists.

7 CKCONTRA The TSWC is not working with the clock selected by the user.

1 = The TSWC is not working with the clock selected by the user.

0 = The TSWC is working with the clock selected by the user.

6 HSLOL Loss of lock—high-speed PLL.

1 = Loss of lock.

0 = In lock.

5 LSLOL Loss of lock—low-speed PLL.

1 = Loss of lock.

0 = In lock.

4 CLKSW Clock switch in progress.

1 = Clock switch in progress.

0 = No clock switch in progress.

3 LOCLS Loss of external 38.88 MHz VCXO clock.

1 = Loss of clock.

0 = No loss of clock.

2 LOCBU Loss of backup clock.

1 = Loss of clock.

0 = No loss of clock.

1 LOCB Loss of clock B.

1 = Loss of clock.

0 = No loss of clock.

0 LOCA Loss of clock A.

1 = Loss of clock.

0 = No loss of clock.

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

7272 Agere Systems Inc.

18 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those

given in the operational sections of this device specification. Exposure to absolute maximum ratings for extended periods

can adversely affect device reliability.

18.1 Handling Precautions

Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be

taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere

employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to deter-

mine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit

parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) stan-

dards.

18.2 Operating Conditions

Note: For conditions of SDHSEL[3:0] = 1111 and PDHSEL[3:0] = 1100, power dissipation will vary based on specific device configuration and customer

applications. For further information, contact the Agere Systems representative.

18.3 Powerup Conditions

No special powerup sequence is necessary; however, the device needs to be reset on powerup. The output clocks will be

active, i.e., free running, based on the pin configurations. CKPDHx clocks will not be active until the high-speed PLL is

locked.

Table 18-1. Absolute Maximum Ratings

Parameter Min Max Unit

Power Supply Voltage (VDD)–0.50 4.2 V

Storage Temperature –40 125 °C

Ball Voltage GND – 0.5 VDD + 0.5 V

Table 18-2. ESD Protection Characteristics

Device Minimum HBM Threshold Minimum CDM Threshold

TSWC03622 1500 V 200 V

Note: All pins, except LSVCO and VCN, have a minimum ESD-HBM threshold of 2000 V.

Table 18-3. Recommended Operation Conditions

Parameter Symbol Min Typ Max Unit

Power Supply (dc voltage) VDD 3.135 3.3 3.465 V

Temperature:

Ambient — –40 25 85 °C

Power Dissipation PD—1.0 1.7 W

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 73

19 Electrical Characteristics

19.1 LVPECL, LVDS, CMOS, Input, and Output Balls

Note: For Table 19-1 through Table 19-5, VDD = 3.3 V ± 5%, TAMBIENT = –40 °C to +85 °C.

* Looser than IEEE® spec of ±10 Ω.

Table 19-1. LVDS Output dc Characteristics

Applicable Balls Parameter Symbol Conditions Min Typ Max Unit

CK622P/N,

CK155P/N[1:0],

SYLVSP/N[1:0]

Output Voltage High, VOA or VOB VOH RLOAD = 100 Ω ± 1% 1350 — 1475 mV

Output Voltage Low, VOA or VOB VOL RLOAD = 100 Ω ± 1% 925 — 1100 mV

Output Differential Voltage |VOD| RLOAD = 100 Ω ± 1% 250 — 400 mV

Output Offset Voltage VOS R

LOAD = 100 Ω ± 1% 1125 — 1275 mV

Differential Output Impedance ROVCM = 1.0 V and 1.4 V 80 100 120 Ω

RO Mismatch Between A and B ∆Ro VCM = 1.0 V and 1.4 V — — 20 %

Change in |VOD| Between Logic 0

and Logic 1

|∆VOD|R

LOAD = 100 Ω ± 1% — — 25 mV

Change in |VOS| Between Logic 0

and Logic 1

|∆VOS|R

LOAD = 100 Ω ± 1% — — 25 mV

Output Current ISA, ISB Driver shorted to GND — — 24 mA

Output Current ISAB Drivers shorted together — — 12 mA

Table 19-2. LVDS Input dc Characteristics

Applicable

Balls

Parameter Symbol Conditions Min Typ Max Unit

CLKAP/N,

CLKBP/N

Input Common-mode Voltage

Range

VCM Avg(VIA,VIB) 0 1200 2400 mV

Input Peak Differential Voltage VDIFF |VIA –VIB| 100 — 800 mV

Input Differential Threshold VIDTH VIA –VIB –100 — 100 mV

Differential Input Impedance* RIN Measure at dc 80 100 120 Ω

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

7474 Agere Systems Inc.

Table 19-3. CMOS Input dc Characteristics

Applicable

Balls

Parameter Symbol Conditions Min Max Unit

LSVCO Input Voltage High VIH — VDD – 1.0 VDD V

Input Voltage Low VIL —GND 0.8 V

Input Current High Leakage IIH VIN = VDD —10 µA

Input Current Low Leakage IIL VIN = GND –10 —µA

CLKA,CLKB, CLKBU,

SYCLKA, SYCLKB,

SDHSEL[3:0],

SYOFF[9:0],

PDHSEL[3:0], SDH_HW,

TSTMODE

Input Voltage High VIH — VDD – 1.0 VDD V

Input Voltage Low VIL —GND 0.8 V

Input Current High Leakage IIH VIN = VDD —225 µA

Input Current Low Leakage IIL VIN = GND –10 —µA

SELLVDS, FINSEL[3:0],

FBUSEL[3:0], INLOSN,

SYOFFPOS, SYDU,

SELCLK, SELBUN,

AUTOSWN, REVERTN,

SWCONTN, ENSQLN,

RESETN, ENLON,

LORSTN, LF0Z,

SERCLK, SERENBLN,

SERDAT

Input Voltage High VIH — VDD –1.0 VDD V

Input Voltage Low VIL —GND 0.8 V

Input Current High Leakage IIH VIN = VDD —10 µA

Input Current Low Leakage IIL VIN = GND –225 —µA

Table 19-4. CMOS Output dc Characteristics

Applicable

Balls

Parameter Symbol Conditions Min Max Unit

CK77,CK51,

CK38,CK19, SYNC8K,

CKPDH5, CKPDH4,

CKPDH3, CKPDH2,

CKPDH1, MON8KA,

MON8KB SERDAT

Output Voltage High VOH IOH = –4.0 mA VDD – 0.5 VDD V

Output Voltage Low VOL IOL = 4.0 mA GND 0.5 V

Output Load Capacitance CL— — 15 pF

SWSTATE[1:0],

INT[8:0]

Output Voltage High VOH IOH = –1.0 mA VDD – 0.5 VDD V

Output Voltage Low VOL IOL = 1.0 mA GND 0.5 V

Output Load Capacitance CL— — 15 pF

Table 19-5. LVPECL Output dc Characteristics

Applicable

Balls

Parameter Symbol Conditions Min Typ Max Unit

PCK622P/N,

PCK155P/N[1:0],

SYPCLP/N[1:0]

Output Voltage High VOH Load = 50 Ω

connected to

VDD – 2.0 V

VDD – 1.21 VDD – 1.135 VDD – 1.06 V

Output Voltage Low VOL VDD – 2.01 VDD – 1.935 VDD – 1.86 V

Output Differential

Voltage

|VOD| 0.650 0.800 0.950 V

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 75

20 Timing Characteristics

*As defined in the IEEE standard 1596.3 -1996.

Table 20-1. LVDS Input ac Timing Characteristics

Applicable

Balls

Symbol Parameter Conditions Min Typ Max Unit

CLKAP/N,

CLKBP/N

tPW Pulse Width Input frequencies >8 kHz 8 — — ns

— Duty Cycle Input frequency = 8 kHz 45 50 55 %

Table 20-2. LVDS Output ac Timing Characteristics

Applicable

Balls

Symbol Parameter Conditions Min Typ Max Unit

CK622P/N,

CK155P/N[1:0]

SYLVSP/N[1:0]

tRISE

tFALL

Rise Time, 20% to 80%

Fall Time, 20% to 80%

ZLOAD = 100 Ω ± 1%

200

—

300

tSKEW1* Differential Skew — — — 50 ps

Table 20-3. CMOS Input ac Timing Characteristics

Applicable

Balls

Symbol Parameter Conditions Min Typ Max Unit

CLKA,CLKB,

CLKBU,

SYCLKA,

SYCLKB

tPW Pulse Width Input frequencies >8 kHz 8 — — ns

— Duty Cycle Input frequency = 8 kHz 45 50 55 %

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

7676 Agere Systems Inc.

21 Packaging Diagram

21.1 208-Plastic Ball Grid Array (17 x 17)-0.63 mm Ball Size (4-Layer—Bottom View)

Dimensions are in millimeters.

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Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 77

22 Ordering Information

Table 22-1. Ordering Information

Device Code Package Temperature Comcode

(Ordering Number)

TSWC03622 208 PBGAM1 –40°C to +85°C 700021311

TSWC03622 SONET/SDH/PDH/ATM Data Sheet

Clock Synthesizer and Protection Switch August 20, 2003

7878 Agere Systems Inc.

23 Revision History

23.1 Navigating Through an Adobe Acrobat Document

If the reader displays this document in Acrobat Reader ®, clicking on any blue entry in the text will bring the reader to that

reference point. Clicking on the back arrow in Acrobat Reader will bring the reader back to the starting point.

For example, clicking on page 11 (below) will bring the reader to page 11 of this document, which is the first change. Clicking

on the back arrow in Acrobat Reader will bring the reader back to this page.

23.2 Changes

Changes that were made to this document (since the September 2002 issue) are listed below.

An introductory paragraph was added. All sections have been assigned a section number; figures and tables have been

labelled according to major sections for ease of navigating through the document.

■On page 11: Figure was updated to reflect LF0Z, SYCLKA, and SYCLKB.

■On page 9: The title of Figure 4-1 was changed to reflect the correct package.

■On page 10: The title of Table 4-1 was changed to reflect the correct package. Ball names for A2, A3, A14, and A15 were

corrected.

■On page 11: The following have changed in Table 4-1, Ball Assignments for 208-Ball PBGA by Ball Number Order: P7

(NC) changed to MON8KB. P8 (RSVB) changed to SYCLKB. P10 (RSVA) changed to SYCLKA. P11 (NC) changed to

MON8KA.

■On page 12: The following have changed in Table 4-2, Physical Ball Orientation (Bumps Down):

P7 (NC) changed to MON8KB. P8 (RSVB) changed to SYCLKB. P10 (RSVA) changed to SYCLKA. P11 (NC) changed to

MON8KA.

■On page 13: P8 and P10 were added to Table 4-3, Clock Inputs and Related Signals.

■In Table 4-3 through Table 4-10, the footnotes now call out 50 kΩ for the pull-up and for the pull-down resistors.

■On page 15: In Table 4-6, Control and Related Signals, the descriptions for N16, N11, and P12 were changed.

■On page 16: Table 4-7, Serial Interface Signals, was added. Table 4-8, Test and Reserved Signals, was updated. In Table

4-9, No-Connect Signals, the footnotes were eliminated and ball P7 and ball P11 were deleted.

■On page 17: A note was added to Table 4-10, Power Signals, referencing the TSWC01622 Power Supply Grouping and

Filtering Application Note.

■On page 19: In the first paragraph, the phase offset changed from a maximum of 200 ns to a maximum of 250 ns, to be

consistent with the figures.

■On page 22: The paragraph under Section 7.4, Backup Reference Clock Selection (FBUSEL[3:0]), has been updated. In

Table 7-2, FBUSEL3 was changed from NC to 0.

■On page 23: Under Section 7.5, Input Clock Minimum Pulse-Width Specifications (Clock A, Clock B, and CLKBU), a tol-

erance of ±5% was added to the input duty cycle performance on an 8 kHz signal. A new Section 7.6, Input Sync Signal

Functionality, was added.

■On page 24: Under Section 8.1, Available Output Clocks, the TBDs in both paragraphs was replaced with the actual fre-

quencies.

■On page 26: In the first paragraph, added a reference to the Clock Requirements for the TSWC01622/TSYN01622

Devices For Ultramapper Family Devices Application Note. In Table 9-1, pins CKPDH1—CKPDH5 were deleted.

■On page 30: In Table 11-1, missing typical clock skew parameters are supplied.

■On page 31: In Table 11-2, missing typical clock skew parameters are supplied.

Data Sheet TSWC03622 SONET/SDH/PDH/ATM

August 20, 2003 Clock Synthesizer and Protection Switch

Agere Systems Inc. 79

■On page 32: In Table 11-3, missing typical clock skew parameters are supplied.

■On page 33: In Table 11-4, missing typical clock skew parameters were supplied.

■On page 34: The title of Table 11-5 has changed. All duty cycle tests have been deleted.

■On page 35: The first paragraph in Section 12.1, Maximum Time Interval Error (MTIE) Specifications, was updated. Val-

ues in Table 12-1 have changed.

■On page 36: The first paragraph in Section 12.2, Time Deviation (TDEV) Specifications, was updated, values in

Table 12-2 have changed.

■On page 37: Figure 12-4, Measured TDEV Wander Generation Performance, was added.

■On page 38: Values in Table 13-1 have changed.

■On page 41: The first entry in Table 14-1 has been updated. Added a note about loop filter components and recom-

mended solutions.

■On page 42: Table 14-3 was updated, a footnote was changed and a footnote was added.

■On page 43: Section 14.6, RREF, was added.

■On page 46: Section 15.4, Loss of Clock Criteria, was updated.

■On page 47: Figure 16-2, Serial Interface WRITE Frame Format, was updated to reflect a change of formatting from

A1:A8 and D1:D15 formatting to A7:A0 and D15:D0 formatting.

■On page 48: Figure 16-3, Serial Interface READ Frame Format, was updated to reflect a change of formatting from

A1:A8 and D1:D15 formatting to A7:A0 and D15:D0 formatting. A note was added to Figure 16-3. The paragraph under

Figure 16-3 was enhanced. Figure 16-4, Serial Interface Timing, was redrawn. Table 16-1, Serial Interface Timing, was

eliminated because no production testing has been performed. A note regarding minimum and maximum data was

added.

■On page 53: The paragraphs under Table 17-7, Loss of Clock Threshold and Table 17-8, Loss of Clock Hysteresis, were

changed.

■On page 58: In Table 17-16, PDH Control Register 2, the reset value for bits 4:3 and 2:0 were changed.

■On page 61: Table 17-20, SDH/Sync Control Register, was updated.

■On page 64: Table 17-25, Sync Source, was updated.

■Starting on page 66, the following sections were added: Section 17.6, LVPECL Output Syncs and Clocks, Section 17.7,

CMOS Output Syncs and Clocks.

■On page 69: Table 17-34, Sync Falling Edge Position, was updated.

■On page 72: Table 18-1, Absolute Maximum Ratings, was updated, and a note was added. In Table 18-2, ESD Protection

Characteristics, HBM was changed from 1000 V to 1500 V. A note was added below Table 18-3, Recommended Opera-

tion Conditions. In Table 18-3, Recommended Operation Conditions, the max power dissipation was replaced with 1.7.

Section 18.3, Powerup Conditions, was added.

■On page 73: Table 19-1, LVDS Output dc Characteristics, was updated and the footnote was removed. The footnote

under Table 19-2, LVDS Input dc Characteristics was updated.

■On page 74: Updated Table 19-3, CMOS Input dc Characteristics. Updated Table 19-4, CMOS Output dc Characteristics.

Table 19-5, LVPECL Output dc Characteristics, was updated.

■On page 75: Table 20-1, LVDS Input ac Timing Characteristics and Table 20-3, CMOS Input ac Timing Characteristics

were added. Table 73, CMOS Output ac Timing Characteristic and Table 74, LVPECL Output ac Timing Characteristic,

were deleted.

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere is a registered trademark of Agere Systems Inc. Agere Systems, the Agere logo, Ultramapper, Hypermapper, and Supermapper are trademarks of Agere Systems Inc.

August 20, 2003

DS03-120HSPL (Replaces DS02-308HSPL)

For additional information, contact your Agere Systems Account Manager or the following:

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Tel. (852) 3129-2000, FAX (852) 3129-2020

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