MOSEL VITELIC
1
V63C31321024
32K X 32 CMOS
SYNCHRONOUS BURST
PIPELINED SRAM
PRELIMINARY
V63C31321024 Rev. 0.3 October 1997
Features
■
High-speed clock access time: 5/6/7/8ns
■
Single 3.3V power supply
■
Synchronous operation
■
Individual byte write control and global write
■
Internal registers for address, data, and controls
■
Output data registers
■
Asynchronous Output Enable
■
Supports snooze mode (low-power state)
■
Internal burst counter supports interleaved or lin-
ear burst mode
■
Available in 100-pin PQFP/TQFP
Functional Description
The V63C31321024 is a high-speed synchro-
nous burst pipelined CMOS SRAM organized as
32,768 words b y 32 bits that supports both i486/
Pentium™ Interleaved mode and 680X0/Power
PC™ linear mode address pipelining. Control is
achieved through the use of the LBO pin.
Burst operations can be initiated with either the
address status processor (ADSP) or address status
cache controller (ADSC) inputs. Subsequently burst
addresses can be internally generated as controlled
by the burst advance (ADV) input.
The V63C31321024 operates on a single 3.3V
power supply and is ideally suited for applica-
tions that require high-speed, low-power and
wide-bit configuration in secondary cache designs.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns) Power Temperature
Mark
Q U 5 6 7 8 Std.
0
°
C to 70
°
C • • • • • • • Blank
2
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
Block Diagram
Byte 0
Write
Register
Address
Registers
Binary
Counter
Byte 0
Write
Driver
32Kx8x4
Memory
Array
Byte 1
Write
Register
Byte 1
Write
Driver
Byte 2
Write
Register
Byte 2
Write
Driver
Byte 3
Write
Register
Enable
Register
Sleep
Control
Input
Registers
Enable
Delay
Register
Byte 3
Write
Driver
Address
Registers
LBO
ADV
CLK
A0 to A14 15
15 13
8
8
8
8
4
4
15
32
32
32
A1
A0 A0'
A1'
CLR
ADSC
GW
BWE
BW0
BW1
BW2
BW3
CE3
CE2
CE1
ADSP
OE
ZZ
I/O0 to I/O31
3
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
NC
I/O16
I/O17
VCCQ
GNDQ
I/O18
I/O19
I/O20
I/O21
GNDQ
VCCQ
I/O22
I/O23
NC
VCC
NC
GND
I/O24
I/O25
VCCQ
GNDQ
I/O26
I/O27
I/O28
I/O29
GNDQ
VCCQ
I/O30
I/O31
NC
NC
I/O15
I/O14
VCCQ
GNDQ
I/O13
I/O12
I/O11
I/O10
GNDQ
VCCQ
I/O9
I/O8
GND
NC
VCC
ZZ
I/O7
I/O6
VCCQ
GNDQ
I/O5
I/O4
I/O3
I/O2
GNDQ
VCCQ
I/O1
I/O0
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A6
A7
CE1
CE2
BW3
BW2
BW1
BW0
CE3
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
LBO
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
NC
NC
100-Pin QFP/TQFP
PIN CONFIGURATION
Ordering Information
FAMILY DEVICE
PKG
SPEED
PWR.
V63C –
5 (5 ns)
6 (6 ns)
7 (7 ns)
8 (8 ns)
TEMP.
BLANK (0°C to 70°C)
BLANK (STANDARD)Q (PQFP)
U (TQFP)
31321024-08
MOSEL VITELIC
V63C31321024
4
V63C31321024 Rev. 0.3 October 1997
Absolute Maximum Ratings*
Core Supply Voltage to GND.............–0.5 to +4.6V
I/O Supply Voltage to GND................–0.5 to +4.6V
Input/Output to
GND Potential......... GNDQ–0.5 to V
CCQ
+0.5V
Allowable Power Dissipation ..........................1.0W
Storage Temperature ...................... –65 to +150
°
C
Operating Temperature ......................... 0 to +70
°
C
Note:
Exposure to conditions beyond those listed under
Absolute Maximum Ratings
may adversely affect the life
and reliability of the device.
Capacitance
V
CC
= 3.3 V, T
A
= 25
°
C, f = 1 MHz
* Note: These parameters are guaranteed by device
characterization and are not production tested.
Symbol Parameter* Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 0V 6 pF
C
I/O
Input/Output
Capacitance V
OUT
= 0V 8 pF
Pin Names
Symbol Type Description
A0—A14 Input, Synchronous Hot Address
I/O
0
-I/O
31
I/O, Synchronous Data Inputs/Outputs
CLK Input, Clock Processor Host Bus Clock
CE1, CE2, CE3 Input, Synchronous Chip Enables
GW Input, Synchronous Global Write
BWE Input, Synchronous Byte Write Enable from Cache Controller
BW
0
-BW
3
Input, Synchronous Host BusByte Enables Used with BWE
OE Input, Asynchronous Output Enable Input
ADV Input, Synchronous Internal Burst Address Counter Advance
ADSC Input, Synchronous Address Status from CPU
ADSP Input, Synchronous Address Status from Chip Set
ZZ Input, Asynchronous Snooze Pin for Low-Power State
LBO Input, Static This Mode Selects Burst Sequence
LOW for Linear or HIGH for interleaved
V
CCQ
I/O Power Supply
GNDQ I/O Ground
V
CC
Power Supply
GND Ground
5
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
Truth Table
Notes:
1. For a detailed definition of read/write, see the Write Table (next page).
2. A “X” means “don’t care,” “1” means logic HIGH, and “0” means logic LOW.
3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled
synchronous to the bus clock except for the OE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data
to setup the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM
data hold timing are met.
Cycle Address
Used CE1 CE2 CE3 ADSP ADSC ADV OE Data
Write
(1)
Unselected No 1 X X X 0 X X Hi-Z X
Unselected No 0 X 1 0 X X X Hi-Z X
Unselected No 0 0 X 0 X X X Hi-Z X
Unselected No 0 X 1 1 0 X X Hi-Z X
Unselected No 0 0 X 1 0 X X Hi-Z X
Begin Read External 0100XXXHi-Z X
Begin Read External 01010XXHi-Z Read
Continue Read Next X X X 1101Hi-Z Read
Continue Read Next X X X 1100D-OUT Read
Continue Read Next 1 X X X 1 0 1 Hi-Z Read
Continue Read Next 1 X X X 1 0 0 D-OUT Read
Suspend Read Current X X X 1111Hi-Z Read
Suspend Read Current X X X 1110D-Out Read
Suspend Read Current 1 X X X 1 1 1 Hi-Z Read
Suspend Read Current 1 X X X 1 1 0 D-OUT Read
Begin Write Current X X X 1 1 1 X Hi-Z Write
Begin Write Current 1 X X X 1 1 X Hi-Z Write
Begin Write External 01010XXHi-Z Write
Continue Write Next X X X 1 1 0 X Hi-Z Write
Continue Write Next 1 X X X 1 0 X Hi-Z Write
Suspend Write Current X X X 1 1 1 X Hi-Z Write
Suspend Write Current 1 X X X 1 1 X Hi-Z Write
MOSEL VITELIC
V63C31321024
6
V63C31321024 Rev. 0.3 October 1997
Write Mode
The V63C31321024 support different kinds of
write mode operations. The BWE and BW [3:0]
support individual byte writes. The BE [7:0] signals
can be directly connected to the SRAM BW [3:0].
The GW signal is used to override the byte enable
signals and allows the cache controller to write all
bytes to the SRAM, no matter what the byte write
enable signals are. The various write modes are
indicated in the Write Table, below. Note that in
pipelined mode, the byte write enable signals are
not latched by the SRAM with addresses but with
data. In pipelined mode, the cache controller must
ensure the SRAM latches both data and valid byte
enable signals from the processor.
Write Table
Burst Address Sequence
Read/Write Function GW BWE BW3BW2BW1BW0
Read 1 1 XXXX
Read 101111
Write Byte 0, I/O
0
– I/O
7
101110
Write Byte 1, I/O
8
– I/O
15
101101
Write Byte 1, Byte 0 101100
Write Byte 2, I/O
16
– I/O
23
101011
Write Byte 2, Byte 0 101010
Write Byte 2, Byte 1 101001
Write Byte 2, Byte 1, Byte 0 101000
Write Byte 3, I/O
24
– I/O
31
100111
Write Byte 3, Byte 0 100110
Write Byte 3, Byte 1 100101
Write Byte 3, Byte 1, Byte 0 100100
Write Byte 3, Byte 2 100011
Write Byte 3, Byte 2, Byte 0 100010
Write Byte 3, Byte 2, Byte 1 100001
Write All Bytes, I/O
0
– I/O
31
100000
Write All Bytes, I/O
0
– I/O
31
0XXXXX
Intel System (LBO = V
CCQ
) Linear Mode (LBO = GNDQ)
A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0]
External Start Address 00 01 10 11 00 01 10 11
Second Address 01 00 11 10 01 10 11 00
Third Address 10 11 00 01 10 11 00 01
Fourth Address 11 10 01 00 11 00 01 10
7
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
Snooze Mode
The ZZ state is a low-power state in which the de-
vice consumes less power than in the unselected
mode. Enabling the ZZ pin for a fixed period of time
will force the SRAM into the ZZ state. Pulling the ZZ
pin LOW for a set period of time will wake up the
SRAM again. While the SRAM is in ZZ mode, data
retention is guaranteed, but the chip will not monitor
any input signal except for the ZZ pin. In the unse-
lected mode, the other hand, all the input signals are
monitored.
Asynchronous Truth Table
Note: H means logic HIGH. L means logic LOW. X means H or L.
Operating Characteristics
(V
CC
= 3.3V
±
5%, T
A
= 0 to 70
°
C)
Note: V
IL
Min = –2.0V undershoot for pulse width
≤
t
CYC
Min/2.
AC Test Conditions
Operation ZZ OE I/O Status
Read L L Data Out
Read L H High-Z
Write L X High-Z, Data in
Deselect L X High-Z
Power down (Snooze) H X High-Z
Parameter Sym Test Conditions Min. Typ. Max. Unit
Input Low Voltage V
IL
–0.5 – +0.8 V
Input High Votage V
IH
2.0 – V
CC
+0.3 V
Input Leakage Current I
LI
V
IN
= GND to V
CCQ
–10 – +10
µ
A
Output Leakage Current I
LO
V
I/O
= GND to V
CCQ
, & data I/O pins disabled –10 – +10
µ
A
Output Low Voltage V
OL
V
OL
= 8mA – – 0.4 V
Output High Voltage V
OH
V
OH
= -4mA 2.4 – – V
Operating Current I
DD
T
CYC
≥
t
KC
Min, I/O = 0 mA, V
CC
= Max – – 250 mA
Standby Current I
SB
V
CC
= Max, Device deselected
All inputs = V
IL
or V
IH
T
CYC
≥
t
KC
Min – – 50 mA
ZZ Mode Current I
ZZ
ZZ mode, T
CYC
≥
t
KC
Min – – 5 mA
Parameter Conditions
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 2 ns
Input and Output Timing Reference Level 1.5V
Output Load C
L
= 30 pF, I
OH
/ IOL = –4mA/8mA
8
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
AC Test Loads and Waveform
AC Timing Characteristics
(VCC = 3.3V ±5%, TA = 0 to 70°C)
# Sym Parameter
5678
Unit NoteMin. Max. Min. Max. Min. Max. Min. Max.
1t
AS Address Setup Time 2.5 – 2.5 – 2.5 – 2.5 – ns
2t
AH Address Hold Time 0.5 – 0.5 – 0.5 – 0.5 – ns
3t
DS Data Setup Time 2.5 – 2.5 – 2.5 – 2.5 – ns
4t
DH Data Hold Time 0.5 – 0.5 – 0.5 – 0.5 – ns
5t
ADVS ADV Setup Time 2.5 – 2.5 – 2.5 – 2.5 – ns
6t
ADVH ADV Hold Time 0.5 – 0.5 – 0.5 – 0.5 – ns
7t
ADSS ADSP Setup Time 2.5 – 2.5 – 2.5 – 2.5 – ns
8t
ADSH ADSP Hold Time 0.5 – 0.5 – 0.5 – 0.5 – ns
9t
ADCS ADSC Setup Time 2.5 – 2.5 – 2.5 – 2.5 – ns
10 tADCH ADSC Hold Time 0.5 – 0.5 – 0.5 – 0.5 – ns
11 tCES CE1, CE2, CE3 Setup Time 2.5 – 2.5 – 2.5 – 2.5 – ns
12 tCEH CE1, CE2, CE3 Hold Time 0.5 – 0.5 – 0.5 – 0.5 – ns
13 tWS GW, BWE X Setup Time 2.5 – 2.5 – 2.5 – 2.5 – ns
14 tWH GW, BWE X Hold Time 0.5 – 0.5 – 0.5 – 0.5 – ns
15 tCYC Clock Cycle Time 10 – 11.1 – 13.3 – 15 – ns
16 tKH Clock High Pulse Width 5 –6–6–6–ns
17 tKL Clock Low Pulse Width 5 –6–6–6–ns
18 tKQ Clock to Output Valid –5–6–7–8ns
19 tKHZ Clock to Output High-Z 2 10 2 11.1 2 13.3 2 15 ns 1
20 tKLZ Clock to Output Low-Z 0 – 0 – 0 – 0 – ns 1
21 tKX Clock to Output Invalid 2–2–2 –2–ns1
22 tOE Output Enable to Output Valid –5–6–7–8ns
23 tOHZ Output Enable to Output High-Z –5–6–7–8ns1
50 ohm
1.5V
3.0V
0V
90%
10%
2 ns
I/O Pin
30 pF
Zo = 50 ohm
9
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
Notes:
1. These parameters are sampled but not 100% tested.
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is
active.
3. ADSC and ADSP should not be accessed for at least 100 ns after chip leaves ZZ Mode.
24 tOLZ Output Enable to Output Low-Z 0–0–0–0–ns1
25 tOX Output Enable to Output Invalid 0–0–0–0–ns
26 tZZS ZZ Standby Time – 100 – 100 – 100 – 100 ns 2
27 tZZR ZZ Recover Time 100 – 100 – 100 – 100 – ns 3
# Sym Parameter
5678
Unit NoteMin. Max. Min. Max. Min. Max. Min. Max.
AC Characteristics
(Cont’d)
10
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
Waveforms of Read Cycle
CLK
ADSP
ADSC
ADV
A[14:0]
GW
BWE
BW[3:0]
CE1
CE2
CE3
OE
DATA OUT
DATA IN
DON’T CARE UNDEFINED
Single Read
tAH(2)
tAS(1)
tOLZ(24)
tKHZ(19)
tKQ(18)
HIGH-Z 1a 2c
HIGH-Z
tOE(22) tOHZ(23)
tKHZ(19)
tKH(16) tKL(17)
tCYC(15)
Pipelined Read
Burst Read Unselected
RD1 RD2 RD3
tADVS(5) tADVH(6)
tADCS(9) tADCH(10)
tADSS(7) tADSH(8) ADSP is block by CE1 inactive
ADSC Initiated Read
Suspend Burst
tWS(13)
tWS(13)
CE1 masks ADSP
tCES(11)
tCES(11)
tCES(11)
tCEH(12)
tCEH(12)
tCEH(12)
CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2
tOX(25)
2b 2d 3a2a
tWH(14)
tWH(14)
tKX(21) tKX(21)
11
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
Waveforms of Write Cycle
CLK
ADSP
ADSC
ADV
A[14:0]
GW
BWE
BW[3:0]
CE1
CE2
CE3
OE
DATA IN
DATA OUT
DON’T CARE UNDEFINED
Single Read
tAS(1)
tDS(3) tDH(4)
HIGH-Z
HIGH-Z
tKH(16) tKL(17)
tCYC(15) WriteBurst Read Unselected
WR1 WR2 WR3
WR1 WR2 WR3
tADVS(5) tADVH(6)
tADCS(9) tADCH(10)
tADSS(7) tADSH(8) ADSP is block by CE1 inactive
ADSC Initiated Write
tWS(13)
CE1 masks ADSP
tCES(11)
tCES(11)
tCES(11)
tCEH(12)
tCEH(12)
tCEH(12)
CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2
GWE allows process address (and BE = BW) to be pipelined during a writeback
ADV must be inactive for ADSP write
1a 2a 2b 2c 2d 3a
tAH(2)
tWH(14)
tWS(13) tWH(14)
tWS(13) tWH(14)
12
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
Waveforms of Read/Write Cycle
CLK
ADSP
ADSC
ADV
A[14:0]
GW
BWE
BW[3:0]
CE1
CE2
CE3
OE
DATA IN
DATA OUT
DON’T CARE UNDEFINED
Single Read Single Write
tOLZ(24)
tKLZ(20)
HIGH-Z
2a 2b 2c 2d
HIGH-Z
tKX(21)
tKHZ(19)
tOE(22) tOHZ(23)
tKH(16) tKL(17)
tCYC(15) Burst Read Unselected
tWS(13)
ADSP is block by CE1 inactive
tDS(3)
tOH
tKHZ(19)
tKQ(18)
tADCH(10)
tADCS(9)
tADVS(5)
WR1
Unselected with CE3
tADVH(6)
ADSC initiated Read
Suspend Burst
tWS(13)
tWS(13)
tCES(11)
tCES(11)
tCES(11) tCEH(12)
tCEH(12)
tCEH(12)
CE2 and CE3 only sampled with ADSP or ADSC
CE masks ADSP
RD1 WR1 RD2
1a
tADSH(8)
tADSS(7)
tAS(1) tAH(2)
tWH(14)
tWH(14)
tWH(14)
tDH(4)
13
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
Waveforms of ZZ and RD Cycle
CLK
ADSP
ADSC
ADV
A[14:0]
GW
BWE
BW[3:0]
CE1
CE2
CE3
OE
DATA IN
ZZ
DATA OUT
DON’T CARE UNDEFINED
Single Read
tOLZ(24)
tKLZ(20)
tKQ(18) tKHZ(19) tZZS(26) tZZR(27)
HIGH-Z
HIGH-Z
tOE(22)
tKX(21)
tOHZ(23)
tKH(4) tKL(17)
tCYC(15) Snooze with Data Retention Read
tOH
tADVS(5) tADVH(6)
tWS(13)
tWS(13)
tWS(13)
tCES(11) tCEH(12)
tCES(11) tCEH(12)
tCES(11) tCEH(12)
tADSS(7)
RD RD RD
1a
RD1 RD2
tADSH(8)
tAS(1) tAH(2)
tWH(14)
tWH(14)
tWH(14)
14
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
Package Diagram
100-pin PQFP (Q)
0.913
+0.008
–0.007
[23.190
]
+0.203
–0.178
0.012+0.003
–0.002 [0.305 ]
+0.076
–0.051
0.787±0.004
[19.990±0.102]
0.551±0.004
[13.995±0.102]
1
30
31 50
51
80
81
100
0.677±0.008
[17.195±0.203]
TOP VIEW
0.144 MAX
[3.657 MAX]
0.035 ±0.006
[0.889 ±0.152]
0.063 TYP.
[1.600 TYP.]
0.134 MAX.
[3.404 MAX.] Unit in inches [mm]
0.010 MIN.
[0.254 MIN.]
0.004 MIN.
[0.102 MIN.]
SEE DETAIL “F”
DETAIL “F”
GAGE PLANE
SEATING PLANE
0.026 TYP.
[0.660 TYP.]
15
V63C31321024 Rev. 0.3 October 1997
MOSEL VITELIC
V63C31321024
100-pin TQFP (TQ)
0.886
±0.006
[21.996±0.152]
0.013±0.002
[0.033±0.051]
0.787±0.004
[19.990±0.102]
0.551±0.004
[13.995±0.102]
1
30
31 50
51
80
81
100
0.630±0.006
[16.002±0.152]
TOP VIEW
0.063 MAX
[1.600 MAX]
0.024±0.006
[0.609±0.152]
0.039 TYP.
[0.990 TYP.]
0.055±0.002
[1.397±0.051]
0.002 MIN.
[0.051 MIN.]
0.004 MIN.
[0.102 MIN.]
SEE DETAIL “F”
DETAIL “F”
GAGE PLANE
SEATING PLANE
0.026 TYP.
[0.65 TYP.]
Unit in inches [mm]
MOSEL VITELIC
WORLDWIDE OFFICES V63C31321024
U.S.A.
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 011-852-665-4883
FAX: 011-852-664-7535
TAIWAN
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 011-886-2-545-1213
FAX: 011-886-2-545-1209
© Copyright 1997, MOSEL VITELIC Inc. 10/97
Printed in U.S.A.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
U.S.A.
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 011-852-665-4883
FAX: 011-852-664-7535
TAIWAN
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 011-886-2-545-1213
FAX: 011-886-2-545-1209
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 011-886-35-783344
FAX: 011-886-35-792838
JAPAN
WBG MARINE WEST 25F
6, NAKASE 2-CHOME
MIHAMA-KU, CHIBA-SHI
CHIBA 261-71
PHONE: 011-81-43-299-6000
FAX: 011-81-43-299-6555
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
SOUTHWESTERN
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 562-498-3314
FAX: 562-597-2174
CENTRAL & SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
U.S. SALES OFFICES