MOSEL VITELIC PRELIMINARY V63C31321024 32K X 32 CMOS SYNCHRONOUS BURST PIPELINED SRAM Features Functional Description The V63C31321024 is a high-speed synchronous burst pipelined CMOS SRAM organized as 32,768 words by 32 bits that supports both i486/ PentiumTM Interleaved mode and 680X0/Power PCTM linear mode address pipelining. Control is achieved through the use of the LBO pin. Burst operations can be initiated with either the address status processor (ADSP) or address status cache controller (ADSC) inputs. Subsequently burst addresses can be internally generated as controlled by the burst advance (ADV) input. The V63C31321024 operates on a single 3.3V power supply and is ideally suited for applications that require high-speed, low-power and wide-bit configuration in secondary cache designs. High-speed clock access time: 5/6/7/8ns Single 3.3V power supply Synchronous operation Individual byte write control and global write Internal registers for address, data, and controls Output data registers Asynchronous Output Enable Supports snooze mode (low-power state) Internal burst counter supports interleaved or linear burst mode Available in 100-pin PQFP/TQFP Device Usage Chart Operating Temperature Range 0C to 70 C Package Outline Access Time (ns) Power Q U 5 6 7 8 Std. Temperature Mark * * * * * * * Blank V63C31321024 Rev. 0.3 October 1997 1 V63C31321024 MOSEL VITELIC Block Diagram LBO A0' 15 A0 to A14 Address Registers ADSC Binary Counter CLR ADV CLK A0 A1' A1 15 13 15 GW Byte 0 Write Register Byte 0 Write Driver 8 Byte 1 Write Register Byte 1 Write Driver 8 BW2 Byte 2 Write Register Byte 2 Write Driver BW3 Byte 3 Write Register Byte 3 Write Driver BWE BW0 BW1 CE3 32Kx8x4 Memory Array 8 8 4 CE2 Enable Register CE1 32 32 4 Address Registers Enable Delay Register ADSP OE Input Registers ZZ 32 Sleep Control I/O0 to I/O31 V63C31321024 Rev. 0.3 October 1997 2 V63C31321024 MOSEL VITELIC Ordering Information V 6 3 C - FAMILY DEVICE PWR. SPEED TEMP. PKG BLANK (STANDARD) 5 6 7 8 (5 ns) (6 ns) (7 ns) (8 ns) BLANK (0C to 70C) Q (PQFP) U (TQFP) 31321024-08 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE1 CE2 BW3 BW2 BW1 BW0 CE3 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Pin QFP/TQFP PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LBO A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC I/O16 I/O17 VCCQ GNDQ I/O18 I/O19 I/O20 I/O21 GNDQ VCCQ I/O22 I/O23 NC VCC NC GND I/O24 I/O25 VCCQ GNDQ I/O26 I/O27 I/O28 I/O29 GNDQ VCCQ I/O30 I/O31 NC V63C31321024 Rev. 0.3 October 1997 3 NC I/O15 I/O14 VCCQ GNDQ I/O13 I/O12 I/O11 I/O10 GNDQ VCCQ I/O9 I/O8 GND NC VCC ZZ I/O7 I/O6 VCCQ GNDQ I/O5 I/O4 I/O3 I/O2 GNDQ VCCQ I/O1 I/O0 NC V63C31321024 MOSEL VITELIC Pin Names Symbol Type Description A0--A14 Input, Synchronous Hot Address I/O0-I/O31 I/O, Synchronous Data Inputs/Outputs CLK Input, Clock Processor Host Bus Clock CE1, CE2, CE3 Input, Synchronous Chip Enables GW Input, Synchronous Global Write BWE Input, Synchronous Byte Write Enable from Cache Controller BW0-BW3 Input, Synchronous Host BusByte Enables Used with BWE OE Input, Asynchronous Output Enable Input ADV Input, Synchronous Internal Burst Address Counter Advance ADSC Input, Synchronous Address Status from CPU ADSP Input, Synchronous Address Status from Chip Set ZZ Input, Asynchronous Snooze Pin for Low-Power State LBO Input, Static This Mode Selects Burst Sequence LOW for Linear or HIGH for interleaved VCCQ I/O Power Supply GNDQ I/O Ground VCC Power Supply GND Ground Absolute Maximum Ratings* Capacitance VCC = 3.3 V, TA = 25C, f = 1 MHz Core Supply Voltage to GND............. -0.5 to +4.6V I/O Supply Voltage to GND................ -0.5 to +4.6V Input/Output to GND Potential ......... GNDQ-0.5 to VCCQ+0.5V Allowable Power Dissipation .......................... 1.0W Storage Temperature ...................... -65 to +150C Operating Temperature ......................... 0 to +70C Parameter* Conditions Max. Unit CIN Input Capacitance VIN = 0V 6 pF CI/O Input/Output Capacitance VOUT = 0V 8 pF * Note: These parameters are guaranteed by device characterization and are not production tested. Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. V63C31321024 Rev. 0.3 October 1997 Symbol 4 V63C31321024 MOSEL VITELIC Truth Table Address Used CE1 CE2 CE3 ADSP ADSC ADV OE Data Write(1) Unselected No 1 X X X 0 X X Hi-Z X Unselected No 0 X 1 0 X X X Hi-Z X Unselected No 0 0 X 0 X X X Hi-Z X Unselected No 0 X 1 1 0 X X Hi-Z X Unselected No 0 0 X 1 0 X X Hi-Z X Begin Read External 0 1 0 0 X X X Hi-Z X Begin Read External 0 1 0 1 0 X X Hi-Z Read Continue Read Next X X X 1 1 0 1 Hi-Z Read Continue Read Next X X X 1 1 0 0 D-OUT Read Continue Read Next 1 X X X 1 0 1 Hi-Z Read Continue Read Next 1 X X X 1 0 0 D-OUT Read Suspend Read Current X X X 1 1 1 1 Hi-Z Read Suspend Read Current X X X 1 1 1 0 D-Out Read Suspend Read Current 1 X X X 1 1 1 Hi-Z Read Suspend Read Current 1 X X X 1 1 0 D-OUT Read Begin Write Current X X X 1 1 1 X Hi-Z Write Begin Write Current 1 X X X 1 1 X Hi-Z Write Begin Write External 0 1 0 1 0 X X Hi-Z Write Continue Write Next X X X 1 1 0 X Hi-Z Write Continue Write Next 1 X X X 1 0 X Hi-Z Write Suspend Write Current X X X 1 1 1 X Hi-Z Write Suspend Write Current 1 X X X 1 1 X Hi-Z Write Cycle Notes: 1. For a detailed definition of read/write, see the Write Table (next page). 2. A "X" means "don't care," "1" means logic HIGH, and "0" means logic LOW. 3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to the bus clock except for the OE pin. 4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timing are met. V63C31321024 Rev. 0.3 October 1997 5 V63C31321024 MOSEL VITELIC Write Mode enable signals are. The various write modes are indicated in the Write Table, below. Note that in pipelined mode, the byte write enable signals are not latched by the SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM latches both data and valid byte enable signals from the processor. The V63C31321024 support different kinds of write mode operations. The BWE and BW [3:0] support individual byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [3:0]. The GW signal is used to override the byte enable signals and allows the cache controller to write all bytes to the SRAM, no matter what the byte write Write Table GW BWE BW3 BW2 BW1 BW0 Read 1 1 X X X X Read 1 0 1 1 1 1 Write Byte 0, I/O0 - I/O7 1 0 1 1 1 0 Write Byte 1, I/O8 - I/O15 1 0 1 1 0 1 Write Byte 1, Byte 0 1 0 1 1 0 0 Write Byte 2, I/O16 - I/O23 1 0 1 0 1 1 Write Byte 2, Byte 0 1 0 1 0 1 0 Write Byte 2, Byte 1 1 0 1 0 0 1 Write Byte 2, Byte 1, Byte 0 1 0 1 0 0 0 Write Byte 3, I/O24 - I/O31 1 0 0 1 1 1 Write Byte 3, Byte 0 1 0 0 1 1 0 Write Byte 3, Byte 1 1 0 0 1 0 1 Write Byte 3, Byte 1, Byte 0 1 0 0 1 0 0 Write Byte 3, Byte 2 1 0 0 0 1 1 Write Byte 3, Byte 2, Byte 0 1 0 0 0 1 0 Write Byte 3, Byte 2, Byte 1 1 0 0 0 0 1 Write All Bytes, I/O0 - I/O31 1 0 0 0 0 0 Write All Bytes, I/O0 - I/O31 0 X X X X X Read/Write Function Burst Address Sequence Intel System (LBO = VCCQ) Linear Mode (LBO = GNDQ) A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] External Start Address 00 01 10 11 00 01 10 11 Second Address 01 00 11 10 01 10 11 00 Third Address 10 11 00 01 10 11 00 01 Fourth Address 11 10 01 00 11 00 01 10 V63C31321024 Rev. 0.3 October 1997 6 V63C31321024 MOSEL VITELIC Snooze Mode SRAM again. While the SRAM is in ZZ mode, data retention is guaranteed, but the chip will not monitor any input signal except for the ZZ pin. In the unselected mode, the other hand, all the input signals are monitored. The ZZ state is a low-power state in which the device consumes less power than in the unselected mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the ZZ pin LOW for a set period of time will wake up the Asynchronous Truth Table Operation ZZ OE Read L L Data Out Read L H High-Z Write L X High-Z, Data in Deselect L X High-Z Power down (Snooze) H X High-Z I/O Status Note: H means logic HIGH. L means logic LOW. X means H or L. Operating Characteristics (VCC = 3.3V 5%, TA = 0 to 70C) Parameter Sym Test Conditions Min. Typ. Max. Unit Input Low Voltage VIL -0.5 - +0.8 V Input High Votage VIH 2.0 - VCC +0.3 V Input Leakage Current ILI VIN = GND to VCCQ -10 - +10 A Output Leakage Current ILO VI/O = GND to VCCQ, & data I/O pins disabled -10 - +10 A Output Low Voltage VOL VOL = 8mA - - 0.4 V Output High Voltage VOH VOH = -4mA 2.4 - - V Operating Current IDD TCYC tKC Min, I/O = 0 mA, VCC = Max - - 250 mA Standby Current ISB VCC = Max, Device deselected All inputs = VIL or VIH TCYC tKC Min - - 50 mA ZZ mode, TCYC tKC Min - - 5 mA ZZ Mode Current IZZ Note: VIL Min = -2.0V undershoot for pulse width tCYC Min/2. AC Test Conditions Parameter Conditions Input Pulse Levels 0V to 3V Input Rise and Fall Times 2 ns Input and Output Timing Reference Level 1.5V Output Load CL = 30 pF, IOH / IOL = -4mA/8mA V63C31321024 Rev. 0.3 October 1997 7 V63C31321024 MOSEL VITELIC AC Test Loads and Waveform 1.5V 3.0V 50 ohm 90% I/O Pin 10% 0V 30 pF 2 ns Zo = 50 ohm AC Timing Characteristics (VCC = 3.3V 5%, TA = 0 to 70C) 5 # Sym 1 tAS 2 Parameter 6 7 8 Min. Max. Min. Max. Min. Max. Min. Max. Unit Address Setup Time 2.5 - 2.5 - 2.5 - 2.5 - ns tAH Address Hold Time 0.5 - 0.5 - 0.5 - 0.5 - ns 3 tDS Data Setup Time 2.5 - 2.5 - 2.5 - 2.5 - ns 4 tDH Data Hold Time 0.5 - 0.5 - 0.5 - 0.5 - ns 5 tADVS ADV Setup Time 2.5 - 2.5 - 2.5 - 2.5 - ns 6 tADVH ADV Hold Time 0.5 - 0.5 - 0.5 - 0.5 - ns 7 tADSS ADSP Setup Time 2.5 - 2.5 - 2.5 - 2.5 - ns 8 tADSH ADSP Hold Time 0.5 - 0.5 - 0.5 - 0.5 - ns 9 tADCS ADSC Setup Time 2.5 - 2.5 - 2.5 - 2.5 - ns 10 tADCH ADSC Hold Time 0.5 - 0.5 - 0.5 - 0.5 - ns 11 tCES CE1, CE2, CE3 Setup Time 2.5 - 2.5 - 2.5 - 2.5 - ns 12 tCEH CE1, CE2, CE3 Hold Time 0.5 - 0.5 - 0.5 - 0.5 - ns 13 tWS GW, BWE X Setup Time 2.5 - 2.5 - 2.5 - 2.5 - ns 14 tWH GW, BWE X Hold Time 0.5 - 0.5 - 0.5 - 0.5 - ns 15 tCYC Clock Cycle Time 10 - 11.1 - 13.3 - 15 - ns 16 tKH Clock High Pulse Width 5 - 6 - 6 - 6 - ns 17 tKL Clock Low Pulse Width 5 - 6 - 6 - 6 - ns 18 tKQ Clock to Output Valid - 5 - 6 - 7 - 8 ns 19 tKHZ Clock to Output High-Z 2 10 2 11.1 2 13.3 2 15 ns 1 20 tKLZ Clock to Output Low-Z 0 - 0 - 0 - 0 - ns 1 21 tKX Clock to Output Invalid 2 - 2 - 2 - 2 - ns 1 22 tOE Output Enable to Output Valid - 5 - 6 - 7 - 8 ns 23 tOHZ Output Enable to Output High-Z - 5 - 6 - 7 - 8 ns V63C31321024 Rev. 0.3 October 1997 8 Note 1 V63C31321024 MOSEL VITELIC AC Characteristics (Cont'd) 5 6 7 8 # Sym Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Note 24 tOLZ Output Enable to Output Low-Z 0 - 0 - 0 - 0 - ns 1 25 tOX Output Enable to Output Invalid 0 - 0 - 0 - 0 - ns 26 tZZS ZZ Standby Time - 100 - 100 - 100 - 100 ns 2 27 tZZR ZZ Recover Time 100 - 100 - 100 - 100 - ns 3 Notes: 1. These parameters are sampled but not 100% tested. 2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active. 3. ADSC and ADSP should not be accessed for at least 100 ns after chip leaves ZZ Mode. V63C31321024 Rev. 0.3 October 1997 9 V63C31321024 MOSEL VITELIC Waveforms of Read Cycle Single Read Pipelined Read Burst Read tCYC(15) Unselected CLK tKH(16) tADSH(8) tADSS(7) tKL(17) ADSP is block by CE1 inactive ADSP tADCS(9) ADSC Initiated Read tADCH(10) ADSC tADVS(5) Suspend Burst tADVH(6) ADV tAS(1) tAH(2) A[14:0] RD1 RD2 tWS(13) RD3 tWH(14) GW tWS(13) tWH(14) BWE BW[3:0] tCES(11) CE1 masks ADSP tCEH(12) CE1 tCES(11) Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC tCEH(12) CE2 tCES(11) tCEH(12) CE3 tOE(22) tOHZ(23) OE tOLZ(24) DATA OUT HIGH-Z tKX(21) tOX(25) 1a tKHZ(19) 2a 2b tKX(21) 2c 2d 3a tKHZ(19) DATA IN HIGH-Z DON'T CARE V63C31321024 Rev. 0.3 October 1997 tKQ(18) UNDEFINED 10 V63C31321024 MOSEL VITELIC Waveforms of Write Cycle Single Read tCYC(15) Burst Read Write Unselected CLK tADSS(7) tADSH(8) tKH(16) tKL(17) ADSP is block by CE1 inactive ADSP tADCS(9) ADSC Initiated Write tADCH(10) ADSC tADVS(5) tADVH(6) ADV tAS(1) A[14:0] tAH(2) ADV must be inactive for ADSP write WR1 WR2 WR3 GWE allows process address (and BE = BW) to be pipelined during a writeback tWS(13) tWH(14) GW tWS(13) tWH(14) BWE tWS(13) tWH(14) BW[3:0] WR1 tCES(11) WR2 WR3 CE1 masks ADSP tCEH(12) CE1 tCES(11) Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC tCEH(12) CE2 tCES(11) tCEH(12) CE3 OE DATA OUT HIGH-Z tDS(3) DATA IN HIGH-Z DON'T CARE V63C31321024 Rev. 0.3 October 1997 tDH(4) 2a 1a 2b UNDEFINED 11 2c 2d 3a V63C31321024 MOSEL VITELIC Waveforms of Read/Write Cycle Single Read Burst Read Single Write tCYC(15) Unselected CLK tKH(16) tADSH(8) tADSS(7) tKL(17) ADSP is block by CE1 inactive ADSP tADCS(9) ADSC initiated Read tADCH(10) ADSC tADVS(5) Suspend Burst tADVH(6) ADV tAS(1) A[14:0] tAH(2) RD1 WR1 tWS(13) RD2 tWH(14) GW tWS(13) tWH(14) BWE tWS(13) tWH(14) BW[3:0] WR1 tCES(11) CE masks ADSP tCEH(12) CE1 tCES(11) CE2 and CE3 only sampled with ADSP or ADSC tCEH(12) CE2 tCES(11) Unselected with CE3 tCEH(12) CE3 tOE(22) tOHZ(23) OE DATA OUT HIGH-Z 2a tKLZ(20) tKQ(18) DATA IN tKX(21) tOH tOLZ(24) tKHZ(19) HIGH-Z DON'T CARE V63C31321024 Rev. 0.3 October 1997 tDH(4) tDS(3) 1a UNDEFINED 12 2b 2c 2d tKHZ(19) V63C31321024 MOSEL VITELIC Waveforms of ZZ and RD Cycle Snooze with Data Retention Single Read tCYC(15) Read CLK tADSS(7) tADSH(8) tKH(4) tKL(17) ADSP ADSC tADVS(5) tADVH(6) ADV tAS(1) A[14:0] tAH(2) RD1 RD2 tWS(13) tWH(14) GW tWS(13) tWH(14) BWE tWS(13) tWH(14) BW[3:0] RD tCES(11) RD RD tCEH(12) CE1 tCES(11) tCEH(12) CE2 tCES(11) tCEH(12) CE3 tOE(22) tOHZ(23) OE tOH tOLZ(24) DATA OUT HIGH-Z 1a tKLZ(20) tKX(21) DATA IN HIGH-Z tKQ(18) tKHZ(19) tZZS(26) tZZR(27) ZZ DON'T CARE V63C31321024 Rev. 0.3 October 1997 UNDEFINED 13 V63C31321024 MOSEL VITELIC Package Diagram 100-pin PQFP (Q) 0.134 MAX. [3.404 MAX.] TOP VIEW 0.026 TYP. [0.660 TYP.] 0.010 MIN. [0.254 MIN.] 81 100 1 Unit in inches [mm] 80 0.012 0.7870.004 [19.9900.102] +0.003 -0.002 [0.305 +0.076 ] -0.051 +0.008 -0.007 +0.203 [23.190 ] -0.178 0.913 30 51 31 50 0.5510.004 [13.9950.102] 0.144 MAX [3.657 MAX] 0.6770.008 [17.1950.203] DETAIL "F" 0.004 MIN. [0.102 MIN.] GAGE PLANE SEATING PLANE 0.035 0.006 [0.889 0.152] SEE DETAIL "F" 0.063 TYP. [1.600 TYP.] V63C31321024 Rev. 0.3 October 1997 14 V63C31321024 MOSEL VITELIC 100-pin TQFP (TQ) 0.0550.002 [1.3970.051] TOP VIEW 0.026 TYP. [0.65 TYP.] 0.002 MIN. [0.051 MIN.] 81 100 1 Unit in inches [mm] 80 0.0130.002 [0.0330.051] 0.7870.004 [19.9900.102] 0.886 0.006 [21.9960.152] 30 51 31 50 0.5510.004 [13.9950.102] 0.063 MAX [1.600 MAX] 0.6300.006 [16.0020.152] DETAIL "F" 0.004 MIN. [0.102 MIN.] GAGE PLANE SEATING PLANE 0.0240.006 [0.6090.152] SEE DETAIL "F" 0.039 TYP. [0.990 TYP.] V63C31321024 Rev. 0.3 October 1997 15 MOSEL VITELIC WORLDWIDE OFFICES V63C31321024 U.S.A. TAIWAN JAPAN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 011-886-2-545-1213 FAX: 011-886-2-545-1209 WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 011-81-43-299-6000 FAX: 011-81-43-299-6555 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 011-852-665-4883 FAX: 011-852-664-7535 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 011-886-35-783344 FAX: 011-886-35-792838 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN CENTRAL & SOUTHEASTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 10/97 Printed in U.S.A. (c) Copyright 1997, MOSEL VITELIC Inc. U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG MOSEL VITELIC PHONE: 011-852-665-4883 FAX: 011-852-664-7535 TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 011-886-2-545-1213 FAX: 011-886-2-545-1209 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461