ADVANCE INFORMATION PI74ALVTC16268 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2.5V 12-Bit to 24-Bit Registered Bus Exchanger with 3-State Outputs Product Features Product Description PI74ALVTC16268 is designed for low voltage operation, VDD = 1.65V to 3.6V Supports Live Insertion 3.6V I/O Tolerant Inputs and Outputs Bus Hold High Drive, 32/64mA @ 3.3V Uses patented noise reduction circuitry Power-off high impedance inputs and outputs Industrial operation at 40C to +85C Packages available: 56-pin 240-mil wide plastic TSSOP (A56) 56-pin 173-mil wide plastic TVSOP (K56) Pericom Semiconductors PI74ALVTC series of logic circuits are produced using the Companys advanced 0.35 micron CMOS technology, achieving industry leading speed. Logic Block Diagram For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the Bport. Data flow is controlled by the active-low output enables (OEA, OEB). These control terminals are registered so bus direction changes are synchronous with CLK. LE1B LE2B LEA1B LEA2B OE2B The PI74ALVTC16268, 12-bit-to-24-bit registered bus exchanger, is designed for 1.65V to 3.6V VDD operation. The device is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock- enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. 2 27 30 55 56 29 OE1B OEA SEL 1 28 G1 A1 8 C1 23 1 1 1D 1B1 C1 6 1D C1 2B1 To ensure the high-impedance state during power up or power down, OE should be tied to VDD through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. The family offers both I/O Tolerant, which allows it to operate in mixed 1.65/3.6V systems, and Bus Hold, which retains the data inputs last state preventing floating inputs and eliminating the need for pullup/ down resistors. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE should be tied to VDD through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. Because OE is being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. 1D C1 1D TO 11 OTHER CHANNELS 1 PXXXX 04/12/00 ADVANCE INFORMATION PI74ALVTC16268 2.5V 12-Bit To 24-Bit Registerd Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Configuration Pin Description Pin Name OE CLK SEL CLKEN A,1B,2B GND VDD Description Output Enable Input (Active LOW) Clock Select (Active Low) Clock Enable (Active Low) 3-State Outputs Ground Power Truth Tables(1) Output Enable INPUTS OUTPUTS CLK OEA OEB A 1B,2B H H Z Z H L Z Active L H Active Z L L Active Active A to B STORAGE (OEB = L) CLKENA1 H L L X X INPUTS CLKENA2 H X X L L CLK X OUTPUTS 1B 2B 1B0(2) 2B0(3) L(2) X H(2) X X L X H A X L H L H B to A STORAGE (OEA = L) INPUTS CLKEN1B CLKEN2B CLK SEL 1B 2B Outputs A H X X H X X A0(3) X H X L X X A0(3) L L H L X L L L H H X H X L L X L L X L L X H H OEA CLKEN1B 1 2 56 55 OEB CLKENA2 2B3 GND 2B2 3 4 5 54 53 52 2B4 GND 2B5 2B1 VDD A1 6 7 8 51 50 49 2B6 VDD 2B7 A2 A3 9 10 48 47 2B8 2B9 GND A4 A5 11 12 13 46 45 44 GND 2B10 2B11 A6 A7 A8 14 15 16 56-Pin 43 A, K 42 41 2B12 1B12 1B11 A9 GND 17 18 40 39 1B10 GND A10 A11 A12 19 20 21 38 37 36 1B9 1B8 1B7 VDD 1B1 1B2 22 23 24 35 34 33 VDD 1B6 1B5 GND 1B3 25 26 32 31 GND 1B4 CLKEN2B SEL 27 28 30 29 CLKENA1 CLK Notes: 1. H = High Signal Level, L = Low Signal Level, X = Irrelevant, Z = High Impedance, = Transition, Low to High 2. Two CLK edges are needed to propagate data 3. Output level before indicated steady state input conditions were established. 2 PXXXX 04/12/00 ADVANCE INFORMATION PI74ALVTC16268 2.5V 12-Bit To 24-Bit Registerd Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage Range, VDD ........................................................ 0.5V to 4.6V Input Voltage Range, VI ................................................................ 0.5V to 4.6V Output Voltage Range, VO (3-Stated) .............................. 0.5V to 4.6V Output Voltage Range, VO(1) (Active) .................. 0.5V to VDD +0.5V DC Input Diode Current (IIK) VI < 0V ........................................ 50mA DC Output Diode Current (IOK) VO < 0V ................................................................................... 50mA VO > VDD .................................................................................................... 50mA DC Output Source/Sink Current (IOH/IOL) ........................... 4/128mA DC VDD or GND Current per Supply Pin (ICC or GND) ............ 100mA Storage Temperature Range, Tstg .................................. 65C to150C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions(2) M in. M ax. Operating 1.65 3.6 Data Retention Only 1.2 3.6 2.0 VDD Supply voltage VIH High- level input voltage VDD = 2.7V to 3.6V VIL Low- level input voltage VDD = 2.7V to 3.6V VI Input voltage VO Output voltage Output current in IOH/IOL t/v TA 0.8 0.3 3.6 Active State 0 VDD Off State 0 3.6 VDD = VDD = VDD = VDD = Operating free- air temperature V 32/64 24 18 6 mA 0 10 ns/V -40 85 C 3.0V to 3.6V 3.0V to 3.6V 2.3V to 2.7V 1.65V to 1.95V Input transistion rise or fall rate(3) Units Notes: 1. Absolute maximum of IO must be observed. 2. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 As measured between 0.8V and 2.0V, VDD = 3.0V. 3 PXXXX 04/12/00 ADVANCE INFORMATION PI74ALVTC16268 2.5V 12-Bit To 24-Bit Registerd Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted) DC Characteristics (2.7V<VDD 3.6V) Parame te r VIK VOH Input Clamp Diode HIGH Level Output Voltage Conditions VDD IIK = -18mA 3.0 2.7 - 3.6 VDD 0.2 IOH = -12mA 2.7 2.2 IOH = -18mA M ax. 3.0 2.2 2.0 IOL = 100A 2.7 - 3.6 0.2 IOL = 12mA 2.7 0.4 IOL = 18mA IOL = 24mA 0.45 3.0 0.5 IOL = 64mA 0.55 II Input Leakage Current VI = VDD, or GND 3.6 5.0 IOZ 3- State Output Leakage VO = 3.6V 2.7 10 IOFF Power- OFF Leakage Current VI or VO 3.6V 0 10 Bus Hold Current A or B Outputs VI = 0.8V 3.0 VI = 2.0V VI = 0 to 3.6V IDD IDD Quiescent Supply Current Increase in IDD per input V 0.4 IOL = 32mA IHOLD Units 2.4 IOH = -32mA LOW Level Output Voltage Typ. 1.2 IOH = -100A IOH = -24mA VOL M in. 3.6 VI = VDD or GND 75 75 A 500 50 VDD (VI,VO) 3.6V VIH = VDD 0.6V, Other inputs at VDD or Gnd 4 2.7 - 3.6 50 400 PXXXX 04/12/00 ADVANCE INFORMATION PI74ALVTC16268 2.5V 12-Bit To 24-Bit Registerd Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted; continued from previous page) DC Characteristics (2.3V VDD 2.7V) De s cription VIK Parame te rs Input Clamp Diode Conditions IIK = 18mA HIGH Level Output Voltage 2.3 - 2.7 IOH = 12mA 2.3 IOH = 18mA IOL = 100A VOL LOW Level Output Voltage M in. Typ. 2.3 IOH = 100A VOH VDD M ax. 1.2 VDD 0.2 1.8 1.7 2.3 - 2.7 0.2 IOL = 12mA IOL = 18mA 2.3 0.5 0.55 II Input Leakage Current VI = VDD or GND 2.7 5.0 IOZ 3- State Output Leakage VO = 3.6V 2.3 10 IOFF Power- OFF Leakage Current VI or VO 3.6V 0 10 Bus Hold Current A or B Outputs VI = 0.7V IDD DD Quiescent Supply Current Increase in IDD per input V 0.4 IOL = 24mA IHOLD(1) Units 2.5 VI = 1.7V VI = VDD or GND VDD (VI,VO) 3.6V VIH = VDD 0.6V, Inputs at VDD or Gnd 90 90 40 2.3 - 2.7 A A 40 400 Note: 1. Not Guaranteed 5 PXXXX 04/12/00 ADVANCE INFORMATION PI74ALVTC16268 2.5V 12-Bit To 24-Bit Registerd Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted; continued from previous page) DC Characteristics (1.65V VDD 1.95V) De s cription Parame te rs VIK Input Clamp Diode VOH HIGH Level Output Voltage VOL LOW Level Output Voltage Conditions VDD IIK = 18mA M in. Typ. 1.65 IOH = 100A M ax. 1.2 1.65- 1.95 VDD 0.2 IOH = 6mA 1.4 IOL = 100A V 1.65 0.2 IOL = 6mA 0.3 II Input Leakage Current VI = VDD or GND 1.95 5.0 IOZ 3- State Output Leakage VO = 3.6V 1.65 10 IOFF Power- OFF Leakage Current VI = VO 3.6V 0 10 IHOLD(1) IDD DD Bus Hold Current A or B Outputs Quiescent Supply Current Increase in IDD per input Units VI = 0.4 1.65 VI = 1.3 VI = VDD or GND 50 A 50 20 VDD (VI,VO) 3.6V VI = VDD 06V, Other inputs at VDD or Gnd 1.65- 1.95 20 400 Note: 1. Not Guaranteed 6 PXXXX 04/12/00 ADVANCE INFORMATION PI74ALVTC16268 2.5V 12-Bit To 24-Bit Registerd Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements Over Operating Range Parame te rs De s cription VDD = 1.8V 0.15V M in. fclock Clock frequency tW Pulse duration, CLK high or low tSU th Setup time Hold time M ax. VDD = 2.5V 0.2V M in. M ax. VDD = 3.3V 0.3V M in. 180 M ax. 180 3 3 A data before CLK 3.4 3 B data before CLK 1.0 0.8 SEL before CLK 1.3 1.1 CLKENA1 or CLKENA2 before CLK 2.8 2.5 CLKENB1 or CLKENB2 before CLK 2.5 2.2 OE before CLK 3.2 2.8 A data after CLK 0.2 0.1 B data after CLK 1.3 1.1 SEL after CLK 1.0 0.8 CLKENA1 or CLKENA2 after CLK 0.4 0.3 CLKENB1 or CLKEB2 after CLK 0.5 0.4 OE after CLK 0.2 0.1 Units MHz ns Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 7 PXXXX 04/12/00 ADVANCE INFORMATION PI74ALVTC16268 2.5V 12-Bit To 24-Bit Registerd Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics Over Operating Range Parame te r From (Input) To (Output) VDD = 1.8V 0.15V M in. fmax M ax. VDD = 2.5V 0.2V M in. VDD = 3.3V 0.3V M ax. 180 tpd CLK ten tdis CLK ten tdis M in. Units M ax. 180 MHz B 1.8 5.4 1.3 3.8 A(1B) 1.7 4.8 1.2 3.4 B(2B) 1.8 4.8 1.3 3.4 A(SEL) 2.4 5.8 1.7 4.1 B 2.6 6.1 1.8 4.3 B 2.5 5.9 1.8 4.1 A 1.8 5.1 1.3 3.6 A 2.1 5.0 1.5 3.5 ns Notes: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Operating Characteristics, TA= 25C Parame te rs Cpd Power Dissipation Capacitance Outputs Enabled Outputs Disabled Te s t Conditions CL = 0pF, f = 10 MHz VDD = 2.5V 0.2V VDD = 3.3V 0.3V Typical Typical TBD TBD Units pF TBD TBD 8 PXXXX 04/12/00 ADVANCE INFORMATION PI74ALVTC16268 2.5V 12-Bit To 24-Bit Registerd Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Circuits and Switching Waveforms Switch Position Parameter Measurement Information (VDD = 1.65V - 3.6V) 3.3V/2.5V VDD 2 x VDD R1 500 From Output Under Test Open 30pF CL RL 500 Te s t S1 tPD Open tPLZ/tPZL 2 x VDD tPHZ/tPZH GND GND Pulse Width (See Note A) VDD Low-High-Low Pulse VDD/2 0V tW 1.8V VDD 2 x VDD VDD High-Low-High Pulse R1 1k From Output Under Test VDD/2 0V Open 30pF CL RL 1k GND Propagation Delay (See Note A) VDD VDD/2 0V Input tPLH Setup, Hold, and Release Timing Data Input tSU Timing Input tH tPHL VDD VDD/2 VOL Output tPHL VDD VDD/2 0V tPLH VDD VDD/2 0V Opposite Phase Input Transition VDD VDD/2 0V Enable Disable Timing VDD Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tr 2ns, tf 2ns, measured from 10% to 90%, unless otherwise specified. D. The outputs are measured one at a time with one transition per measurement. Output Control (Active LOW) VDD/2 0V tPLZ tPZL VDD Output Waveform 1 S1 at 2xVDD (see Note B) Output Waveform 2 S1 at GND VDD VDD/2 +0.15V tPZH VOL tPHZ -0.15V VOH VDD/2 0V (see Note B) Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 9 PXXXX 04/12/00