1
®
FN3705.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2004-2006. All Rights Reserved
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HA-5002/883
Monolithic, Wideband, High Slew Rate,
High Output Current Buffer
The HA-5002/883 is a monolithic, wideband, high slew rate,
high output current, buffer amplifier.
Utilizing the advantages of the Intersil Dielectric Isolation
technologies, the HA-5002/883 current buffer offers
1300V/µs slew rate typically and 1000V/µs minimum with
110MHz of bandwidth. The ±100mA minimum output current
capability is enhanced by a 3Ω output impedance.
The monolithic HA-5002/883 will replace the hybrid LH0002
with corresponding performance increases. These
characteristics range from the 3MΩ (typ) input impedance to
the increased output voltage swing. Monolithic design
technologies have allowed a more precise buffer to be
developed with more than an order of magnitude smaller
gain error. The voltage gain is 0.98 guaranteed minimum
with a 1kΩ load and 0.96 minimum with a 100Ω load.
The HA-5002/883 will provide many present hybrid users
with a higher degree of reliability and at the same time
increase overall circuit performance.
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Voltage Gain (RL = 1kΩ) . . . . . . . . . . . . . . . . . . 0.98 (Min)
0.995 (Typ)
(RL = 100Ω) . . . . . . . . . . . . . . . . . 0.96 (Min)
0.971 (Typ)
• High Input Impedance . . . . . . . . . . . . . . . . . . 1.5MΩ (Min)
3MΩ (Typ)
• Low Output Impedance . . . . . . . . . . . . . . . . . . . 5Ω (Max)
3Ω (Typ)
• Very High Slew Rate . . . . . . . . . . . . . . . . .1000V/µs (Min)
1300V/µs (Typ)
• Wide Small Signal Bandwidth . . . . . . . . . . .110MHz (Typ)
• High Output Current . . . . . . . . . . . . . . . . . . . .100mA (Min)
• High Pulsed Output Current . . . . . . . . . . . . . 400mA (Max)
• Monolithic Dielectric Isolation Construction
• Replaces Hybrid LH0002
Applications
• Line Driver
• Data Acquisition
• 110MHz Buffer
• High Power Current Booster
• High Power Current Source
• Sample and Holds
• Radar Cable Driver
• Video Products
Ordering Information
PART
NUMBER
PART
MARKING
TEMP
RANGE
(°C) PACKAGE
HA2-5002/883 HA2-5002/883 -55 to +125 8 Pin Can
HA4-5002/883 HA4-5002/883 -55 to +125 20 Ld Ceramic LCC
Pinouts
HA-5002/883 (CLCC)
TOP VIEW
HA-5002/883
(METAL CAN)
TOP VIEW
4
5
6
7
8
9101112
13
3 2 1 20 19
15
14
18
17
16
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V2-
V1+
NC
OUT
IN
V2+
V1-
2
4
6
1
3
7
5
8
OUT
NC NC
IN
V1-
V2-V2+
V1+
Data Sheet January 5, 2006
2FN3705.4
January 5, 2006
Absolute Maximum Ratings Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .44V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equal to Supplies
Peak Output Current (50ms On, 1s Off) . . . . . . . . . . . . . . . . . .±400mA
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<4000V
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . .-55°C to +125°C
Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . ±12V to ±15V
RL ≥ 100Ω
Thermal Resistance θJA (°C/W) θJC (°C/W)
Metal Can Package . . . . . . . . . . . . . . . 160 70
Ceramic LCC Package. . . . . . . . . . . . . 80 30
Package Power Dissipation Limit at +75°C for TJ ≤ +175°C
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625mW
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25W
Package Power Dissipation Derating Factor Above +75°C
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.3mW/°C
Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . .12.5mW/°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379
for details.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VSUPPLY = ±12V and ±15V, RSOURCE = 50Ω, CLOAD ≤ 10pF, VIN = 0V, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE (°C) MIN MAX UNITS
Input Offset
Voltage
VIO1 VSUP = ±15V 1 +25 -20 20 mV
2, 3 +125, -55 -30 30 mV
VIO2 VSUP = ±12V 1 +25 -20 20 mV
2, 3 +125, -55 -30 30 mV
Input Bias Current IB1 VSUP = ±15V, RS = 1kΩ1+25-77µA
2, 3 +125, -55 -10 10 µA
IB2 VSUP = ±12V, RS = 1kΩ1+25-77µA
2, 3 +125, -55 -10 10 µA
Voltage Gain 1 +AV1VSUP = ±12V, RL = 1kΩ,
VIN = 10V
1 +25 0.98 - V/V
2, 3 +125, -55 0.98 - V/V
-AV1VSUP = ±12V, RL = 1kΩ,
VIN = -10V
1 +25 0.98 - V/V
2, 3 +125, -55 0.98 - V/V
Voltage Gain 2 +AV2VSUP = ±12V, RL = 100Ω,
VIN = 10V
1 +25 0.96 - V/V
-AV2VSUP = ±12V, RL = 100Ω,
VIN = -10V
1 +25 0.96 - V/V
Voltage Gain 3 +AV3VSUP = ±15V, RL = 100Ω,
VIN = 10V
1 +25 0.96 - V/V
-AV3VSUP = ±15V, RL = 100Ω,
VIN = -10V
1 +25 0.96 - V/V
Voltage Gain 4 +AV4VSUP = ±15V,
RL = 1kΩ,
VIN = +10V
1 +25 0.99 - V/V
2, 3 +125, -55 0.99 - V/V
-AV4VSUP = ±15V,
RL = 1kΩ,
VIN = -10V
1 +25 0.99 - V/V
2, 3 +125, -55 0.99 - V/V
HA-5002/883
3FN3705.4
January 5, 2006
Output Voltage
Swing
+VOUT1 VSUP = ±15V,
RL = 100Ω,
VIN = +15V
1 +25 10 - V
2, 3 +125, -55 10 - V
-VOUT1 VSUP = ±15V,
RL = 100Ω,
VIN = -15V
1 +25 - -10 V
2, 3 +125, -55 - -10 V
+VOUT2 VSUP = ±15V,
RL = 1kΩ,
VIN = +15V
1 +25 10 - V
2, 3 +125, -55 10 - V
-VOUT2 VSUP = ±15V,
RL = 1kΩ,
VIN = -15V
1 +25 - -10 V
2, 3 +125, -55 - -10 V
+VOUT3 VSUP = ±12V,
RL = 1kΩ,
VIN = +12V
1 +25 10 - V
2, 3 +125, -55 10 - V
-VOUT3 VSUP = ±12V,
RL = 1kΩ,
VIN = -12V
1 +25 - -10 V
2, 3 +125, -55 - -10 V
Output Current +IOUT1 VSUP = ±15V,
VOUT = +10V
1 +25 100 - mA
2, 3 +125, -55 100 - mA
-IOUT1 VSUP = ±15V,
VOUT = -10V
1 +25 - -100 mA
2, 3 +125, -55 - -100 mA
+IOUT2 VSUP = ±12V,
VOUT = +10V
1 +25 100 - mA
2, 3 +125, -55 100 - mA
-IOUT2 VSUP = ±12V,
VOUT = -10V
1 +25 - -100 mA
2, 3 +125, -55 - -100 mA
Power Supply
Rejection Ratio
+PSRR1∆VSUP = ±5V,
V+ = +20V, V- = -15V,
V+ = +10V, V- = -15V
1 +25 54 - dB
2, 3 +125, -55 54 - dB
-PSRR1∆VSUP = ±5V,
V+ = +15V, V- = -20V,
V+ = +15V, V- = -10V
1 +25 54 - dB
2, 3 +125, -55 54 - dB
+PSRR2∆VSUP = ±5V,
V+ = +17V, V- = -12V,
V+ = +7V, V- = -12V
1 +25 54 - dB
2, 3 +125, -55 54 - dB
-PSRR2∆VSUP = ±5V,
V+ = +12V, V- = -17V,
V+ = +12V, V- = -7V
1 +25 54 - dB
2, 3 +125, -55 54 - dB
Power Supply
Current
+ICC1VSUP = ±15V,
VOUT = 0V
1+25-10mA
2, 3 +125, -55 - 10 mA
-ICC1VSUP = ±15V,
VOUT = 0V
1+25-10-mA
2, 3 +125, -55 -10 - mA
+ICC2VSUP = ±12V,
VOUT = 0V
1+25-10mA
2, 3 +125, -55 - 10 mA
-ICC2VSUP = ±12V,
VOUT = 0V
1+25-10-mA
2, 3 +125, -55 -10 - mA
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: VSUPPLY = ±12V and ±15V, RSOURCE = 50Ω, CLOAD ≤ 10pF, VIN = 0V, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE (°C) MIN MAX UNITS
HA-5002/883
4FN3705.4
January 5, 2006
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank. See AC Specifications in Table 3
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VSUPPLY = ±15V or ±12V, RLOAD = 1kΩ, CLOAD ≤ 10pF, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS NOTES TEMPERATURE
(°C) MIN MAX UNITS
Input Resistance RIN1 VSUP = ±15V 1 +25 1.5 - MΩ
RIN2 VSUP = ±12V 1 +25 1.5 - MΩ
Slew Rate +SR1VSUP = ±15V,
VOUT = -5V to +5V
1 +25 1000 - V/µs
+125, -55 1000 - V/µs
-SR1VSUP = ±15V,
VOUT = +5V to -5V
1 +25 1000 - V/µs
+125, -55 1000 - V/µs
+SR2VSUP = ±12V,
VOUT = -5V to +5V
1 +25 1000 - V/µs
+125, -55 1000 - V/µs
-SR2VSUP = ±12V,
VOUT = +5V to -5V
1 +25 1000 - V/µs
+125, -55 1000 - V/µs
Rise and Fall Time TRVSUP = ±15V or ±12V,
VOUT = 0 to +500mV
1, 2 +25 - 10 ns
1, 2 +125, -55 - 10 ns
TFVSUP = ±15V or ±12V,
VOUT = 0 to -500mV
1, 2 +25 - 10 ns
1, 2 +125, -55 - 10 ns
Overshoot +OS VSUP = ±12V or ±15V,
VOUT = 0 to +500mV
1+25-30%
+125, -55 - 30 %
-OS VSUP = ±12V or ±15V,
VOUT = 0 to -500mV
1+25-30%
+125, -55 - 30 %
Quiescent Power
Consumption
PC1VSUP = ±15V,
VIN = 0V,
IOUT = 0mA
1, 3 +25 - 300 mW
+125, -55 - 300 mW
PC2VSUP = ±12V,
VIN = 0V,
IOUT = 0mA
1, 3 +25 - 240 mW
+125, -55 - 240 mW
Output Resistance ROUT1 VSUP = ±12V 1 +25 - 5 Ω
ROUT2 VSUP = ±12V 1 +25 - 5 Ω
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters
are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon
data from multiple production runs which reflect lot to lot and within lot variation.
2. Measured between 10% and 90% points.
3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.)
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1)
Interim Electrical Parameters (Pre Burn-In) 1
Final Electrical Test Parameters 1 (Note 1), 2, 3
Group A Test Requirements 1, 2, 3
Groups C and D Endpoints 1
NOTE:
1. PDA applies to Subgroup 1 only.
HA-5002/883
5FN3705.4
January 5, 2006
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): V1-
TRANSISTOR COUNT: 27
PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5002/883
V1-IN
OUT
V2+
V1+ (ALT)
V1- (ALT)
V2-
V1+
HA-5002/883
6FN3705.4
January 5, 2006
HA-5002/883
Ceramic Leadless Chip Carrier Packages (CLCC)
D
j x 45oD3
B
h x 45o
AA1
E
LL3
e
B3
L1
D2
D1
e1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010 E HS S
0.010 E F
SS
-E-
0.007 E FM S HS
B1
-H-
-F-
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.060 0.100 1.52 2.54 6, 7
A1 0.050 0.088 1.27 2.23 -
B-----
B1 0.022 0.028 0.56 0.71 2 , 4
B2 0.072 REF 1.83 REF -
B3 0.006 0.022 0.15 0.56 -
D 0.342 0.358 8.69 9.09 -
D1 0.200 BSC 5.08 BSC -
D2 0.100 BSC 2.54 BSC -
D3 -0.358-9.092
E 0.342 0.358 8.69 9.09 -
E1 0.200 BSC 5.08 BSC -
E2 0.100 BSC 2.54 BSC -
E3 -0.358-9.092
e 0.050 BSC 1.27 BSC -
e1 0.015 - 0.38 - 2
h 0.040 REF 1.02 REF 5
j 0.020 REF 0.51 REF 5
L 0.045 0.055 1.14 1.40 -
L1 0.045 0.055 1.14 1.40 -
L2 0.075 0.095 1.91 2.41 -
L3 0.003 0.015 0.08 0.38 -
ND 5 5 3
NE 5 5 3
N20 203
Rev. 0 5/18/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the dr awing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is packag e height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3705.4
January 5, 2006
Metal Can Packages (Can)
NOTES:
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
2. Measured from maximum diameter of the product.
3. α is the basic spacing from the centerline of the tab to terminal 1
and β is the basic spacing of each lead or lead position (N -1
places) from α, looking at the bottom of the package.
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
Øb
ØD2
Øek1
k
β
Øb1
BASE AND
SEATING PLANE
F
Q
ØD ØD1
L1
L2
REFERENCE PLANE
L
A
α
Øb2
Øb1
BASE METAL LEAD FINISH
SECTION A-A
A
A
N
e1
C
L
2
1
T8.C MIL-STD-1835 MACY1-X8 (A1)
8 LEAD METAL CAN PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.165 0.185 4.19 4.70 -
Øb 0.016 0.019 0.41 0.48 1
Øb1 0.016 0.021 0.41 0.53 1
Øb2 0.016 0.024 0.41 0.61 -
ØD 0.335 0.375 8.51 9.40 -
ØD1 0.305 0.335 7.75 8.51 -
ØD2 0.110 0.160 2.79 4.06 -
e 0.200 BSC 5.08 BSC -
e1 0.100 BSC 2.54 BSC -
F - 0.040 - 1.02 -
k 0.027 0.034 0.69 0.86 -
k1 0.027 0.045 0.69 1.14 2
L 0.500 0.750 12.70 19.05 1
L1 - 0.050 - 1.27 1
L2 0.250 - 6.35 - 1
Q 0.010 0.045 0.25 1.14 -
α45o BSC 45o BSC 3
β45o BSC 45o BSC 3
N8 84
Rev. 0 5/18/94
HA-5002/883
