©1999 Integrated Device Technology, Inc.
JUNE 1999
DSC 2674/9
1
IDT7052S/L
Functional Block Diagram
HIGH-SPEED
2K x 8 FourPortTM
STATIC RAM
Features
◆◆
◆◆
◆High-speed access
– Military: 25/35ns (max.)
– Commercial: 20/25/35ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT7052S
Active: 750mW (typ.)
Standby: 7.5mW (typ.)
– IDT7052L
Active: 750mW (typ.)
Standby: 1.5mW (typ.)
◆◆
◆◆
◆True FourPort memory cells which allow simultaneous
access of the same memory locations
◆◆
◆◆
◆Fully asynchronous operation from each of the four ports:
P1, P2, P3, P4
◆◆
◆◆
◆Versatile control for write-inhibit: separate BUSY input to
control write-inhibit for each of the four ports
◆◆
◆◆
◆Battery backup operation—2V data retention
MEMORY
ARRAY
COLUMN
I/O
PORT 1
ADDRESS
DECODE
LOGIC
PORT 2
ADDRESS
DECODE
LOGIC
COLUMN
I/O
COLUMN
I/O
PORT 4
ADDRESS
DECODE
LOGIC
PORT 3
ADDRESS
DECODE
LOGIC
COLUMN
I/O
R/WP1
I/O0P1-I/O7P1
CEP1
OEP1
A0P1 -A
10P1
BUSYP2
R/WP2
CEP2
OEP2
2674 drw 01
I/O0P2-I/O7P2
A0P2 -A
10P2
BUSYP1
R/WP4
I/O0P4-I/O7P4
CEP4
OEP4
A0P4 -A
10P4
BUSYP3
R/WP3
CEP3
OEP3
I/O0P3-I/O7P3
A0P3 -A
10P3
BUSYP4
◆◆
◆◆
◆TTL-compatible; single 5V (±10%) power supply
◆◆
◆◆
◆Available in 120 pin and 132 pin Thin Quad Flatpacks and
108 pin PGA
◆◆
◆◆
◆Military product compliant to MIL-PRF-38535 QML
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Description
The IDT7052 is a high-speed 2K x 8 FourPort™ Static RAM designed
to be used in systems where multiple access into a common RAM is
required. This FourPort Static RAM offers increased system performance
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access
is required in the same cycle.
The IDT7052 is also designed to be used in systems where on-chip
hardware port arbitration is not needed. This part lends itself to those
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
2
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configurations(1,2,3)
2674 drw 02
OE
P2
A7
P2
A8
P2
A5
P2
80
I/O2
P1 I/O3
P1 I/O6
P1 VCC GND I/O2
P4 I/O5
P4
A3
P2
A4
P2
A5
P3 A7
P3
A8
P3 OE
P3
A0
P2
A1
P3
A1
P2
A0
P3
77 74 72 69 68 65 63 60
A3
P3
A4
P3
83 78 76 73 70 67 64 61 5984 56
8687
8890
9192
9495
9796
10099
103101
105104
2
1
5
4
7
8
10
12
13
17
16
21
19
25
22
28
24
32
31 34
35 37
39 40
44 43
48 46
52 49
55 51
IDT7052G
G108-1(4)
108-Pin PGA
Top View(5)
ABCDEFGHJKLM
81 57 54
53
82 79 75 71 66 62 58 50
R/W
P2 NC NC R/W
P3
BUSY
P2 BUSY
P3
A6
P2 CE
P3
A2
P3
A2
P2 A6
P3 A2
P4
A1
P4
A9
P3
A9
P2
CE
A1
P1
A2
P1
33
36
38
41
42
45
47
3 6 9 111415182023
29 30
26 27
85
89
93
98
102
106
107
108
NC
P1 GND
A5
P1 A3
P1 A0
P1
A6
P1 A4
P1
VCC
CE
P1
OE
P1 I/O0
P1
A8
P1
A9
P1
A7
P1
R/W
P1
BUSY I/O1
P1
VCC VCC VCC
GND I/O6
P4
I/O4
P1 I/O7
P1 I/O0
P2 I/O2
P2 I/O4
P2 I/O6
P2 I/O1
P3 I/O3
P3 I/O5
P3 I/O7
P3 I/O3
P4 I/O4
P4
I/O5
P1 NC I/O1
P2 I/O3
P2 I/O5
P2 I/O7
P2 I/O0
P3 I/O2
P3 I/O4
P3 I/O6
P3 I/O0
P4 I/O1
P4
A0
P4 A3
P4 A5
P4
A4
P4 A6
P4
GND P4
A7P4
A8
P4 NC P4
A9
P4
OE P4
R/W
GND P4
I/O7P4
BUSY
GND
CE
12
11
10
09
08
07
06
05
04
03
02
01
A10
P1
A10
P2 A10
P3
A10
P4
INDEX
systems which cannot tolerate wait states or are designed to be able to
externally arbitrate or withstand contention when all ports simultaneously
access the same FourPort RAM location.
The IDT7052 provides four independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. It is the user’s responsibility to
ensure data integrity when simultaneously accessing the same memory
location from all ports. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low power standby
power mode.
Fabricated using IDT’s CMOS high-performance technology, this
FourPort SRAM typically operates on only 750mW of power. Low-power
(L) versions offer battery backup data retention capability, with each port
typically consuming 50µW from a 2V battery.
The IDT7052 is packaged in a ceramic 108-pin Pin Grid Array (PGA),
120-pin Thin Quad Flatpack (TQFP) and 132-pin Plastic Quad Flatpack
(PQF). Military grade product is manufactured in compliance with the latest
revision of MIL-PRF-38535 QML, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
N/C
N/C
OEP2
BUSYP2
A0P1
A1P1
A2P1
A3P1
A4P1
A5P1
A6P1
A10P1
VCC
A7P1
A8P1
A9P1
N/C
CEP1
R/WP1
OEP1
BUSYP1
I/O0P1
I/O1P1
I/O2P1
I/O3P1
GND
I/O4P1
I/O5P1
N/C
N/C
N/C
I/O
6P1
I/O
7P1
N/C
V
CC
I/O
0P2
I/O
1P2
I/O
2P2
GND
I/O
3P2
I/O
4P2
I/O
5P2
V
CC
I/O
6P2
I/O
7P2
N/C
I/O
0P3
I/O
1P3
V
CC
I/O
2P3
I/O
3P3
I/O
4P3
GND
I/O
5P3
I/O
6P3
I/O
7P3
V
CC
I/O
0P4
I/P
1P4
N/C
N/C
N/C
BUSYP3
A0P4
A1P4
A2P4
A3P4
A4P4
A5P4
A6P4
A10P4
GND
A7P4
A8PR
A9P4
N/C
CEP4
R/WP4
OEP4
BUSYP4
GND
I/O7P4
I/O6P4
I/O5P4
GND
I/O4P4
I/O3P4
I/O2PR
N/C
N/C
CE
P2
R/W
P2
N/C
A
9P2
A
8P2
A
7P2
A
10P2
A
6P2
A
5P2
A
4P2
A
3P2
A
2P2
A
1P2
A
0P2
N/C
A
0P3
A
1P3
A
2P3
A
3P3
A
4P3
A
5P3
A
6P3
A
10P3
A
7P3
A
8P3
A
9P3
N/C
OE
P3
CE
P3
R/W
P3
2674 drw 04
IDT7052PF
PN120-1(4)
120-Pin Thin Quad Flatpack
Top View(5)
Pin Configurations(1,2,3) (con't.)
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. PQ132-1 package body is approximately
.95 in x .95 in x .14 in.
PN120-1 package body is approximately
14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
6. The side of the package containing pin1 may have a bevelled edge in place of the indicator dot..
IDT7052PQF
PQ132-1(4)
132-Pin Plastic Quad Flatpack
Top View(5,6)
1
17 117
116
18
5051 83 84
N/C
OEP2
BUSYP2
N/C
A0P1
A1P1
A2P1
A3P1
A4P1
A5P1
A6P1
A7P1
A8P1
A9P1
N/C
VCC
N/C
CEP1
R/WP1
OEP1
BUSYP1
N/C
I/O0P1
I/O1P1
I/O2P1
I/O3P1
I/O4P1
I/O5P1
N/C
GND
N/C
N/C
I/O2P4
I/O3P4
I/O4P4
I/O5P4
I/O6P4
I/O7P4
N/C
N/C
GND
N/C
GND
N/C
CEP4
R/WP4
OEP4
BUSYP4
N/C
A0P4
A1P4
A2P4
A3P4
A4P4
A5P4
A6P4
A7P4
A8P4
A9P4
GND
N/C
N/C
BUSYP3
N/C
2674 drw 03
A10P4
A10P1
N/C
A9P2
A8P2
A7P2
A6P2
A5P2
A4P2
A3P2
A2P2
A1P2
A0P2
N/C
N/C
N/C
CEP2
CEP3
OEP3
N/C
N/C
A0P3
A1P3
A2P3
A4P3
A5P3
A6P3
A7P3
A8P3
A9P3
A3P3
A10P3
A10P2
I/O5P3
I/O6P1
I/O7P1
N/C
VCC
N/C
I/O0P2
I/O1P2
I/O2P2
I/O3P2
I/O4P2
I/O5P2
GND
VCC
I/O0P3
I/O1P3
I/O2P3
I/O3P3
I/O4P3
I/O6P3
I/O7P3
I/O0P4
I/O1P4
N/C
VCC
GND
N/C
N/C
VCC
N/C
N/C
I/O7P2
R/WP2
R/WP3
I/O6P2
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
4
Pin Configurations(1,2)
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP only
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
the output signals switch from 0V to 3V or from 3V to 0V.
Maximum Operating
Temperature and Supply Voltage(1, 2)
Recommended DC Operating
Conditions
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This is the parameter TA.
2 . Industrial temperature: for specific speeds, packages and powers, contact your
sales office
Symbol
Pin Name
A
0
P1 - A
10
P1 Address Line s - Port 1
A
0
P2 - A
10
P2 Address Line s - Port 2
A
0
P3 - A
10
P3 Address Line s - Port 3
A
0
P4 - A
10
P4 Address Line s - Port 4
I/O
0
P1 - I/O
7
P1 Data I/ O - Po rt 1
I/O
0
P2 - I/O
7
P2 Data I/ O - Po rt 2
I/O
0
P3 - I/O
7
P3 Data I/ O - Po rt 3
I/O
0
P4 - I/O
7
P4 Data I/ O - Po rt 4
R/W P1 Rea d/ Write - Port 1
R/W P2 Rea d/ Write - Port 2
R/W P3 Rea d/ Write - Port 3
R/W P4 Rea d/ Write - Port 4
GND Ground
CE P1 Chip Enabl e - Port 1
CE P2 Chip Enabl e - Port 2
CE P3 Chip Enabl e - Port 3
CE P4 Chip Enabl e - Port 4
OE P 1 Outp ut Enable - P ort 1
OE P 2 Outp ut Enable - P ort 2
OE P 3 Outp ut Enable - P ort 3
OE P 4 Outp ut Enable - P ort 4
BUSY P1 Write Disab le - Port 1
BUSY P2 Write Disab le - Port 2
BUSY P3 Write Disab le - Port 3
BUSY P4 Write Disab le - Port 4
VCC Power
2674 tbl 01
Symbol
Rating
& Industrial
Military
Unit
VTERM(2) Terminal Vo ltage
wi th Re s pe c t to
GND
-0.5 to +7.0 -0.5 to +7.0 V
TBIAS Temperature
Und e r B ias -55 to +125 -65 to +135 oC
TSTG Storage
Temperature -55 to +125 -65 to +150 oC
IOUT DC Outp ut Current 50 50 mA
2674 tbl 02
Grade
Ambient
Temperature
GND
Vcc
Military -55OC to +125 OC0V5.0V
+ 10%
Commercial 0OC to + 70OC0V5.0V
+ 10%
Industrial -40OC to +85OC0V5.0V
+ 10%
2674 tbl 04
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Inp ut Cap acitanc e V
IN
= 0V 9 pF
C
OUT
Outp ut Cap acitance V
OUT
= 0V 10 pF
2674 tbl 03
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC Sup ply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
VIH Inp ut Hi g h Vo l tag e 2.2 ____ 6.0(2) V
VIL Inp ut Lo w Vo l tag e -0. 5(1) ____ 0.8 V
2 6 74 tb l 05
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
5
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. VCC = 5V, TA = +25°C and are not production tested.
3. f = 0 means no address or control lines change.
4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
5. For the case of one port, divide the appropriate current above by four.
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5,6) (VCC = 5.0V ± 10%)
Symbol
Parameter
Condition
7052X20
Com'l Only
7052X25
Com'l &
Military
7052X35
Com'l &
Military
Unit
Version
Typ.
(2)
Max.
Typ.
(2)
Max.
Typ.
(2)
Max.
ICC1 Operating Power
Supply Current
(All P orts Active )
CE
= VIL
Outputs Ope n
f =
0(3)
COM'L. S
L150
150 300
250 150
150 300
250 150
150 300
250 mA
MIL. &
IND. S
L
____
____
____
____
150
150 360
300 150
150 360
300
ICC2 Dynamic Op erating
Current
(All P orts Active )
CE
= VIL
Outputs Ope n
f =
fMAX(4)
COM'L. S
L240
210 370
325 225
195 350
305 210
180 335
290 mA
MIL. &
IND. S
L
____
____
____
____
225
195 400
340 210
180 395
330
ISB Standby Current
(Al l P orts - TTL Le v el
Inputs)
CE
= V
IH
f =
fMAX(4) COM'L. S
L70
60 95
80 45
40 85
70 40
35 75
60 mA
MIL. &
IND. S
L
____
____
____
____
45
40 115
85 40
35 110
80
ISB1 Full Standby Current
(Al l P o rts - Al l CMO S
Le v e l Inputs )
All Ports
CE
> VCC - 0.2V
VIN > VCC - 0. 2V o r
VIN < 0.2V, f = 0 (3)
COM'L. S
L1.5
0.3 15
1.5 1.5
0.3 15
1.5 1.5
0.3 15
1.5 mA
MIL. &
IND. S
L
____
____
____
____
1.5
0.3 30
4.5 1.5
0.3 30
4.5
2674 tbl 06
Symbol
Parameter
Test Conditions
7052S
7052L
Unit
Min.
Max.
Min.
Max.
|ILI| Inp ut Leak age Curre nt(1) VCC = 5. 5V, VIN = 0V to VCC ___ 10 ___ 5µA
|ILO| Outp ut Le akag e Current CE = VIH, VOUT = 0V to VCC ___ 10 ___ 5µA
VOL Outp ut Lo w Vo ltage IOL = 4mA ___ 0.4 ___ 0.4 V
VOH Outp ut Hig h Vo ltag e IOH = -4mA 2.4 ___ 2.4 ___ V
2674 tbl 07
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
6
Low VCC Data Retention Waveform
Data Retention Characteristics Over All Temperature Ranges(4)
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
NOTES:
1. VCC = 2V, TA = +25°C
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
4. Industrial temperature: For other speeds, packages and powers contact your sales office.
AC Test Conditions
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
Symbol
Parameter
Test Condition
Min.
Typ.
(1)
Max.
Unit
VDR VCC
for Data Retentio n VCC = 2
V
2.0 ___ ___ V
ICCDR Da ta Re tenti on Cu rre nt CE
> VHC
VIN > VHC or < VLC
Com'l. ___ 25 600 µA
Mil. & Ind. ___ 25 1800
tCDR(3) C hip De se le ct to Data Rete ntio n Time 0 ___ ___ ns
tR(3) Op eratio n Reco v ery Time tRC(2) ___ ___ ns
2674 tb l 08 a
DATA RETENTION MODE
VCC
CE
2674 drw 05
4.5V
tCDR tR
VIH
VDR
VIH
4.5VVDR 2V
≥
347Ω
893Ω
30pF
5V
2674 drw 06
DATAOUT
347Ω
893Ω
5pF*
5V
DATAOUT
,
Inp ut P ul se Le v e l s
Inp ut Ris e /Fal l Time s
Inp ut Timing Re fere nc e Le ve ls
Outp ut Re fe re nce Le ve ls
Outp ut Lo ad
GND to 3.0V
5ns M ax .
1.5V
1.5V
Fi g ure s 1 and 2
2674 tb l 08b
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
7
2674 drw 08
tAOE
tLZ tHZ
DATAOUT
CE
tACE
VALID DATA
OE
CURRENT ICC
ISB
tPU
50%
tLZ tPD
50%
tHZ
2674 drw 07
tAA
tOH tOH
DATAOUT
ADDRESS
tRC
DATA VALIDPREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 1, Any Port(1)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(3,4)
NOTES:
1. Transition is measured ±200mV from Low or High-Impedance voltage with the Output Test Load (Figure 2)
2. This parameter is guaranteed by device characterization but is not production tested.
3. 'X' in part number indicates power rating (S or L)
4. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Read Cycle No. 2, Any Port(1,2)
NOTES:
1. R/W = VIH, OE = VIL and CE = VIL.
NOTES:
1. R/W = VIH for Read Cycles.
2. Addresses valid prior to or coincident with CE transition LOW.
7052X20
Co m'l On ly
7052X25
Com'l &
Military
7052X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
RE AD CYCLE
tRC Read Cyc le Time 20 ____ 25 ____ 35 ____ ns
tAA Address Access Time ____ 20 ____ 25 ____ 35 ns
tACE Chip Enable A cce ss Time ____ 20 ____ 25 ____ 35 ns
tAOE Outp ut Enab le Ac ce ss Time ____ 10 ____ 15 ____ 25 ns
tOH Outp ut Hol d fro m Ad d re ss Change 0 ____ 0____ 0____ ns
tLZ Outp ut Lo w-Z Time (1,2) 5____ 5____ 5____ ns
tHZ Outp ut High-Z Time(1,2) ____ 12 ____ 15 .____ 15 ns
tPU Chip Enabl e to Powe r Up Time(2) 0____ 0____ 0____ ns
tPD Chi p Dis ab le to P o we r Do wn Tim e (2) ____ 20 ____ 25 ____ 35 ns
2674 tbl 09
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(7,8)
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers
to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement
does not apply and the write pulse can be as short as the specified tWP. Specified for OE = VIH (refer to “Timing Waveform of Write Cycle”, Note 8).
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. To ensure that the write cycle is inhibited on port "A" during contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port.
6. To ensure that a write cycle is completed on port "A" after contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port.
7. 'X' in part number indicates power rating.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7052X20
Co m'l On ly
7052X25
Com'l &
Military
7052X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRIT E C YC LE
tWC Write Cycle Time 20 ____ 25 ____ 35 ____ ns
tEW Chip Enable to End-of-Write(3) 15 ____ 20 ____ 30 ____ ns
tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns
tAS Address Set-up Time 0 ____ 0____ 0____ ns
tWP Write Pulse Width(3) 15 ____ 20 ____ 30 ____ ns
tWR Write Recovery Time 0 ____ 0____ 0____ ns
tDW Data Valid to End-of-Write 15 ____ 15 ____ 20 ____ ns
tHZ Outp ut High-Z Time(1,2) ____ 15 ____ 15 ____ 15 ns
tDH Data Ho ld Tim e 0 ____ 0____ 0____ ns
tWZ Write Enab le to Output in High-Z(1,2) ____ 12 ____ 15 ____ 15 ns
tOW Output A c ti v e from E nd - o f-Wri te(1,2) 0____ 0____ 0____ ns
tWDD Write Pulse to Data Delay(4) ____ 35 ____ 45 ____ 55 ns
tWDD Write Data Valid to Read Data Del ay (4) ____ 30 ____ 35 ____ 45 ns
BUSY
INPUT TI MING
tWB Write to BUSY(5) 0____ 0____ 0____ ns
tWH Write Hold After BUSY(6) 15 ____ 15 ____ 20 ____ ns
2674 tbl 10
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
9
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5)
NOTES:
1. R/W or CE = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL.
3. tWR is measured from the earlier of CE or R/W = VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production
tested.
8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed
on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
CE
2674 drw 09
tAW
tAS
tWR
tDW
DATAIN
ADDRESS
tWC
R/W
tWP
DATAOUT
tWZ (7)
(4) (4)
(2)
tOW
OE
tHZ
tLZ
(7)
tHZ
(6)
(3)
(9)
tDH
(7)
CE
2674 drw 10
tAW
tAS tWR
tDW
DATAIN
ADDRESS
tWC
R/W
tEW
tDH
(9)
(6) (2) (3)
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
10
Timing Waveform of Write with Port-to-Port Read(1,2,3)
Functional Description
The IDT7052 provides four ports with separate control, address, and
I/O pins that permit independent access for reads or writes to any location
in memory. These devices have an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into standby mode when not selected (CE
= VIH). When a port is enabled, access to the entire memory array is
permitted. Each port has its own Output Enable control (OE). In the read
mode, the port’s OE turns on the output drivers when set LOW. READ/
WRITE conditions are illustrated in the table below.
Timing Waveform of Write with BUSY Input
NOTES:
1. BUSY is aserted on Port "B" blocking R/W"B" until BUSY"B" goes HIGH.
Truth Table I  Read/Write Control(3)
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z "= High Impedance
2 . If BUSY = VIL, write is blocked.
3 . For valid write operation, no more than one port can write to the same address
location at the same time.
NOTES:
1. Assume BUSY input = VIH and CE = VIL for the writing port.
2. OE = VIL for the reading ports.
3. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port.
2674 drw 11
ADDR"A"
tWC
DATA"B"
MATCH
tWP
R/W"A"
DATAIN"A"
ADDR"B"
tDH
VALID
MATCH
VALID
tDDD
tWDD
tDW
2674 drw 12
R/W"A"
BUSY"B"
tWP
tWH
tWB
R/W"B" (1)
,
Any Port
(1)
R/
WCE OE
D
0-7
Function
X H X Z Port Deselected: Power-Down
XHX Z CE
P1=CE
P2=CE
P3=CE
P4=VIH
Power Down Mode ISB or ISB1
LLXDATA
IN Data o n p o rt writte n into m em o ry (2)
HLLDATA
OUT Data in memory output on port
X X H Z Outputs Disabled
2 674 tb l 11
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
11
Ordering Information
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
A
Power 999
Speed A
Package A
Process/
Temperature
Range
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
G
PQF
PF
108-Pin Pin Grid Array (G108-1)
132-Pin Plastic Quad Flatpack (PQ132-1)
120-Pin Thin Quad Plastic Flatpack (PN120-1)
20
25
35
XXXX
Device
Type
IDT
Speed
in nanoseconds
2674 drw 13
L
SLow Power
Standard Power
7052 16K (2K x 8) FourPort RAM
Commercial Only
Commercial & Military
Commercial & Military
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
1/18/99: Initiated datasheet document history
Converted to new format
Cosmetic typographical corrections
Added additional notes to pin configurations
6/4/99: Changed drawing format
Page1 Corrected DSC number
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www.idt.com