[AK5397] AK5397 32-Bit Stereo Premium ADC 1. Genaral Description The AK5397 is a high performance 32-bit stereo ADC that achieves class leading performance of 127dB dynamic range for stereo output. This is a flagship addition to AKM's VERITA series of product in the Audio 4 ProTM family. The AK5397 integrates a newly developed circuit by VELVET SOUNDTM technology achieving rich sound field and bass representation that realizes a music playback experience with less distortion. The 2. class leading performance with a maximum 768kHz PCM output is supported for digital output and newly developed 32-bit digital filters are integrated for the best sound quality. The AK5397 is suitable for digital video recorders and high quality sound studio mixers for recording and editing high-resolution sound sources. Feartures Advanced multi bit Architecture ADC Resolution: 32bit Sampling Rate: 8kHz ~ 768kHz Full Differential Inputs S/(N+D): 108dB DR, S/N: 127dB (Mono Mode: 130dB) Sharp Roll Off Digital Filter (GD=41.5/fs) Passband: 0 ~ 21.82kHz (@ fs=48kHz) Passband Ripple: +0.00010/-0.00015dB Stopband Attenuation: 100dB Short Delay Digital Filter (GD=12.5/fs) Passband: 0 ~ 22.22kHz (@ fs=48kHz) Passband Ripple: +0.055/-0.015dB Stopband Attenuation: 93dB Minimum Phase Digital Filter (GD=3.5/fs) Passband: 0 ~ 21.75kHz(@ fs=48kHz) Passband Ripple: +0.04/-0.02dB Stopband Attenuation: 93dB Master / Slave Mode Master Clock: 256fs/512fs (Normal Speed; 8kHz~48kHz) 256fs (Double Speed; 48Hz ~ 96kHz) 128fs (Quad Speed; 96kHz ~ 192kHz) 64fs (Octal Speed; 192kHz ~ 384kHz) 32fs (Hex Speed; 384kHz ~ 768kHz) Audio Interface Format: 32bit MSB justified, I2S compatible or TDM Cascade TDM I/F: 8ch/48kHz, 4ch/96kHz, 4ch/192kHz Digital HPF for Offset Cancel Overflow Flag Power Supply: 4.75 ~ 5.25V(Analog), 3.0 ~ 3.6V(Digital) Power Dissipation: 455mW Ta = -10 ~ 70 C Package: 44-pin LQFP 014011535-E-00 2014/11 -1- [AK5397] 3. Block Diagram AVDD AVSS SDFI L VCOM LIN+ LIN- Common Voltage Delta-Sigma Modulator VREFHL VREFLL Voltage Reference VREFLR VREFHR Voltage Reference RINRIN+ HPFE DVDD DVSS MONO DIF Delta-Sigma Modulator TDM1 TDM0 SDM2 Decimation Filter HPF Audio Interface Decimation Filter HPF PDN SDM1 TDMIN2 TDMIN1 OVF SDTO1 SDTO2 LRCK BICK MCLK MSN CKS2 CKS1 CKS0 Figure 1. Block Diagram 014011535-E-00 2014/11 -2- [AK5397] 4. Table of Contents 1. 2. 3. 4. 5. Genaral Description .......................................................................................................................... 1 Feartures ........................................................................................................................................... 1 Block Diagram .................................................................................................................................. 2 Table of Contents ............................................................................................................................. 3 Pin Configurations and Functions .................................................................................................... 4 Pin Configurations .............................................................................................................................. 4 Functions ............................................................................................................................................ 5 Handling of Unused Pin ..................................................................................................................... 6 6. Absolute Maximum Ratings .............................................................................................................. 7 7. Recommended Operating Conditions .............................................................................................. 7 8. Electrical Characteristics .................................................................................................................. 8 Analog Characteristics ....................................................................................................................... 8 Sharp Roll-Off Filter Characteristics .................................................................................................. 9 Short Delay Filter Characteristics .................................................................................................... 11 Minimum Phase Filter Characteristics ............................................................................................. 12 Digital Filter Plot ............................................................................................................................... 14 DC Characteristics ........................................................................................................................... 18 Switching Characteristics ................................................................................................................. 18 Timing Diagrams .............................................................................................................................. 21 9. Functional Descriptions .................................................................................................................. 23 System Clock ................................................................................................................................... 23 Master Mode/Slave Mode ................................................................................................................ 24 Audio Interface Format..................................................................................................................... 25 Cascade TDM Mode ........................................................................................................................ 29 Digital High Pass Filter ..................................................................................................................... 33 Overflow Detection ........................................................................................................................... 33 Mono Mode....................................................................................................................................... 33 Digital Output Data ........................................................................................................................... 34 Power Down & Reset ....................................................................................................................... 36 10. SYSTEM DESIGN .......................................................................................................................... 37 11. PACKAGE ....................................................................................................................................... 41 Outline Dimensions .......................................................................................................................... 41 Material & Lead finish....................................................................................................................... 42 MARKING ......................................................................................................................................... 42 12. Ordering Guide ............................................................................................................................... 42 13. Revision History .............................................................................................................................. 43 IMPORTANT NOTICE ........................................................................................................................... 44 014011535-E-00 2014/11 -3- [AK5397] 5. Pin Configurations and Functions TEST2 AVSS MONO TDM1 TDM0 TDMIN2 TDMIN1 DVDD DVSS 31 30 29 28 27 26 25 23 RIN32 24 RIN+ 33 Pin Configurations VREFLR 34 22 MSN VREFHR 35 21 DIF AVSS 36 20 SDFIL AVDD 37 19 SDM2 TOUT 38 18 SDM1 VCOM 39 17 OVF TEST3 40 16 SDTO2 AVDD 41 15 SDTO1 AVSS 42 14 LRCK VREFHL 43 13 BICK VREFLL 44 12 MCLK AK5397EQ 5 6 7 8 9 10 11 HPFE CKS1 PDN DVDD DVSS CKS2 4 AVSS CKS0 3 TEST1 2 LIN+ LIN- 1 Top View Figure 2. Pin Configurations 014011535-E-00 2014/11 -4- [AK5397] Functions No. Pin Name Power I/O Function 1 LIN+ A I Lch Positive Analog Input Pin 2 LINA I Lch Negative Analog Input Pin Test Pin 3 TEST1 A This pin must be connected to AVSS. 4 AVSS A - Analog Ground Pin, 0V HPF Enable Pin 5 HPFE D I "L": Disable, "H" Enable 6 CKS0 D I Clock Mode Select #0 Pin 7 CKS1 D I Clock Mode Select #1 Pin 8 CKS2 D I Clock Mode Select #2 Pin Power down & Reset pin 9 PDN D I "L": All blocks are powered-down and reset. "H": Normal Operation 10 DVDD D - Digital Power Supply Pin, 3.0V ~ 3.6V 11 DVSS D - Digital Ground Pin, 0V 12 MCLK D I Master Clock Input Pin Serial Data Clock Pin 13 BICK D I/O When PDN pin = "L", BICK outputs "L" in master made. L/R Channel Select Clock Pin 14 LRCK D I/O When PDN pin = "L", LRCK outputs "L" in master made. Serial Data Output #1 Pin (Sharp Roll Off Filter Output) 15 SDTO1 D O When PDN pin = "L", SDTO1 outputs "L". Serial Data Output #2 Pin (Short Delay or Minimum Phase Filter Output) 16 SDTO2 D O When PDN pin = "L", SDTO2 outputs "L". Analog Input Overflow Detect Pin 17 OVF D O This pin goes to "H" if any analog inputs overflows When the PDN pin = "L", the OVF pin outputs "L". SDTO1 Output Mute Pin 18 SDM1 D I This function is synchronized with LRCK edges. "L": Normal Operation, "H": "L" output SDTO2 Output Mute Pin 19 SDM2 D I This function is synchronized with LRCK edges. "L": Normal Operation, "H": "L" output SDTO2 Digital Filter Select Pin 20 SDFIL D I "L": Short Delay, "H": Minimum Phase Audio Interface Format Pin 21 DIF D I "L": 32bit MSB justified, "H": 32bit I2S Compatible Master/Slave mode Select Pin 22 MSN D I "L": Slave mode, "H": Master mode 23 DVSS D - Digital Ground Pin, 0V 24 DVDD D - Digital Power Supply Pin, 3.0 ~ 3.6V 25 TDMIN1 D I TDM Data Input #1 Pin 26 TDMIN2 D I TDM Data Input #2 Pin TDM I/F Format Enable Pin 27 TDM0 D I "L": Normal Mode, "H": TDM Mode TDM I/F BICK Frequency Select Pin 28 TDM1 D I "L": 256fs, "H": 128fs 014011535-E-00 2014/11 -5- [AK5397] No. Pin Name Power I/O Function Stereo/Mono mode Select Pin "L": Stereo mode, "H": Mono mode 30 AVSS A - Analog Ground Pin, 0V Test Pin 31 TEST2 A I This pin must be connected to AVSS. 32 RINA I Rch Negative Analog Input Pin 33 RIN+ A I Rch Positive Analog Input Pin Rch Negative Reference Voltage Input Pin 34 VREFLR A I Normally connected to AVSS. Rch Positive Reference Voltage Input Pin, 4.75 ~ 5.25V Normally connected to the VREFLR pin with a large electrolytic 35 VREFHR A I capacitor and a 0.1F ceramic capacitor. 36 AVSS A - Analog Ground Pin, 0V 37 AVDD1 A - Analog Power Supply Pin, 4.75 ~ 5.25V TEST Pin 38 TOUT A I This pin must be Connected to AVSS. Common Voltage Output Pin, AVDD/2 39 VCOM A O Normally connected to AVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic capacitor. Test Pin 40 TEST3 A I This pin must be connected to AVSS. 41 AVDD2 A - Analog Power Supply Pin, 4.75 ~ 5.25V 42 AVSS A - Analog Ground Pin, 0V Lch Positive Reference Voltage Input Pin, 4.75 ~ 5.25V Normally connected to the VREFLL pin with a large electrolytic 43 VREFHL A I capacitor and a 0.1F ceramic capacitor. Lch Negative Reference Voltage Input Pin 44 VREFLL A I Normally connected to AVSS. Note 1. All digital input pins must not be left floating. 29 MONO D I Handling of Unused Pin The unused I/O pin must be processed as below. Classification Digital Analog Pin Name TEST1/2/3, TOUT TDMIN1/2 SDTO1, SDTO2, OVF LIN+, LINRIN+, RIN- Setting This pin must be connected to AVSS. This pin must be connected to DVSS. This pin must be open. Connect the LIN+ pin and the LIN- pin. Connect the RIN+ pin and the RIN- pin. 014011535-E-00 2014/11 -6- [AK5397] 6. Absolute Maximum Ratings (AVSS=DVSS=0V; Note 2) Parameter Symbol Min. Max. Unit AVDD 0.3 Power Analog 6.0 V DVDD Supplies: Digital 4.6 V 0.3 |AVSS-DVSS| (Note 3) 0.3 V GND1 Input Current, Any Pin Except Supplies IIN mA 10 Analog Input Voltage (Note 4) VINA AVDD+0.3 V 0.3 Digital Input Voltage (Note 5) VIND DVDD+0.3 V 0.3 Ambient Temperature (power applied) Ta 70 10 C Storage Temperature Tstg 150 65 C Note 2. All voltages with respect to ground. Note 3. AVSS and DVSS must be connected to the same analog ground plane. Note 4. VREFHL, VREFLL, VREFHR, VREFLR, LIN+, LIN-, RIN+, RIN-, TEST1-3 and TOUT pins. Note 5. CKS0, CKS1, CKS2,PDN, SDM1, SDM2, SDFIL, TDMIN1, TDMIN2, MCLK, BICK, LRCK, DIF, MSN, HPFE, MONO, TDM0, TDM1pins WARING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operating Conditions (AVSS=DVSS=0V; Note 2) Parameter Power Supplies: (Note 6) Voltage Reference (Note 9) Symbol Min. Analog AVDD 4.75 Digital DVDD 3.0 "H" voltage reference (Note 7) VREFHL/R AVDD-0.5 "L" voltage reference (Note 8) VREFLL/R (VREFHL/R) - (VREFLL/R) AVDD-0.5 VREF Note 2. All voltages with respect to ground. Note 6. AVDD and DVDD are powered up simultaneously. Note 7. VREFHL pin, VREFHR pin Note 8. VREFLL pin, VREFLR pin Note 9. VREFLL and VREFLR pins must be connected to AVSS. Analog input voltage scales with voltage of {(VREFH) - (VREFL)}. Vin (typ.) = 2.8 x {(VREFH) - (VREFL)} / 5 [V] Typ. 5.0 3.3 AVSS - Max. 5.25 3.6 AVDD AVDD Unit V V V V V WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. 014011535-E-00 2014/11 -7- [AK5397] 8. Electrical Characteristics Analog Characteristics (Ta = 25C; AVDD=5.0V; DVDD=3.3V; AVSS=DVSS=0V; VREFHL=VREFHR=AVDD, VREFLL=VREFLR=AVSS; fs=48kHz, 96kHz, 192kHz; BICK=64fs; Signal Frequency=1kHz; 32bit Data; Measurement frequency=10Hz20kHz at fs=48kHz, 40Hz40kHz at fs=96kHz, 80Hz80kHz at fs=192kHz; External circuit: Figure 41 "Analog input buffer circuit example 2"; unless otherwise specified) Parameter Min. Typ. Max. Unit Resolution 32 Bits Analog Input Characteristics: S/(N+D) fs=48kHz 92 100 -1dBFS dB -1dBFS (Note 10) BW=20kHz 108 dB -2dBFS (Note 10) 110 dB -20dBFS 102 dB -60dBFS 64 fs=96kHz -1dBFS 92 99 dB BW=40kHz -1dBFS (Note 10) 107 dB -20dBFS 99 dB -60dBFS 60 fs=192kHz -1dBFS 91 99 dB BW=80kHz -1dBFS (Note 10) 106 dB -20dBFS 94 dB -60dBFS 54 Dynamic Range (-60dBFS with A-weighted) (Stereo Mode) 122 127 dB (Mono Mode) 125 130 dB S/N (A-weighted) fs=48kHz (Stereo Mode) 122 127 dB (Mono Mode) 125 130 dB S/N (Without A-weighted) fs=96kHz (Stereo Mode) 115 120 dB S/N (Without A-weighted) fs=192kHz (Stereo Mode) 111 116 dB Input Resistance 650 720 Interchannel Isolation 120 130 dB Interchannel Gain Mismatch 0.1 0.5 dB Gain Drift 150 ppm/C Input Voltage (Note 11) Vpp 2.6 2.8 3.0 Input DC Bias Voltage Vpp 0.382xAVDD Power Supplies: Power Supply Current AVDD + VREFHL + VREFHR 74.6 94.0 mA DVDD (fs=48kHz, MSN=H, SDM1=L, SDM2=H) 24 33 mA (fs=96kHz, MSN=H, SDM1=L, SDM2=L) 52 71 mA (fs=192kHz, MSN=H, SDM1=L, SDM2=L) 53 72 mA (fs=384kHz, MSN=H, SDM1=L, SDM2=L) 34 46 mA (fs=768kHz, MSN=H, SDM1=L, SDM2=L) 34 46 mA Power down current (AVDD + DVDD) 10 100 uA Power Supply Rejection (Note 12) 50 dB Note 10. Using the circuit as shown in Figure 40(Analog input buffer circuit example 1) Note 11. This value is (LIN+) - (LIN-) and (RIN+) - (RIN-). Input voltage is proportional to a difference between VREFP and VREFL voltages. Vin (typ.) = 2.8 x {(VREFH) - (VREFL)} / 5 [V] 014011535-E-00 2014/11 -8- [AK5397] Note 12. PSRR is applied to AVDD and DVDD with 1kHz, 20mVpp. The VREFHL/R and VREFLL/R pins held a constant voltage. Sharp Roll-Off Filter Characteristics (1) Sharp Roll-Off Filter Characteristics (fs=48kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=48kHz) Parameter Symbol Min. ADC Digital Filter (Decimation LPF): Passband (Note 13) Figure 3-(1) PB 0 Passband Ripple (Note 14) Figure 3-(3) PR -0.00015 Frequency Response -0.001dB FR (Note 14) -0.1dB -3.0dB -6.0dB Stopband (Note 14) Figure 3-(2) SB 26.17 Stopband Attenuation Figure 3-(4) SA 100 Group Delay Distortion GD Group Delay (Note 15) GD ADC Digital Filter (HPF): Frequency response -3dB FR (Note 14) -0.1dB (2) Sharp Roll-Off Filter Characteristics (fs=96kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=96kHz) Parameter Symbol Min. ADC Digital Filter (Decimation LPF): Passband (Note 13) Figure 4-(1) PB 0 Pass Band Ripple (Note 14) Figure 4-(3) PR -0.00015 Frequency Response -0.001dB FR (Note 14) -0.1dB -3.0dB -6.0dB Stopband (Note 14) Figure 4-(2) SB 52.36 Stopband Attenuation Figure 4-(4) SA 100 Group Delay Distortion GD Group Delay (Note 15) GD ADC Digital Filter (HPF): Frequency response -3dB FR (Note 14) -0.1dB - 014011535-E-00 Typ. Max. Unit 21.82 +0.00010 3072 kHz dB kHz kHz kHz kHz kHz dB 1/fs 1/fs 0.93 6.1 - Hz Hz Typ. Max. Unit 43.62 +0.00015 3072 kHz dB kHz kHz kHz kHz kHz dB 1/fs 1/fs - Hz Hz 21.93 22.54 23.62 23.99 0 41.5 43.87 45.10 47.25 47.99 0 41.4 0.93 6.1 2014/11 -9- [AK5397] (3) Sharp Roll-Off Filter Characteristics (fs=192kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=192kHz) Parameter Symbol Min. ADC Digital Filter (Decimation LPF): Passband (Note 13) Figure 5-(1) PB 0 PassBand Ripple (Note 14) Figure 5-(2) PR -0.005 Frequency Response -0.1dB FR (Note 14) -3.0dB -6.0dB Stopband (Note 14) Figure 5-(3) SB 105.60 Stopband Attenuation Figure 5-(4) SA 100 Group Delay Distortion GD Group Delay (Note 15) GD ADC Digital Filter (HPF): Frequency response -3dB FR (Note 14) -0.1dB (4) Sharp Roll-Off Filter Characteristics (fs=384kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=384kHz) Parameter Symbol Min. ADC Digital Filter (Decimation LPF): Frequency Response -0.1dB FR 0 (Note 14) -1.0B -3.0dB -6.0dB Stopband (Note 14) Figure 6-(1) SB 223.93 Stopband Attenuation Figure 6-(2) SA 83 Group Delay Distortion GD Group Delay (Note 15) GD Typ. Max. Unit 87.32 +0.006 3072 kHz dB kHz kHz kHz kHz dB 1/fs 1/fs 0.93 6.1 - Hz Hz Typ. Max. Unit 60.67 86.93 107.70 125.30 3072 kHz kHz kHz kHz kHz dB 1/fs 1/fs 89.52 94.33 95.97 0 36.3 0 10.6 (5) Sharp Roll-Off Filter Characteristics (fs=768kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=768kHz) Parameter Symbol Min. Typ. Max. Unit ADC Digital Filter (Decimation LPF): Frequency Response -0.1dB FR 0 34.01 kHz (Note 14) -1.0dB 101.51 kHz -3.0dB 163.13 kHz -6.0dB 216.16 kHz Stopband (Note 14) Figure 7-(1) 533.42 3072 KHz Stopband Attenuation Figure 7-(2) 85 dB Group Delay Distortion 0 1/fs GD Group Delay (Note 15) GD 8.4 1/fs Note 13. The definition of Passband is applied to the frequency which is within the limits of Passband Ripple. Note 14. The passband and stopband frequencies scales with fs. The reference frequency of these responses is 1kHz. Note 15. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 32bit data both of channels to the ADC output register for ADC. 014011535-E-00 2014/11 - 10 - [AK5397] Short Delay Filter Characteristics (1) Short Delay Filter Characteristics (fs=48kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=48kHz; SDFIL="L") Parameter Symbol Min. Typ. ADC Digital Filter (Decimation LPF): Passband (Note 13) Figure 8-(1) PB 0 Passband Ripple (Note 14) Figure 8-(2) PR -0.015 Frequency Response -0.1dB FR 22.40 (Note 14) -3.0dB 23.70 -6.0dB 24.28 Stopband (Note 14) Figure 8-(3) SB 27.93 Stopband Attenuation Figure 8-(4) SA 93 Group Delay Distortion GD Group Delay (Note 15) GD 12.5 ADC Digital Filter (HPF): Frequency response -3dB FR 0.93 (Note 14) -0.1dB 6.1 (2) Short Delay Filter Characteristics (fs=96kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=96kHz; SDFIL="L") Parameter Symbol Min. Typ. ADC Digital Filter (Decimation LPF): Passband (Note 13) Figure 9-(1) PB 0 Passband Ripple (Note 14) Figure 9-(2) PR -0.05 Frequency Response -0.1dB FR 44.68 (Note 14) -3.0dB 47.40 -6.0dB 48.56 Stopband (Note 14) Figure 9-(3) SB 55.90 Stopband Attenuation Figure 9-(4) SA 93 Group Delay Distortion GD Group Delay (Note 15) GD 12.4 ADC Digital Filter (HPF): Frequency response -3dB FR 0.93 (Note 14) -0.1dB 6.1 014011535-E-00 Max. Unit 22.22 +0.055 3072 kHz dB kHz kHz kHz kHz dB 1/fs 1/fs 0.1 - Hz Hz Max. Unit 44.46 +0.02 3072 kHz dB kHz kHz kHz kHz dB 1/fs 1/fs 0.075 - Hz Hz 2014/11 - 11 - [AK5397] (3) Short Delay Filter Characteristics (fs=192kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=192kHz; SDFIL="L") Parameter Symbol Min. Typ. Max. Unit ADC Digital Filter (Decimation LPF): Passband (Note 13) Figure 10-(1) PB 0 80.71 kHz Passband Ripple (Note 14) Figure 10-(2) PR -0.05 +0.02 dB Frequency Response -0.1dB PB 82.5 kHz (Note 14) -3.0dB 92.86 kHz -6.0dB 96.31 kHz Stopband (Note 14) Figure 10-(3) SB 116.67 3072 kHz Stopband Attenuation Figure 10-(4) SA 93 dB Group Delay Distortion 0.02 1/fs GD Group Delay (Note 15) GD 12.2 1/fs ADC Digital Filter (HPF): Frequency response -3dB FR 0.93 Hz (Note 14) -0.1dB 6.1 Hz Note 13. The definition of Passband is applied to the frequency which is within the limits of Passband Ripple. Note 14. The passband and stopband frequencies scales with fs. The reference frequency of these responses is 1kHz. Note 15. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 32bit data both of channels to the ADC output register for ADC. Minimum Phase Filter Characteristics (1) Minimum Phase Filter Characteristics (fs=48kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=48kHz; SDFIL="H") Parameter Symbol Min. Typ. ADC Digital Filter (Decimation LPF): Passband (Note 13) Figure 11-(1) PB 0 Passband Ripple (Note 14) Figure 11-(2) PR -0.02 Frequency Response -0.1dB FR 21.97 (Note 14) -3.0dB 23.49 -6.0dB 24.12 Stopband (Note 14) Figure 11-(3) SB 27.97 Stopband Attenuation Figure 11-(4) SA 93 Group Delay Distortion GD Group Delay (Note 15) GD 3.5 ADC Digital Filter (HPF): Frequency response -3dB FR 0.93 (Note 14) -0.1dB 6.1 014011535-E-00 Max. Unit 21.75 +0.04 3072 kHz dB kHz kHz kHz kHz dB 1/fs 1/fs 1.5 - Hz Hz 2014/11 - 12 - [AK5397] (2) Minimum Phase Filter Characteristics (fs=96kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=96kHz; SDFIL="H") Parameter Symbol Min. Typ. ADC Digital Filter (Decimation LPF): Passband (Note 13) Figure 12-(1) PB 0 Passband Ripple (Note 14) Figure 12-(2) PR -0.04 Frequency Response -0.1dB FR 43.87 (Note 14) -3.0dB 46.98 -6.0dB 48.26 Stopband (Note 14) Figure 12-(3) SB 55.96 Stopband Attenuation Figure 12-(4) SA 93 Group Delay Distortion GD Group Delay (Note 15) GD 3.4 ADC Digital Filter (HPF): Frequency response -3dB FR 0.93 (Note 14) -0.1dB 6.1 Max. Unit 43.55 +0.02 3072 kHz dB kHz kHz kHz kHz dB 1/fs 1/fs 1.5 - Hz Hz (3) Minimum Phase Filter Characteristics (fs=192kHz) (Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=192kHz; SDFIL="H") Parameter Symbol Min. Typ. Max. Unit ADC Digital Filter (Decimation LPF): Passband (Note 13) Figure 13-(1) PB 0 80.97 kHz Passband Ripple (Note 14) Figure 13-(2) PR -0.045 +0.015 dB Frequency Response -0.1dB FR 82.55 kHz (Note 14) -3.0dB 92.02 kHz -6.0dB 95.44 kHz Stopband (Note 14) Figure 13-(3) SB 115.57 3072 kHz Stopband Attenuation Figure 13-(4) SA 93 dB Group Delay Distortion 1.6 1/fs GD Group Delay (Note 15) GD 4.2 1/fs ADC Digital Filter (HPF): Frequency response -3dB FR 0.93 Hz (Note 14) -0.1dB 6.1 Hz Note 13. The definition of Passband is applied to the frequency which is within the limits of Passband Ripple. Note 14. The passband and stopband frequencies scales with fs. The reference frequency of these responses is 1kHz. Note 15. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 32bit data both of channels to the ADC output register for ADC. 014011535-E-00 2014/11 - 13 - [AK5397] Digital Filter Plot 0.00040 20.0 0.00030 0.0 -20.0 (2) 0.00010 Attenation[dB] PB Ripple[dB] 0.00020 -40.0 0.00000 (3) -0.00010 -0.00020 -60.0 (4) -80.0 -100.0 (1) -0.00030 -120.0 -0.00040 -140.0 0 8 16 24 32 40 48 Frequency[KHz] Figure 3. Sharp Roll Off Filter Normal Mode 0.00040 20.0 0.00030 0.0 -20.0 (2) 0.00010 -40.0 0.00000 -0.00010 -0.00020 -60.0 (4) (3) -80.0 Attenation[dB] PB Ripple[dB] 0.00020 -100.0 (1) -0.00030 -120.0 -0.00040 -140.0 0 16 32 48 64 80 96 Frequency[KHz] Figure 4. Sharp Roll Off Filter Double Mode 0.00800 20.0 (2) 0.0 0.00400 -20.0 0.00200 -40.0 0.00000 -60.0 (4) (3) -0.00200 -80.0 -0.00400 Attenation[dB] PB Ripple[dB] 0.00600 -100.0 -0.00600 -120.0 (1) -0.00800 -140.0 0 32 64 96 128 160 192 Frequency[KHz] Figure 5. Sharp Roll Off Filter Quad Mode 014011535-E-00 2014/11 - 14 - [AK5397] 0.40 20.0 0.00 0.0 -20.0 -0.80 -40.0 (2) (1) -1.20 -60.0 -1.60 -80.0 -2.00 -100.0 -2.40 -120.0 -2.80 -140.0 -3.20 Attenation[dB] PB Ripple[dB] -0.40 -160.0 0 64 128 192 256 320 384 Frequency[KHz] Figure 6. Sharp Roll Off Filter Octal Mode 0.40 20.0 0.00 0.0 -20.0 -0.80 -40.0 (2) (1) -1.20 -60.0 -1.60 -80.0 -2.00 -100.0 -2.40 -120.0 -2.80 -140.0 -3.20 Attenation[dB] PB Ripple[dB] -0.40 -160.0 0 128 256 384 512 640 768 Frequency[KHz] Figure 7. Sharp Roll Off Filter Hex Mode 014011535-E-00 2014/11 - 15 - [AK5397] 0.080 20.0 (2) 0.0 0.040 -20.0 0.020 -40.0 0.000 -60.0 (3) (4) -0.020 -80.0 -0.040 -100.0 (1) -0.060 Attenation[dB] PB Ripple[dB] 0.060 -120.0 -0.080 -140.0 0 8 16 24 32 40 48 Frequency[KHz] Figure 8 Short Delay Filter Normal Mode 0.080 20.0 0.060 0.0 -20.0 (2) 0.020 -40.0 0.000 (3) -60.0 (4) -0.020 -80.0 -0.040 -100.0 -0.060 Attenation[dB] PB Ripple[dB] 0.040 -120.0 (1) -0.080 -140.0 0 16 32 48 64 80 96 Frequency[KHz] Figure 9. Short Delay Filter Double Mode 0.080 20.0 0.060 0.0 -20.0 (2) 0.020 -40.0 0.000 (3) -60.0 (4) -0.020 -80.0 -0.040 -100.0 -0.060 Attenation[dB] PB Ripple[dB] 0.040 -120.0 (1) -0.080 -140.0 0 32 64 96 128 160 192 Frequency[KHz] Figure 10. Short Delay Filter Quad Mode 014011535-E-00 2014/11 - 16 - [AK5397] 0.080 20.0 0.0 (2) PB Ripple[dB] 0.040 -20.0 0.020 -40.0 0.000 (3) -60.0 (4) -0.020 -80.0 -0.040 -100.0 (1) -0.060 Attenation[dB] 0.060 -120.0 -0.080 -140.0 0 8 16 24 32 40 48 Frequency[KHz] 0.080 20.0 0.060 0.0 PB Ripple[dB] 0.040 -20.0 (2) 0.020 -40.0 0.000 -60.0 (4) (3) Attenation[dB] Figure 11. Minimum Phase Filter Normal Mode -0.020 -80.0 -0.040 -100.0 -0.060 -120.0 (1) -0.080 -140.0 0 16 32 48 64 80 96 Frequency[KHz] 0.080 20.0 0.060 0.0 0.040 -20.0 (2) 0.020 -40.0 0.000 (3) -60.0 (4) -0.020 -80.0 -0.040 -100.0 -0.060 Attenation[dB] PB Ripple[dB] Figure 12. Minimum Phase Filter Double Mode -120.0 (1) -0.080 -140.0 0 32 64 96 128 160 192 Frequency[KHz] Figure 13. Minimum Phase Filter Quad Mode 014011535-E-00 2014/11 - 17 - [AK5397] DC Characteristics (Ta= -10~70C; AVDD=4.75~5.25V; DVDD=3.03.6V) Parameter Symbol Min. Typ. Max. Unit High-Level Input Voltage (Note 5) VIH 70%DVDD V Low-Level Input Voltage (Note 5) VIL 30%DVDD V High-Level Output Voltage (Iout=-100A) VOH V DVDD0.5 VOL 0.5 V Low-Level Output Voltage (Iout= 100A) Input Leakage Current Iin 10 A Note 5. CKS0, CKS1, CKS2,PDN, SDM1, SDM2, SDFIL, TDMIN1, TDMIN2, MCLK, BICK, LRCK, DIF, MSN, HPFE, MONO, TDM0, TDM1pin Switching Characteristics (Ta= -10~70C; AVDD=4.75~5.25V; DVDD=3.03.6V; CL=20pF) Parameter Symbol Min. Master Clock Timing fCLK 2.048 Frequency tCLKL 0.4/fCLK Pulse Width Low tCLKH 0.4/fCLK Pulse Width High LRCK Timing (Slave Mode) Normal mode (TDM1="L", TDM0="L") fs 8 LRCK Frequency Duty 45 Duty Cycle TDM256 MODE (TDM1="L", TDM0="H") fs 8 LRCK Frequency tLRH 1/256fs "H" time tLRL 1/256fs "L" time TDM128 MODE (TDM1="H", TDM0="H") fs 8 LRCK Frequency tLRH 1/128fs "H" time tLRL 1/128fs "L" time LRCK Timing (Master Mode) Normal mode (TDM1="L", TDM0="L") fs 8 LRCK Frequency Duty Duty Cycle TDM256 MODE (TDM1="L", TDM0="H") fs 8 LRCK Frequency tLRH "H" time (Note 16) TDM128 MODE (TDM1="H", TDM0="H") fs 8 LRCK Frequency tLRH "H" time (Note 16) Note 16. "L" time at I2S format. 014011535-E-00 Typ. Max. Unit 12.288 24.576 MHz ns ns 768 55 kHz % 48 kHz ns ns 192 kHz ns ns 768 kHz % 48 kHz ns 192 kHz ns 50 1/8fs 1/4fs 2014/11 - 18 - [AK5397] Parameter Audio Interface Timing (Slave mode) Normal mode (TDM1="L", TDM0="L") (8KHzfs192KHz) BICK Period (8kHz fs 48kHz) (48kHz < fs 192kHz) BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 17) BICK "" to LRCK Edge (Note 17) LRCK to SDTO1/2 (MSB) (Except I2S mode) BICK "" to SDTO1/2 Normal mode (TDM1="L", TDM0="L") (192KHzfs768KHz) BICK Period (192kHz fs 384kHz) (384kHz < fs 768kHz) BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 17) BICK "" to LRCK Edge (Note 17) BICK "" to SDTO1/2 TDM256 mode (TDM1="L", TDM0="H") BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 17) BICK "" to LRCK Edge (Note 17) BICK "" to SDTO1/2 TDMIN1/2 Setup Time TDMIN1/2 Hold Time TDM128 mode (TDM1="H", TDM0="H") (8kHz fs 96kHz) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 17) BICK "" to LRCK Edge (Note 17) BICK "" to SDTO1/2 TDMIN1/2 Setup Time TDMIN1/2 Hold Time TDM128 mode (TDM1="H", TDM0="H") (96kHz < fs 192kHz) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 17) BICK "" to LRCK Edge (Note 17) BICK "" to SDTO1/2 TDMIN1/2 Setup Time TDMIN1/2 Hold Time Symbol Min. tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/128fs 1/64fs 32 32 20 20 tBCK tBCK tBCKL tBCKH tLRB tBLR tBSD 1/64fs 1/32fs 16 16 10 10 tBCK tBCKL tBCKH tLRB tBLR tBSD tTDS tTDH 1/256fs 32 32 20 20 tBCK tBCKL tBCKH tLRB tBLR tBSD tTDS tTDH 1/128fs 32 32 20 20 tBCK tBCKL tBCKH tLRB tBLR tBSD tTDS tTDH 1/128fs 16 16 10 10 014011535-E-00 Typ. Max. Unit 20 20 ns ns ns ns ns ns ns ns 10 ns ns ns ns ns ns ns 20 10 10 20 10 10 10 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2014/11 - 19 - [AK5397] Parameter Symbol Min. Typ. Max. Audio Interface Timing (Master mode) Normal mode (TDM1="L", TDM0="L") BICK Frequency (8kHz fs 192kHz) fBCK 64fs (192kHz < fs 384kHz) fBCK 32fs BICK Duty dBCK 50 BICK "" to LRCK tMBLR 12 12 BICK "" to SDTO1/2 tBSD 20 20 Normal mode (TDM1="L", TDM0="L") (384KHz < fs 768KHz) BICK Frequency fBCK 32fs BICK Duty dBCK 50 BICK "" to LRCK tMBLR 6 6 BICK "" to SDTO1/2 tBSD 10 10 TDM256 mode (TDM1="L", TDM0="H") BICK Frequency fBCK 256fs BICK Duty (Note 18) dBCK 50 BICK "" to LRCK tMBLR 12 12 BICK "" to SDTO1/2 tBSD 20 20 TDMIN1/2 Setup Time tTDS 10 TDMIN1/2 Hold Time tTDH 10 TDM128 mode (TDM1="H", TDM0="H") (8kHz fs 96kHz) BICK Frequency fBCK 128fs BICK Duty dBCK 50 BICK "" to LRCK tMBLR 12 12 BICK "" to SDTO1/2 tBSD 20 20 TDMIN1/2 Setup Time tTDS 10 TDMIN1/2 Hold Time tTDH 10 TDM128 mode (TDM1="H", TDM0="H") (96kHz < fs 192kHz) BICK Frequency fBCK 128fs BICK Duty dBCK 50 BICK "" to LRCK tMBLR 6 6 BICK "" to SDTO1/2 tBSD 10 10 TDMIN1/2 Setup Time tTDS 10 TDMIN1/2 Hold Time tTDH 10 Reset timing tRTW 150 RSTN Pulse width Note 17. BICK rising edge must not occur at the same time as LRCK edge. Note 18. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs. 014011535-E-00 Unit Hz Hz % ns ns Hz Hz % ns ns Hz % ns ns ns ns Hz % ns ns ns ns Hz % ns ns ns ns ns 2014/11 - 20 - [AK5397] Timing Diagrams 1/fCLK VIH MCLK VIL tCLKL tCLKH Figure 14. MCLK Timing (TDM0 pin = "L" or "H") 1/fs VIH LRCK VIL tLRH tLRL Figure 15. LRCK Timing (TDM0 pin = "L" or "H") tBCK VIH BICK VIL tBCKH tBCKL Figure 16.BICK Timing (TDM0 pin = "L" or "H") VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD 50%DVDD 50%OVDD SDTO Figure 17. Audio Interface Timing (Slave mode, TDM0 pin = "L") 014011535-E-00 2014/11 - 21 - [AK5397] VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSD 50%DVDD 50%OVDD SDTO tTDS tTDH VIH TDMIN VIL Figure 18. Audio Interface Timing (Slave mode, TDM0 pin = "H") 50%DVDD 50%OVDD LRCK tMBLR dBCK 50%DVDD 50%OVDD BICK tBSD 50%DVDD 50%OVDD SDTO tTDS tTDH VIH TDMIN VIL Figure 19. Audio Interface Timing (Master mode, TDM0 pin= "H" or "L") tPDW PDN Figure 20. Reset & Calibration Timing Note: SDTO shows SDTO1 and SDTO2. TDMIN shows TDMIN1 and TDMIN2. 014011535-E-00 2014/11 - 22 - [AK5397] 9. Functional Descriptions System Clock MCLK, BICK and LRCK (fs) clocks are required in slave mode. A stable clock must be supplied when the AK5397 is in operation (PDN pin = "H"). The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. MCLK frequency, BICK frequency and master/slave mode are selected by CKS2-0 and MSN pins as shown in Table 2. The MSN pin controls Master/Slave mode switching. The AK5397 outputs BICK and LRCK in master mode when inputting MCLK. When the AK5397 is in slave mode, MCLK, BICK and LRCK should be input. (Table 4) For synchronization between multiple devices, the AK5397 should be reset by the PDN pin after an operation clock change, clock mode switching, digital I/F change and Master/Slave mode switching. Clock and Mode changes should only be made during the reset. fs 32kHz 44.1kHz 48kHz 96kHz 192kHz 384kHz 768kHz MCLK 32fs 64fs 128fs 256fs 512fs N/A N/A N/A N/A N/A N/A 24.576MHz N/A N/A N/A N/A N/A 24.576MHz N/A N/A N/A N/A N/A 24.576MHz N/A N/A 8.192MHz 11.2896MHz 12.288MHz 24.576MHz N/A N/A N/A 16.384MHz 22.5792MHz 24.576MHz N/A N/A N/A N/A Table 1. System Clock Example (N/A: Not Available) 014011535-E-00 2014/11 - 23 - [AK5397] MSN pin CKS2 pin CKS1 pin CKS0 pin MCLK 0 0 0 256fs 0 0 1 0 1 0 256fs 64fs 0 1 1 128fs 64fs 1 0 0 64fs 64fs 1 0 1 32fs 32fs 1 1 0 0 1 1 0 0 0 1 0 1 256fs 512fs 64fs 64fs 0 1 0 256fs 64fs 0 1 1 128fs 64fs 1 0 0 64fs 64fs 1 0 1 32fs 32fs L (Slave) H (Master) 1 1 MCLK 512fs 256fs 128fs 64fs 32fs BICK Sampling Speed 64fs BICK 128fs (Table 3) Normal Speed Mode (8kHz fs 48kHz) Auto Setting Mode Double Speed Mode (48kHz < fs 96kHz) Quad Speed Mode (96kHz < fs 192kHz) Octal Speed Mode (fs = 384kHz) Hex Speed Mode (fs = 768kHz) N/A Normal Speed Mode (8kHz fs 48kHz) Double Speed Mode (48kHz < fs 96kHz) Quad Speed Mode (96kHz < fs 192kHz) Octal Speed Mode (fs = 384kHz) Hex Speed Mode (fs = 768kHz) 1 0 N/A 1 1 Table 2. Setting of MCLK /BICK/Sampling Speed BICK Sampling Speed 64fs BICK 128fs Normal Speed Mode (8kHz fs 48kHz) 64fs Double Speed Mode (48kHz < fs 96kHz) 64fs Quad Speed Mode (96kHz < fs 192kHz) 64fs Octal Speed Mode (fs = 384kHz) 32fs Hex Speed Mode (fs = 768kHz) Table 3. Auto Setting Mode (Slave Mode) Master Mode/Slave Mode The MSN pin selects either master or slave modes as shown in Table 4. The AK5397 outputs BICK and LRCK in master mode. In slave mode, provide MCLK, BICK and LRCK. MSN pin Mode BICK, LRCK BICK = Input L Slave Mode LRCK = Input BICK = Output H Master Mode LRCK = Output Table 4. Master mode/Slave mode 014011535-E-00 2014/11 - 24 - [AK5397] Audio Interface Format 12 types of audio data interface can be selected by the TDM1-0, MSN and DIF pins as shown in Table 5. The audio data format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's complement format. The SDTO1/2 is clocked out on the falling edge of BICK. In normal mode, Mode 0-1 are the slave mode, and Mode 2-3 are the master mode. BICK frequency is shown in Table 2. In TDM256 mode, BICK must be fixed to 256fs. In the slave mode, "H" time and "L" time of LRCK must be 1/256fs at least. In the master mode, "H" time ("L" time at I2S mode) of LRCK is 1/8fs typically. TDM256 mode supports only Normal Speed. In TDM128 mode, BICK must be fixed to 128fs. In the slave mode, "H" time and "L" time of LRCK must be 1/128fs at least. In the master mode, "H" time ("L" time at I2S mode) of LRCK is 1/4fs typically. TDM128 mode supports Normal/Double/Quad Speed. TDM1 pin TDM0 pin L L L H H H H L LRCK BICK MSN DIF Mode SDTO pin pin I/O L 0 32bit, MSB justified H/L I L (Slave) H 1 32bit, I2S Compatible L/H I Normal (Table 2) L 2 32bit, MSB justified H/L O H 2 (Master) H 3 32bit, I S Compatible L/H O L 4 32bit, MSB justified I 256fs L (Slave) H 5 32bit, I2S Compatible I 256fs TDM256 L 6 32bit, MSB justified O 256fs H (Master) H 7 32bit, I2S Compatible O 256fs L 8 32bit, MSB justified I 128fs L 2 (Slave) H 9 32bit, I S Compatible I 128fs TDM128 L 10 32bit, MSB justified O 128fs H 2 (Master) H 11 32bit, I S Compatible O 128fs N/A N/A 12 N/A N/A N/A N/A N/A Table 5. Audio Interface Format (N/A: Not available) Sampling Speed I/O I I O O I I O O I I O O N/A Audio Interface Format Normal TDM256 TDM128 Normal TDM256 TDM128 Normal TDM256 TDM128 Normal TDM256 TDM128 The maximum number of channels 2ch Normal Speed 8ch 4ch 2ch Double Speed N/A 4ch 2ch Quad Speed N/A 4ch 2ch Octal Speed N/A N/A 2ch Normal (SDTO1: Lch, SDTO2: Rch) Hex Speed TDM256 N/A TDM128 N/A Table 6. Relationship between Sampling Speed and Audio Interface Format (N/A: Not available) 014011535-E-00 2014/11 - 25 - [AK5397] LRCK 0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1 BICK(128fs) SDTO 31 30 0 1 12 11 10 2 12 13 0 14 31 30 23 24 31 0 12 1 2 11 10 12 13 0 14 31 23 24 31 0 1 BICK(64fs) SDTO 31 30 20 19 18 8 9 0 1 31 30 20 19 18 Lch Data 8 9 0 1 31 Rch Data 31: MSB, 0:LSB @ 32bit Figure 21. Mode 0/2 Timing (Normal mode, MSB justified, Normal/Double/Quad/Octal speed mode) LRCK 0 1 2 13 14 15 16 17 18 30 29 31 0 1 2 13 14 15 16 17 18 30 29 0 31 1 BICK(32fs) SDTO1(Lch) 31 30 18 SDTO2(Rch) 2 1 0 31 30 18 17 16 15 14 8 2 1 0 31 2 1 0 31 30 18 17 16 15 14 8 2 1 0 31 18 17 16 15 14 31 30 16 15 14 18 17 16 15 14 18 16 15 14 18 16 15 14 31: MSB, 0:LSB @ 32bit Figure 22. Mode 0/2 Timing (Normal mode, MSB justified, Hex speed mode) LRCK 0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 24 25 31 0 1 BICK(128fs) SDTO 31 0 1 13 12 11 2 12 13 0 14 31 24 25 31 0 1 13 2 12 11 12 0 13 14 0 1 BICK(64fs) SDTO 0 31 21 20 19 9 8 2 Lch Data 1 0 31 21 20 19 9 8 2 1 0 Rch Data 31: MSB, 0:LSB @ 32bit Figure 23. Mode 1/3 Timing (Normal mode, I2S Compatible, Normal/Double/Quad/Octal Speed) 014011535-E-00 2014/11 - 26 - [AK5397] LRCK 0 1 13 2 14 15 16 17 18 30 29 31 0 1 2 13 14 15 16 17 18 30 29 0 31 1 BICK(32fs) SDTO1(Lch) 0 31 19 18 17 16 15 3 2 1 0 31 19 18 17 16 15 8 3 2 1 0 SDTO2(Rch) 0 31 19 18 18 16 15 3 2 1 0 31 19 18 17 16 15 8 3 2 1 0 9 31: MSB, 0:LSB @ 32bit 18 16 15 14 Figure 24. Mode 1/3 Timing (Normal mode, I2S Compatible, Hex Speed) 256 BICK LRCK (Mode 6) LRCK (Mode 4) BICK (256fs) SDTO 31 30 0 31 30 0 Lch Rch 32 BICK 32 BICK 31 30 Figure 25. Mode 4/6 Timing (TDM256 mode, MSB justified) 256 BICK LRCK (Mode 7) LRCK (Mode 5) BICK (256fs) SDTO 31 30 Lch 32 BICK 0 31 30 0 31 Rch 32 BICK 32 BICK Figure 26. Mode 5/7 Timing (TDM256 mode, I2S Compatible) 014011535-E-00 2014/11 - 27 - [AK5397] 128 BICK LRCK (Mode 10) LRCK (Mode 8) BICK (128fs) SDTO 31 30 0 31 30 0 Lch Rch 32 BICK 32 BICK 31 30 Figure 27. Mode 8/10 Timing (TDM128 mode, MSB justified) 128 BICK LRCK (Mode 11) LRCK (Mode 9) BICK (128fs) SDTO 31 30 0 31 30 0 Lch Rch 32 BICK 32 BICK 31 32 BICK Figure 28. Mode 9/11 Timing (TDM128 mode, I2S Compatible) 014011535-E-00 2014/11 - 28 - [AK5397] Cascade TDM Mode (1) TDM256 mode The AK5397 supports cascading of up to four devices in a daisy chain configuration at TDM256 mode. In this mode, the SDTO1 pin (SDTO2 pin) is connected to the TDMIN1 pin (TDMIN2 pin) of next device. When four devices are connected by daisy-chaining as Figure 29, the SDTO1 pin (SDTO2 pin) of device #4 can send 8ch TDM data. AK5397 #1 256fs or 512fs MCLK TDMIN1 48kHz LRCK TDMIN2 256fs BICK SDTO1 GND SDTO2 AK5397 #2 MCLK TDMIN1 LRCK TDMIN2 BICK SDTO1 SDTO2 AK5397 #3 MCLK TDMIN1 LRCK TDMIN2 BICK SDTO1 SDTO2 AK5397 #4 MCLK TDMIN1 LRCK TDMIN2 BICK SDTO1 8ch TDM SDTO2 8ch TDM Figure 29. Cascade TDM Connection Diagram 014011535-E-00 2014/11 - 29 - [AK5397] 256 BICK LRCK BICK(256fs) #1 SDTO1/2(o) #2 SDTO1/2(o) #3 SDTO1/2(o) #4 SDTO1/2(o) 31 30 1 0 31 30 1 L#1 R#1 32 BICK 32 BICK 31 30 1 0 31 30 31 30 0 1 0 31 30 1 0 31 30 1 L#2 R#2 L#1 R#1 32 BICK 32 BICK 32 BICK 32 BICK 31 30 1 0 31 30 1 0 31 30 1 0 31 30 31 30 0 1 0 31 30 1 0 31 30 1 0 L#3 R#3 L#2 R#2 L#1 R#1 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 31 30 1 0 31 30 1 0 31 30 1 0 31 30 L#4 R#4 L#3 R#3 L#2 R#2 L#1 R#1 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 30. Cascade TDM Timing (Mode 4; TDM256 mode, MSB justified, Slave mode) 014011535-E-00 2014/11 - 30 - [AK5397] (2) TDM128 mode The AK5397 supports cascading of two devices in a daisy chain configuration at TDM128 mode. In this mode, the SDTO1 pin (SDTO2 pin) is connected to the TDMIN1 pin (TDMIN2 pin) of next device. When two devices are connected by daisy-chaining as Figure 31, the SDTO1 pin (SDTO2 pin) of device #2 can send 4ch TDM data. AK5397 #1 256fs or 512fs MCLK TDMIN1 48kHz or 96kHz or 192kHz LRCK TDMIN2 128fs BICK SDTO1 GND SDTO2 AK5397 #2 MCLK TDMIN1 LRCK TDMIN2 BICK SDTO1 4ch TDM SDTO2 4ch TDM Figure 31. Cascade TDM Connection Diagram 128 BICK LRCK BICK(128fs) #1 SDTO1/2(o) #2 SDTO1/2(o) 31 30 29 28 4 3 2 1 0 31 30 29 28 4 3 2 L#1 R#1 32 BICK 32 BICK 31 30 29 28 4 3 2 1 0 31 30 29 28 4 3 2 31 30 1 0 1 0 31 30 29 28 4 3 2 1 0 31 30 29 28 4 3 2 L#2 R#2 L#1 R#1 32 BICK 32 BICK 32 BICK 32 BICK 1 0 31 30 Figure 32. Cascade TDM Timing (Mode 8; TDM128 mode, MSB justified, Slave mode) 014011535-E-00 2014/11 - 31 - [AK5397] When using multiple devices in slave mode on cascade connection, internal operation timing of each device may differ for one MCLK cycle depending on PDN, MCLK and BICK input timings. To prevent this timing difference, BICK "" should be more than 10ns from MCLK "" and PDN "" should be more than 15ns from MCLK "" as shown in Table 7. This timing can be achieved by inputting BICK divided half on MCLK "" when MCLK=2 x BICK (Normal 512fs, Double Speed) (Figure 33), and can be achieved by inputting BICK synchronized to MCLK when MCLK=BICK (Normal 256fs mode, Quad speed) (Figure 34). Parameter MCLK "" to BICK "" BICK "" to MCLK "" MCLK "" to PDN "" PDN "" to MCLK "" Symbol min typ max Unit tMCB 10 tBIM 10 tMPD 15 tPDM 15 Table 7. TDM Mode Clock Timing ns ns ns ns VIH MCLK VIL tMCB tBIM VIH BICK VIL Figure 33. Audio Interface Timing (Slave mode, TDM Mode MCLK=2 x BICK) VIH MCLK VIL tMCB tBIM VIH BICK VIL Figure 34. Audio Interface Timing (Slave mode, TDM Mode MCLK=BICK) VIH VIL PDN tMPD VIH VIL MCLK tPDM Figure 35. Reset Timing (Slave mode, TDM Mode) 014011535-E-00 2014/11 - 32 - [AK5397] Digital High Pass Filter The AK5397 has a digital high pass filter for DC offset cancellation. The high pass filter is controlled by the HPFE pin as shown by Table 8 and is reflected in both SDTO1 and SDTO2. The cut-off frequency of the high pass filter is fixed 1.0Hz. The high pass filter is disabled in fs=384KHz mode or fs=768KHz mode, and the setting of HPFE pin is ignored. The high pass filter setting should only be changed when the PDN pin = "L". HPFE pin HPF L OFF H ON Table 8. Setting of HPF Overflow Detection The AK5397 has an overflow detect function for the analog input. The OVF pin becomes "H" for one cycle after LRCK "" if either channel overflows (more than -0.276dBFS). The OVF output for overflowed analog input has the same group delay as the ADC. The OVF pin is "L" for 1028/fs (=21.41ms@fs=48kHz) after the PDN pin="", and then overflow detection is enabled. Mono Mode When the MONO pin is set to "H", the AK5397 becomes MONO mode. In the Mono mode, L channel and R channel data are summed digitally and divided into half. The dynamic range and S/N can be improved about 3dB when the same analog signal is input to left and right channels. In this mode, the left and right channel data on SDTO1 and SDTO2 are the same data. MONO pin SDTO1/2 Output Data L Stereo Mode H Mono Mode Table 9. The setting of MONO mode. LRCK 0 1 2 13 14 15 16 17 18 30 29 31 32 33 34 44 45 46 47 48 49 62 61 0 63 1 BICK(64fs) SDTO1/2(Normal) 31 30 18 17 16 15 14 18 2 0 1 31 30 8 2 1 0 31 1 0 31 16 15 14 31: MSB, 0:LSB @ Lch 32bit SDTO1/2(MONO) 31 30 18 17 16 15 14 18 17 16 15 14 18 31: MSB, 0:LSB @ Rch 32bit 2 1 0 31 30 18 17 16 15 14 18 16 15 14 31: MSB, 0:LSB @ Lch 32bit 2 16 15 14 31: MSB, 0:LSB @ Rch 32bit Same Data Figure 36. Audio Interface Timing (Normal mode or MONO mode, MSB justified) 014011535-E-00 2014/11 - 33 - [AK5397] Digital Output Data The AK5397 has two kinds of output data. These data are sent from SDTO1 and SDTO2 pins at the same time. The SDTO1 pin is passed through "Sharp Roll-off" and the SDTO2 pin is passed through "Short Delay Filter" or "Minimum Phase Filter" selected by the SDFIL pin as shown by Table 12. When fs=384kHz, 768kHz, the AK5397 does not support "Short Delay Filter" and "Minimum Phase Filter". When fs=384kHz, the SDTO1 pin is passed through "Sharp Roll-off Filter", and the SDTO2 pin is "L". When fs=768kHz, the SDTO1 and SDTO2 pins are passed through "Sharp Roll-off Filter" as shown in Table 10. However, in MONO mode, the SDTO1 pin outputs the data of (Lch+Rch)/2, and the SDTO2 pin is "L" as shown in Table 11. The output data of SDTO1 and SDTO2 pins can be disabled by using SDM1 and SDM2 pins respectively as shown in Figure 37, Table 13 and Table 14. However, the SDM2 pin can output data if fs=768KHz even when the SDM2 pin = "H". Sampling Speed SDTO1 Output Data SDTO2 Output Data 48kHz Sharp Roll-off Filter Short Delay Filter 96kHz Sharp Roll-off Filter Short Delay Filter 192kHz Sharp Roll-off Filter Short Delay Filter 384kHz Sharp Roll-off Filter "L" Output 768kHz Sharp Roll-off Filter (Lch) Sharp Roll-off Filter (Rch) Table 10. SDTO1 / SDTO2 Output Data (MONO = "L") 17 18 16 15 14 Sampling Speed 48kHz 96kHz 192kHz SDTO1 Output Data SDTO2 Output Data Sharp Roll Off Filter Short Delay Filter Sharp Roll Off Filter Short Delay Filter Sharp Roll Off Filter Short Delay Filter Sharp Roll Off filter 384kHz, 768kHz "L "Output (Lch+Rch)/2 Table 11. SDTO1 / SDTO2 Output Data (MONO = "H") Delta-Sigma Modulator Digital Filter (Sharp) Digital Filter (Short) Audio Interface Audio Interface SDTO1 SDTO2 Sharp Roll Off Filter Block Short Delay Filter Block Figure 37. Digital Filter Block 014011535-E-00 2014/11 - 34 - [AK5397] SDFIL pin SDTO2 Output Data L Short Delay Filter H Minimum Phase Filter Table 12. The setting of SDFIL pin SDM1 pin SDTO1 Output Data L Normal output H "L" output Table 13. The setting of SD1M pin SDM2 pin SDTO2 Output Data L Normal output H "L" output Table 14. The setting of SD2M pin The SDTO1/2 outputs settle to data correspondent to the analog input signals after group delay time when SDM1/2 pins are changed "H" "L" and SDTO1/2 pins are in Normal Output Mode. 014011535-E-00 2014/11 - 35 - [AK5397] Power Down & Reset The AK5397 is placed in the power-down mode by bringing the PDN pin "L" and the digital filter is also reset at the same time. This reset should always be made after power-up. In the power-down mode, the VCOM is AVSS level. An analog initialization cycle starts after exiting the power-down mode. The output data SDTO1/2 are valid after 1028 cycles of LRCK clock in master mode (1029 cycles in slave mode). During initialization, the ADC digital data outputs of both channels are forced to "0". The ADC outputs settle to data correspondent to the input signals after the end of initialization (This settling takes approximately the group delay time). The AK5397 should be reset once by bringing the PDN pin "L" after power-up. The AK5397 exits reset and power down state by MCLK rising edge after setting the PDN pin to "H". The internal timing starts clocking by the rising edge (falling edge in I2S mode) of LRCK after exiting reset and power down state by MCLK. (1) PDN (2) VCOM Internal State Normal Operation Power-down Initialize Normal Operation GD (3) GD A/D In (Analog) A/D Out (Digital) OVF (4) Idle Noise "0"data "0"data "0"data Idle Noise "0"data Notes: (1) 1030/fs in slave mode, 1031/fs in master mode. (2) The VCOM voltage reaches 2.5V in 1.53 ms (typ), 2.64ms (max) after the PDN pin = "H". (3) Analog output corresponding to digital input has group delay (GD). (4) ADC and OVF outputs are "0" data in the power-down mode. Figure 38. Power-down/up sequence example 014011535-E-00 2014/11 - 36 - [AK5397] 10. SYSTEM DESIGN Figure 39 shows the system connection diagram. An evaluation board (AKD5397) is available for fast evaluation as well as suggestions for peripheral circuitry. + VREFLR 34 0.1u VREFHR 35 AVSS 36 TOUT 38 0.1u AVDD 37 VCOM 39 VREFHL 43 VREFLL 44 0.1u LIN1+ LIN1- RIN2+ 33 3 TEST1 4 AVSS 5 HPFE 6 CKS0 TDM1 28 7 CKS1 TDM0 27 8 CKS2 9 PDN RIN2- 32 TEST2 31 AVSS 30 AK5397 MONO 29 Top View TDMIN2 26 TDMIN1 25 + 0.1u Digital3.3v 10u 22 MSN 21 DIF 20 SDFIL 19 SDM2 DVSS 23 18 SDM1 11 DVSS 17 OVF DVDD 24 16 SDTO2 10 DVDD 15 SDTO1 0.1u + 2 12 MCLK 10u Analog5.0V 10u 10u + + 0.1u 14 LRCK Digital3.3v+ 10u + 1 13 BICK Micro-Controller 0.1u 10u TEST3 40 + + AVSS 42 10u AVDD 41 Analog5.0V Electrolytic Capacitor Ceramic Capacitor Micro-Controller Note: - AVSS and DVSS of the AK5397 must be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. Figure 39. System Design 014011535-E-00 2014/11 - 37 - [AK5397] 1. Grounding and Power Supply Decoupling The AK5397 requires careful attention to power supply and grounding arrangements. To minimize digital noise coupling, AVDD and DVDD should be individually de-coupled at the AK5397. AVDD is usually supplied from analog supply in system and DVDD is supplied from digital supply in system. Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. AVSS and DVSS must be connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as possible to the supply pin. 2. Voltage Reference Inputs The reference voltage for A/D converter is the difference between VREFHL/R pin and VREFLL/R pin. VREFLL/R pins are connected to AVSS and an electrolytic capacitor over 10F parallel with a 0.1F ceramic capacitor between the VREFHL/R pin and the VREFLL/R pin eliminates the effects of high frequency noise. It is important that a ceramic capacitor should be as near to the pins as possible. All digital signals, especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid unwanted coupling into the AK5397. VCOM is a signal ground of this chip. A 10F electrolytic capacitor in parallel with a 0.1F ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5397. 3. Analog Inputs The Analog input signal is differentially supplied into the modulator via the LIN+ (RIN+) and the LIN(RIN-) pins. The input voltage is the difference between the LIN+ (RIN+) and LIN- (RIN-) pins. The full scale signal on each pin is nominally 2.80V (typ). The output code format is two's complement. The output voltage (VAOUT) is positive full scale for 7FFFFFFFH (@32bit) and negative full scale for 80000000H (@32bit). The ideal VAOUT is 0V for 00000000H (@32bit). The internal HPF removes DC offset. The AK5397 samples the analog inputs at 128fs (6.144MHz@fs=48kHz, Normal Speed Mode). The digital filter rejects noise above the stop band except for multiples of 128fs. The AK5397 includes an anti-aliasing filter (RC filter) to attenuate a noise around 128fs. The AK5397 requires a +5V analog supply voltage. Any voltage which exceeds the upper limit of AVDD+0.3V and lower limit of AVSS-0.3V and any current beyond 10mA for the analog input pins (LIN+/-, RIN+/-) should be avoided. Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals at or beyond these limits. Use caution especially when using 15V for other analog circuits in the system. 014011535-E-00 2014/11 - 38 - [AK5397] 4. External Analog Circuit Examples Figure 40 shows an input buffer circuit example 1. (1st order HPF; fc=0.795Hz, 2nd order LPF; fc=438kHz, gain=-9.63dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is 17.0Vpp (AK5397: 5.6Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=124dB, S/(N+D)=108dB. Resistor values should be in 1% accuracy. When the bias voltage is more than 0.28xAVDD+0.6 [V], the internal diode is powered up. 1.0k 1.0k Analog In 300 VP+ JP1 + 8.5Vpp Vin+ 220 + 910 Bias VP- 100 + 5 2.80Vpp AK5397 AIN+ LME49710 LME49710 XLR 33n VA+ 300 1100 Bias JP2 220 + + 680 10 Vin- 910 - 100 5 AK5397 AIN- + 0.1 LME49710 BiasLME VA=+5V VP=15V 2.80Vpp Figure 40. Analog Input Buffer Circuit Example 1 fin 1Hz 10Hz Frequency Response -2.13dB -0.03dB Table 15. Frequency Response of HPF fin 20kHz 40kHz 80kHz Frequency Response 0.01dB -0.04dB -0.14dB Table 16. Frequency Response of LPF 014011535-E-00 6.144MHz 30.31dB 2014/11 - 39 - [AK5397] Figure 41 shows an input buffer circuit example 1. (1st order HPF; fc=0.795Hz, 2nd order LPF; fc=290kHz, gain=963 dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is 17.0Vpp (AK5397: 5.6Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=127dB, S/(N+D)=100dB. Resistor values should be in 1% accuracy. When the bias voltage is more than 0.28xAVDD+0.6 [V], the internal diode is powered up. 1.0k 1.0k Analog In 300 VP+ JP1 + 8.5Vpp Vin+ 220 + 910 Bias VP- 100 + 5 2.80Vpp AK5397 AIN+ 33n LME49990 LME49990 XLR 33n VA+ 300 1100 Bias JP2 + + 680 10 220 910 Vin0.1 VA=+5V - 100 5 2.80Vpp AK5397 AIN- + 33n LME49990 Bias VP=15V Figure 41. Analog Input Buffer Circuit Example 2 fin 1Hz 10Hz Frequency Response -2.1dB -0.03dB Table 17. Frequency Response of HPF fin 20kHz 40kHz 80kHz Frequency Response -0.01dB -0.02dB -0.08dB Table 18. Frequency Response of LPF 014011535-E-00 6.144MHz 33.82dB 2014/11 - 40 - [AK5397] 11. PACKAGE Outline Dimensions 44pin LQFP (Unit: mm) 1.60 Max 12.00.20 1.40 0.05 10.00.20 0.05~0.15 23 33 12.00.20 0.80 BSC 12 44 1 1.00 Ref 22 10.00.20 34 11 0.37 +0.08 -0.07 0.20 M C A-B 0.09~0.20 07 C 0.60.15 0.10 C A B 014011535-E-00 2014/11 - 41 - [AK5397] Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy, Halogen (bromine and chlorine) free Cu Solder (Pb free) plate MARKING AK5397EQ XXXXXXX AKM 1 1) Pin #1 indication 2) Audio 4 pro Logo 3) Date Code: XXXXXXX(7 digits) 4) Marking Code: AK5397 5) AKM Logo 12. Ordering Guide AK5397EQ AKD5397 10 +70C 44pin LQFP (0.8mm pitch) Evaluation Board for AK5397 014011535-E-00 2014/11 - 42 - [AK5397] 13. Revision History Date (Y/M/D) 14/11/14 Revision 00 Reason First Edition Page Contents 014011535-E-00 2014/11 - 43 - [AK5397] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ("Product"), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. 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Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 014011535-E-00 2014/11 - 44 -