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1. Genaral Description
The AK5397 is a high performance 32-bit stereo
ADC that achieves class leading performance of
127dB dynamic range for stereo output. This is a
flagship addition to AKM’s VERITA series of
product in the Audio 4 ProTM family. The AK5397
integrates a newly developed circuit by VELVET
SOUNDTM technology achieving rich sound field
and bass representation that realizes a music
playback experience with less distortion. The
class leading performance with a maximum
768kHz PCM output is supported for digital
output and newly developed 32-bit digital filters
are integrated for the best sound quality. The
AK5397 is suitable for digital video recorders
and high quality sound studio mixers for
recording and editing high-resolution sound
sources.
2. Feartures
Advanced multi bit Architecture ADC
Resolution: 32bit
Sampling Rate: 8kHz ~ 768kHz
Full Differential Inputs
S/(N+D): 108dB
DR, S/N: 127dB (Mono Mode: 130dB)
Sharp Roll Off Digital Filter (GD=41.5/fs)
Passband: 0 ~ 21.82kHz (@ fs=48kHz)
Passband Ripple: +0.00010/-0.00015dB
Stopband Attenuation: 100dB
Short Delay Digital Filter (GD=12.5/fs)
Passband: 0 ~ 22.22kHz (@ fs=48kHz)
Passband Ripple: +0.055/-0.015dB
Stopband Attenuation: 93dB
Minimum Phase Digital Filter (GD=3.5/fs)
Passband: 0 ~ 21.75kHz(@ fs=48kHz)
Passband Ripple: +0.04/-0.02dB
Stopband Attenuation: 93dB
Master / Slave Mode
Master Clock:
256fs/512fs (Normal Speed; 8kHz~48kHz)
256fs (Double Speed; 48Hz ~ 96kHz)
128fs (Quad Speed; 96kHz ~ 192kHz)
64fs (Octal Speed; 192kHz ~ 384kHz)
32fs (Hex Speed; 384kHz ~ 768kHz)
Audio Interface Format: 32bit MSB justified, I2S
compatible or TDM
Cascade TDM I/F: 8ch/48kHz, 4ch/96kHz,
4ch/192kHz
Digital HPF for Offset Cancel
Overflow Flag
Power Supply:
4.75 ~ 5.25V(Analog), 3.0 ~ 3.6V(Digital)
Power Dissipation: 455mW
Ta = -10 ~ 70 C
Package: 44-pin LQFP
32-Bit Stereo Premium ADC
AK5397
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3. Block Diagram
SDM1
VREFLR
VREFHR
SDM2
TDMIN2
TDMIN1
AVDD
AVSS
DVDD
SDTO1
MCLK
DIF
HPFE
LIN-
VREFLL
Delta-Sigma
Modulator
Voltage
Reference
Decimation
Filter
VCOM
RIN-
RIN+
LIN+
VREFHL
MONO
Voltage
Reference
Decimation
Filter
SDTO2
CKS0
CKS1
CKS2
LRCK
BICK
PDN
Common
Voltage
SDFI
L
TDM1
TDM0
OVF
MSN
Delta-Sigma
Modulator
HPF
HPF
Audio
Interface
DVSS
Figure 1. Block Diagram
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4. Table of Contents
1. Genaral Description .......................................................................................................................... 1
2. Feartures ........................................................................................................................................... 1
3. Block Diagram .................................................................................................................................. 2
4. Table of Contents ............................................................................................................................. 3
5. Pin Configurations and Functions .................................................................................................... 4
■ Pin Configurations .............................................................................................................................. 4
■ Functions ............................................................................................................................................ 5
■ Handling of Unused Pin ..................................................................................................................... 6
6. Absolute Maximum Ratings .............................................................................................................. 7
7. Recommended Operating Conditions .............................................................................................. 7
8. Electrical Characteristics .................................................................................................................. 8
■ Analog Characteristics ....................................................................................................................... 8
■ Sharp Roll-Off Filter Characteristics .................................................................................................. 9
■ Short Delay Filter Characteristics .................................................................................................... 11
■ Minimum Phase Filter Characteristics ............................................................................................. 12
■ Digital Filter Plot ............................................................................................................................... 14
■ DC Characteristics ........................................................................................................................... 18
■ Switching Characteristics ................................................................................................................. 18
■ Timing Diagrams .............................................................................................................................. 21
9. Functional Descriptions .................................................................................................................. 23
■ System Clock ................................................................................................................................... 23
■ Master Mode/Slave Mode ................................................................................................................ 24
■ Audio Interface Format ..................................................................................................................... 25
■ Cascade TDM Mode ........................................................................................................................ 29
■ Digital High Pass Filter ..................................................................................................................... 33
■ Overflow Detection ........................................................................................................................... 33
■ Mono Mode....................................................................................................................................... 33
■ Digital Output Data ........................................................................................................................... 34
■ Power Down & Reset ....................................................................................................................... 36
10. SYSTEM DESIGN .......................................................................................................................... 37
11. PACKAGE ....................................................................................................................................... 41
■ Outline Dimensions .......................................................................................................................... 41
■ Material & Lead finish ....................................................................................................................... 42
■ MARKING ......................................................................................................................................... 42
12. Ordering Guide ............................................................................................................................... 42
13. Revision History .............................................................................................................................. 43
IMPORTANT NOTICE ........................................................................................................................... 44
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5. Pin Configurations and Functions
■ Pin Configurations
VREFLR
RIN+
34
VREFHR
33
35
AVSS
36
AVDD
37
TOUT
38
VCOM
39
TEST3
40
AVDD
41
AVSS
42
VREFHL
43
VREFLL
44
RIN-
32
TEST2
31
AVSS
30
MONO
29
TDM1
28
TDM0
27
TDMIN2
26
TDMIN1
25
DVDD
24
DVSS
23
LIN+
1
LIN-
2
TEST1
3
4
5
CKS0
6
CKS1
7
CKS2
8
PDN
9
DVDD
10
DVSS
11
22
21
20
19
18
17
16
15
14
13
12
MSN
DIF
SDFIL
SDM2
SDM1
OVF
SDTO2
SDTO1
LRCK
BICK
MCLK
AK5397EQ
Top View
AVSS
HPFE
Figure 2. Pin Configurations
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■ Functions
No.
Pin Name
Power
I/O
Function
1
LIN+
A
I
Lch Positive Analog Input Pin
2
LIN-
A
I
Lch Negative Analog Input Pin
3
TEST1
A
-
Test Pin
This pin must be connected to AVSS.
4
AVSS
A
-
Analog Ground Pin, 0V
5
HPFE
D
I
HPF Enable Pin
“L”: Disable, “H” Enable
6
CKS0
D
I
Clock Mode Select #0 Pin
7
CKS1
D
I
Clock Mode Select #1 Pin
8
CKS2
D
I
Clock Mode Select #2 Pin
9
PDN
D
I
Power down & Reset pin
“L”: All blocks are powered-down and reset.
“H”: Normal Operation
10
DVDD
D
-
Digital Power Supply Pin, 3.0V ~ 3.6V
11
DVSS
D
-
Digital Ground Pin, 0V
12
MCLK
D
I
Master Clock Input Pin
13
BICK
D
I/O
Serial Data Clock Pin
When PDN pin = “L”, BICK outputs “L” in master made.
14
LRCK
D
I/O
L/R Channel Select Clock Pin
When PDN pin = “L”, LRCK outputs “L” in master made.
15
SDTO1
D
O
Serial Data Output #1 Pin (Sharp Roll Off Filter Output)
When PDN pin = “L”, SDTO1 outputs “L”.
16
SDTO2
D
O
Serial Data Output #2 Pin (Short Delay or Minimum Phase Filter Output)
When PDN pin = “L”, SDTO2 outputs “L”.
17
OVF
D
O
Analog Input Overflow Detect Pin
This pin goes to “H” if any analog inputs overflows
When the PDN pin = “L”, the OVF pin outputs “L”.
18
SDM1
D
I
SDTO1 Output Mute Pin
This function is synchronized with LRCK edges.
“L”: Normal Operation, “H”: “L” output
19
SDM2
D
I
SDTO2 Output Mute Pin
This function is synchronized with LRCK edges.
“L”: Normal Operation, “H”: “L” output
20
SDFIL
D
I
SDTO2 Digital Filter Select Pin
“L”: Short Delay, “H”: Minimum Phase
21
DIF
D
I
Audio Interface Format Pin
“L”: 32bit MSB justified, “H”: 32bit I2S Compatible
22
MSN
D
I
Master/Slave mode Select Pin
“L”: Slave mode, “H”: Master mode
23
DVSS
D
-
Digital Ground Pin, 0V
24
DVDD
D
-
Digital Power Supply Pin, 3.0 ~ 3.6V
25
TDMIN1
D
I
TDM Data Input #1 Pin
26
TDMIN2
D
I
TDM Data Input #2 Pin
27
TDM0
D
I
TDM I/F Format Enable Pin
“L”: Normal Mode, “H”: TDM Mode
28
TDM1
D
I
TDM I/F BICK Frequency Select Pin
“L”: 256fs, “H”: 128fs
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No.
Pin Name
Power
I/O
Function
29
MONO
D
I
Stereo/Mono mode Select Pin
“L”: Stereo mode, “H”: Mono mode
30
AVSS
A
-
Analog Ground Pin, 0V
31
TEST2
A
I
Test Pin
This pin must be connected to AVSS.
32
RIN-
A
I
Rch Negative Analog Input Pin
33
RIN+
A
I
Rch Positive Analog Input Pin
34
VREFLR
A
I
Rch Negative Reference Voltage Input Pin
Normally connected to AVSS.
35
VREFHR
A
I
Rch Positive Reference Voltage Input Pin, 4.75 ~ 5.25V
Normally connected to the VREFLR pin with a large electrolytic
capacitor and a 0.1F ceramic capacitor.
36
AVSS
A
-
Analog Ground Pin, 0V
37
AVDD1
A
-
Analog Power Supply Pin, 4.75 ~ 5.25V
38
TOUT
A
I
TEST Pin
This pin must be Connected to AVSS.
39
VCOM
A
O
Common Voltage Output Pin, AVDD/2
Normally connected to AVSS with a 0.1F ceramic capacitor in
parallel with a 10F electrolytic capacitor.
40
TEST3
A
I
Test Pin
This pin must be connected to AVSS.
41
AVDD2
A
-
Analog Power Supply Pin, 4.75 ~ 5.25V
42
AVSS
A
-
Analog Ground Pin, 0V
43
VREFHL
A
I
Lch Positive Reference Voltage Input Pin, 4.75 ~ 5.25V
Normally connected to the VREFLL pin with a large electrolytic
capacitor and a 0.1F ceramic capacitor.
44
VREFLL
A
I
Lch Negative Reference Voltage Input Pin
Normally connected to AVSS.
Note 1. All digital input pins must not be left floating.
■ Handling of Unused Pin
The unused I/O pin must be processed as below.
Classification
Pin Name
Setting
Digital
TEST1/2/3, TOUT
This pin must be connected to AVSS.
TDMIN1/2
This pin must be connected to DVSS.
SDTO1, SDTO2, OVF
This pin must be open.
Analog
LIN+, LIN-
Connect the LIN+ pin and the LIN- pin.
RIN+, RIN-
Connect the RIN+ pin and the RIN- pin.
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6. Absolute Maximum Ratings
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
Min.
Max.
Unit
Power
Supplies:
Analog
Digital
|AVSS-DVSS| (Note 3)
AVDD
DVDD
GND1
0.3
0.3
6.0
4.6
0.3
V
V
V
Input Current, Any Pin Except Supplies
IIN
10
mA
Analog Input Voltage (Note 4)
VINA
0.3
AVDD+0.3
V
Digital Input Voltage (Note 5)
VIND
0.3
DVDD+0.3
V
Ambient Temperature (power applied)
Ta
10
70
C
Storage Temperature
Tstg
65
150
C
Note 2. All voltages with respect to ground.
Note 3. AVSS and DVSS must be connected to the same analog ground plane.
Note 4. VREFHL, VREFLL, VREFHR, VREFLR, LIN+, LIN-, RIN+, RIN-, TEST1-3 and TOUT pins.
Note 5. CKS0, CKS1, CKS2,PDN, SDM1, SDM2, SDFIL, TDMIN1, TDMIN2, MCLK, BICK, LRCK, DIF,
MSN, HPFE, MONO, TDM0, TDM1pins
WARING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies:
Analog
AVDD
4.75
5.0
5.25
V
(Note 6)
Digital
DVDD
3.0
3.3
3.6
V
Voltage Reference
(Note 9)
“H” voltage reference (Note 7)
“L” voltage reference (Note 8)
(VREFHL/R) – (VREFLL/R)
VREFHL/R
VREFLL/R
VREF
AVDD-0.5
-
AVDD-0.5
-
AVSS
-
AVDD
-
AVDD
V
V
V
Note 2. All voltages with respect to ground.
Note 6. AVDD and DVDD are powered up simultaneously.
Note 7. VREFHL pin, VREFHR pin
Note 8. VREFLL pin, VREFLR pin
Note 9. VREFLL and VREFLR pins must be connected to AVSS.
Analog input voltage scales with voltage of {(VREFH) – (VREFL)}.
Vin (typ.) = 2.8 x {(VREFH) – (VREFL)} / 5 [V]
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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8. Electrical Characteristics
■ Analog Characteristics
(Ta = 25C; AVDD=5.0V; DVDD=3.3V; AVSS=DVSS=0V; VREFHL=VREFHR=AVDD,
VREFLL=VREFLR=AVSS; fs=48kHz, 96kHz, 192kHz; BICK=64fs; Signal Frequency=1kHz; 32bit Data;
Measurement frequency=10Hz20kHz at fs=48kHz, 40Hz40kHz at fs=96kHz, 80Hz80kHz at
fs=192kHz; External circuit: Figure 41 “Analog input buffer circuit example 2”; unless otherwise specified)
Parameter
Min.
Typ.
Max.
Unit
Resolution
32
Bits
Analog Input Characteristics:
S/(N+D)
fs=48kHz
BW=20kHz
-1dBFS
-1dBFS (Note 10)
-2dBFS (Note 10)
-20dBFS
-60dBFS
92
-
-
-
-
100
108
110
102
64
dB
dB
dB
dB
fs=96kHz
BW=40kHz
-1dBFS
-1dBFS (Note 10)
-20dBFS
-60dBFS
92
-
-
-
99
107
99
60
dB
dB
dB
fs=192kHz
BW=80kHz
-1dBFS
-1dBFS (Note 10)
-20dBFS
-60dBFS
91
-
-
-
99
106
94
54
dB
dB
dB
Dynamic Range (-60dBFS with A-weighted)
(Stereo Mode)
(Mono Mode)
122
125
127
130
dB
dB
S/N (A-weighted) fs=48kHz
(Stereo Mode)
(Mono Mode)
122
125
127
130
dB
dB
S/N (Without A-weighted) fs=96kHz
(Stereo Mode)
115
120
dB
S/N (Without A-weighted) fs=192kHz
(Stereo Mode)
111
116
dB
Input Resistance
650
720
Interchannel Isolation
120
130
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Gain Drift
150
ppm/C
Input Voltage (Note 11)
2.6
2.8
3.0
Vpp
Input DC Bias Voltage
0.382×AVDD
Vpp
Power Supplies:
Power Supply Current
AVDD + VREFHL + VREFHR
DVDD (fs=48kHz, MSN=H, SDM1=L, SDM2=H)
(fs=96kHz, MSN=H, SDM1=L, SDM2=L)
(fs=192kHz, MSN=H, SDM1=L, SDM2=L)
(fs=384kHz, MSN=H, SDM1=L, SDM2=L)
(fs=768kHz, MSN=H, SDM1=L, SDM2=L)
74.6
24
52
53
34
34
94.0
33
71
72
46
46
mA
mA
mA
mA
mA
mA
Power down current (AVDD + DVDD)
10
100
uA
Power Supply Rejection (Note 12)
-
50
-
dB
Note 10. Using the circuit as shown in Figure 40(Analog input buffer circuit example 1)
Note 11. This value is (LIN+) – (LIN-) and (RIN+) - (RIN-). Input voltage is proportional to a difference
between VREFP and VREFL voltages.
Vin (typ.) = 2.8 x {(VREFH) – (VREFL)} / 5 [V]
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Note 12. PSRR is applied to AVDD and DVDD with 1kHz, 20mVpp. The VREFHL/R and VREFLL/R pins
held a constant voltage.
■ Sharp Roll-Off Filter Characteristics
(1) Sharp Roll-Off Filter Characteristics (fs=48kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=48kHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 13) Figure 3-(1)
PB
0
21.82
kHz
Passband Ripple (Note 14) Figure 3-(3)
PR
-0.00015
+0.00010
dB
Frequency Response
(Note 14)
-0.001dB
-0.1dB
-3.0dB
-6.0dB
FR
-
-
-
-
21.93
22.54
23.62
23.99
-
-
-
-
kHz
kHz
kHz
kHz
Stopband (Note 14) Figure 3-(2)
SB
26.17
3072
kHz
Stopband Attenuation Figure 3-(4)
SA
100
dB
Group Delay Distortion
GD
0
1/fs
Group Delay (Note 15)
GD
41.5
1/fs
ADC Digital Filter (HPF):
Frequency response
(Note 14)
-3dB
-0.1dB
FR
-
-
0.93
6.1
-
-
Hz
Hz
(2) Sharp Roll-Off Filter Characteristics (fs=96kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=96kHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 13) Figure 4-(1)
PB
0
43.62
kHz
Pass Band Ripple (Note 14) Figure 4-(3)
PR
-0.00015
+0.00015
dB
Frequency Response
(Note 14)
-0.001dB
-0.1dB
-3.0dB
-6.0dB
FR
-
-
-
-
43.87
45.10
47.25
47.99
-
-
-
-
kHz
kHz
kHz
kHz
Stopband (Note 14) Figure 4-(2)
SB
52.36
3072
kHz
Stopband Attenuation Figure 4-(4)
SA
100
dB
Group Delay Distortion
GD
0
1/fs
Group Delay (Note 15)
GD
41.4
1/fs
ADC Digital Filter (HPF):
Frequency response
(Note 14)
-3dB
-0.1dB
FR
-
-
0.93
6.1
-
-
Hz
Hz
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(3) Sharp Roll-Off Filter Characteristics (fs=192kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=192kHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 13) Figure 5-(1)
PB
0
87.32
kHz
PassBand Ripple (Note 14) Figure 5-(2)
PR
-0.005
+0.006
dB
Frequency Response
(Note 14)
-0.1dB
-3.0dB
-6.0dB
FR
-
-
-
89.52
94.33
95.97
-
-
-
kHz
kHz
kHz
Stopband (Note 14) Figure 5-(3)
SB
105.60
3072
kHz
Stopband Attenuation Figure 5-(4)
SA
100
dB
Group Delay Distortion
GD
0
1/fs
Group Delay (Note 15)
GD
36.3
1/fs
ADC Digital Filter (HPF):
Frequency response
(Note 14)
-3dB
-0.1dB
FR
-
-
0.93
6.1
-
-
Hz
Hz
(4) Sharp Roll-Off Filter Characteristics (fs=384kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=384kHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Frequency Response
(Note 14)
-0.1dB
-1.0B
-3.0dB
-6.0dB
FR
0
-
-
-
60.67
86.93
107.70
125.30
-
-
-
-
kHz
kHz
kHz
kHz
Stopband (Note 14) Figure 6-(1)
SB
223.93
3072
kHz
Stopband Attenuation Figure 6-(2)
SA
83
dB
Group Delay Distortion
GD
0
1/fs
Group Delay (Note 15)
GD
10.6
1/fs
(5) Sharp Roll-Off Filter Characteristics (fs=768kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=768kHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Frequency Response
(Note 14)
-0.1dB
-1.0dB
-3.0dB
-6.0dB
FR
0
-
-
-
34.01
101.51
163.13
216.16
-
-
-
-
kHz
kHz
kHz
kHz
Stopband (Note 14) Figure 7-(1)
533.42
3072
KHz
Stopband Attenuation Figure 7-(2)
85
dB
Group Delay Distortion
GD
0
1/fs
Group Delay (Note 15)
GD
8.4
1/fs
Note 13. The definition of Passband is applied to the frequency which is within the limits of Passband
Ripple.
Note 14. The passband and stopband frequencies scales with fs. The reference frequency of these
responses is 1kHz.
Note 15. The calculated delay time induced by digital filtering. This time is from the input of an analog
signal to the setting of 32bit data both of channels to the ADC output register for ADC.
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■ Short Delay Filter Characteristics
(1) Short Delay Filter Characteristics (fs=48kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=48kHz; SDFIL=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 13) Figure 8-(1)
PB
0
22.22
kHz
Passband Ripple (Note 14) Figure 8-(2)
PR
-0.015
+0.055
dB
Frequency Response
(Note 14)
-0.1dB
-3.0dB
-6.0dB
FR
-
-
-
22.40
23.70
24.28
-
-
-
kHz
kHz
kHz
Stopband (Note 14) Figure 8-(3)
SB
27.93
3072
kHz
Stopband Attenuation Figure 8-(4)
SA
93
dB
Group Delay Distortion
GD
±0.1
1/fs
Group Delay (Note 15)
GD
12.5
1/fs
ADC Digital Filter (HPF):
Frequency response
(Note 14)
-3dB
-0.1dB
FR
-
-
0.93
6.1
-
-
Hz
Hz
(2) Short Delay Filter Characteristics (fs=96kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=96kHz; SDFIL=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 13) Figure 9-(1)
PB
0
44.46
kHz
Passband Ripple (Note 14) Figure 9-(2)
PR
-0.05
+0.02
dB
Frequency Response
(Note 14)
-0.1dB
-3.0dB
-6.0dB
FR
-
-
-
44.68
47.40
48.56
-
-
-
kHz
kHz
kHz
Stopband (Note 14) Figure 9-(3)
SB
55.90
3072
kHz
Stopband Attenuation Figure 9-(4)
SA
93
dB
Group Delay Distortion
GD
±0.075
1/fs
Group Delay (Note 15)
GD
12.4
1/fs
ADC Digital Filter (HPF):
Frequency response
(Note 14)
-3dB
-0.1dB
FR
-
-
0.93
6.1
-
-
Hz
Hz
[AK5397]
014011535-E-00 2014/11
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(3) Short Delay Filter Characteristics (fs=192kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=192kHz; SDFIL=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 13) Figure 10-(1)
PB
0
80.71
kHz
Passband Ripple (Note 14) Figure 10-(2)
PR
-0.05
+0.02
dB
Frequency Response
(Note 14)
-0.1dB
-3.0dB
-6.0dB
PB
-
-
-
82.5
92.86
96.31
-
-
-
kHz
kHz
kHz
Stopband (Note 14) Figure 10-(3)
SB
116.67
3072
kHz
Stopband Attenuation Figure 10-(4)
SA
93
dB
Group Delay Distortion
GD
±0.02
1/fs
Group Delay (Note 15)
GD
12.2
1/fs
ADC Digital Filter (HPF):
Frequency response
(Note 14)
-3dB
-0.1dB
FR
-
-
0.93
6.1
-
-
Hz
Hz
Note 13. The definition of Passband is applied to the frequency which is within the limits of Passband
Ripple.
Note 14. The passband and stopband frequencies scales with fs. The reference frequency of these
responses is 1kHz.
Note 15. The calculated delay time induced by digital filtering. This time is from the input of an analog
signal to the setting of 32bit data both of channels to the ADC output register for ADC.
■ Minimum Phase Filter Characteristics
(1) Minimum Phase Filter Characteristics (fs=48kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=48kHz; SDFIL=“H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 13) Figure 11-(1)
PB
0
21.75
kHz
Passband Ripple (Note 14) Figure 11-(2)
PR
-0.02
+0.04
dB
Frequency Response
(Note 14)
-0.1dB
-3.0dB
-6.0dB
FR
-
-
-
21.97
23.49
24.12
-
-
-
kHz
kHz
kHz
Stopband (Note 14) Figure 11-(3)
SB
27.97
3072
kHz
Stopband Attenuation Figure 11-(4)
SA
93
dB
Group Delay Distortion
GD
±1.5
1/fs
Group Delay (Note 15)
GD
3.5
1/fs
ADC Digital Filter (HPF):
Frequency response
(Note 14)
-3dB
-0.1dB
FR
-
-
0.93
6.1
-
-
Hz
Hz
[AK5397]
014011535-E-00 2014/11
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(2) Minimum Phase Filter Characteristics (fs=96kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=96kHz; SDFIL=“H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 13) Figure 12-(1)
PB
0
43.55
kHz
Passband Ripple (Note 14) Figure 12-(2)
PR
-0.04
+0.02
dB
Frequency Response
(Note 14)
-0.1dB
-3.0dB
-6.0dB
FR
-
-
-
43.87
46.98
48.26
-
-
-
kHz
kHz
kHz
Stopband (Note 14) Figure 12-(3)
SB
55.96
3072
kHz
Stopband Attenuation Figure 12-(4)
SA
93
dB
Group Delay Distortion
GD
±1.5
1/fs
Group Delay (Note 15)
GD
3.4
1/fs
ADC Digital Filter (HPF):
Frequency response
(Note 14)
-3dB
-0.1dB
FR
-
-
0.93
6.1
-
-
Hz
Hz
(3) Minimum Phase Filter Characteristics (fs=192kHz)
(Ta=25C; AVDD=4.75~5.25V; DVDD=3.03.6V; fs=192kHz; SDFIL=“H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 13) Figure 13-(1)
PB
0
80.97
kHz
Passband Ripple (Note 14) Figure 13-(2)
PR
-0.045
+0.015
dB
Frequency Response
(Note 14)
-0.1dB
-3.0dB
-6.0dB
FR
-
-
-
82.55
92.02
95.44
-
-
kHz
kHz
kHz
Stopband (Note 14) Figure 13-(3)
SB
115.57
3072
kHz
Stopband Attenuation Figure 13-(4)
SA
93
dB
Group Delay Distortion
GD
±1.6
1/fs
Group Delay (Note 15)
GD
4.2
1/fs
ADC Digital Filter (HPF):
Frequency response
(Note 14)
-3dB
-0.1dB
FR
-
-
0.93
6.1
-
-
Hz
Hz
Note 13. The definition of Passband is applied to the frequency which is within the limits of Passband
Ripple.
Note 14. The passband and stopband frequencies scales with fs. The reference frequency of these
responses is 1kHz.
Note 15. The calculated delay time induced by digital filtering. This time is from the input of an analog
signal to the setting of 32bit data both of channels to the ADC output register for ADC.
[AK5397]
014011535-E-00 2014/11
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■ Digital Filter Plot
-0.00040
-0.00030
-0.00020
-0.00010
0.00000
0.00010
0.00020
0.00030
0.00040
0 8 16 24 32 40 48
Frequency[KHz]
PB Ripple[dB]
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
(3)
(4)
Figure 3. Sharp Roll Off Filter Normal Mode
-0.00040
-0.00030
-0.00020
-0.00010
0.00000
0.00010
0.00020
0.00030
0.00040
016 32 48 64 80 96
Frequency[KHz]
PB Ripple[dB]
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
(3)
(4)
Figure 4. Sharp Roll Off Filter Double Mode
-0.00800
-0.00600
-0.00400
-0.00200
0.00000
0.00200
0.00400
0.00600
0.00800
032 64 96 128 160 192
Frequency[KHz]
PB Ripple[dB]
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
(3)
(4)
Figure 5. Sharp Roll Off Filter Quad Mode
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014011535-E-00 2014/11
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-3.20
-2.80
-2.40
-2.00
-1.60
-1.20
-0.80
-0.40
0.00
0.40
064 128 192 256 320 384
Frequency[KHz]
PB Ripple[dB]
-160.0
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
Figure 6. Sharp Roll Off Filter Octal Mode
-3.20
-2.80
-2.40
-2.00
-1.60
-1.20
-0.80
-0.40
0.00
0.40
0128 256 384 512 640 768
Frequency[KHz]
PB Ripple[dB]
-160.0
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
Figure 7. Sharp Roll Off Filter Hex Mode
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014011535-E-00 2014/11
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-0.080
-0.060
-0.040
-0.020
0.000
0.020
0.040
0.060
0.080
0 8 16 24 32 40 48
Frequency[KHz]
PB Ripple[dB]
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
(3)
(4)
Figure 8 Short Delay Filter Normal Mode
-0.080
-0.060
-0.040
-0.020
0.000
0.020
0.040
0.060
0.080
016 32 48 64 80 96
Frequency[KHz]
PB Ripple[dB]
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
(3)
(4)
Figure 9. Short Delay Filter Double Mode
-0.080
-0.060
-0.040
-0.020
0.000
0.020
0.040
0.060
0.080
032 64 96 128 160 192
Frequency[KHz]
PB Ripple[dB]
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
(3)
(4)
Figure 10. Short Delay Filter Quad Mode
[AK5397]
014011535-E-00 2014/11
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-0.080
-0.060
-0.040
-0.020
0.000
0.020
0.040
0.060
0.080
0 8 16 24 32 40 48
Frequency[KHz]
PB Ripple[dB]
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
(3)
(4)
Figure 11. Minimum Phase Filter Normal Mode
-0.080
-0.060
-0.040
-0.020
0.000
0.020
0.040
0.060
0.080
016 32 48 64 80 96
Frequency[KHz]
PB Ripple[dB]
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
(3)
(4)
Figure 12. Minimum Phase Filter Double Mode
-0.080
-0.060
-0.040
-0.020
0.000
0.020
0.040
0.060
0.080
032 64 96 128 160 192
Frequency[KHz]
PB Ripple[dB]
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
Attenation[dB]
(2)
(1)
(3)
(4)
Figure 13. Minimum Phase Filter Quad Mode
[AK5397]
014011535-E-00 2014/11
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■ DC Characteristics
(Ta= -10~70C; AVDD=4.75~5.25V; DVDD=3.03.6V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
High-Level Input Voltage (Note 5)
VIH
70%DVDD
-
-
V
Low-Level Input Voltage (Note 5)
VIL
-
-
30%DVDD
V
High-Level Output Voltage (Iout=-100A)
Low-Level Output Voltage (Iout= 100A)
VOH
VOL
DVDD0.5
-
-
-
0.5
V
V
Input Leakage Current
Iin
-
-
10
A
Note 5. CKS0, CKS1, CKS2,PDN, SDM1, SDM2, SDFIL, TDMIN1, TDMIN2, MCLK, BICK, LRCK, DIF,
MSN, HPFE, MONO, TDM0, TDM1pin
■ Switching Characteristics
(Ta= -10~70C; AVDD=4.75~5.25V; DVDD=3.03.6V; CL=20pF)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
2.048
0.4/fCLK
0.4/fCLK
12.288
24.576
MHz
ns
ns
LRCK Timing (Slave Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
Duty Cycle
fs
Duty
8
45
768
55
kHz
%
TDM256 MODE (TDM1=“L”, TDM0=“H”)
LRCK Frequency
“H” time
“L” time
fs
tLRH
tLRL
8
1/256fs
1/256fs
48
kHz
ns
ns
TDM128 MODE (TDM1=“H”, TDM0=“H”)
LRCK Frequency
“H” time
“L” time
fs
tLRH
tLRL
8
1/128fs
1/128fs
192
kHz
ns
ns
LRCK Timing (Master Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
Duty Cycle
fs
Duty
8
50
768
kHz
%
TDM256 MODE (TDM1=“L”, TDM0=“H”)
LRCK Frequency
“H” time (Note 16)
fs
tLRH
8
1/8fs
48
kHz
ns
TDM128 MODE (TDM1=“H”, TDM0=“H”)
LRCK Frequency
“H” time (Note 16)
fs
tLRH
8
1/4fs
192
kHz
ns
Note 16. “L” time at I2S format.
[AK5397]
014011535-E-00 2014/11
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Parameter
Symbol
Min.
Typ.
Max.
Unit
Audio Interface Timing (Slave mode)
Normal mode (TDM1=“L”, TDM0=“L”)
(8KHz≦fs≦192KHz)
BICK Period (8kHz fs 48kHz)
(48kHz < fs 192kHz)
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “” (Note 17)
BICK “” to LRCK Edge (Note 17)
LRCK to SDTO1/2 (MSB) (Except I2S mode)
BICK “” to SDTO1/2
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/128fs
1/64fs
32
32
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Normal mode (TDM1=“L”, TDM0=“L”)
(192KHz≦fs≦768KHz)
BICK Period (192kHz fs 384kHz)
(384kHz < fs 768kHz)
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “” (Note 17)
BICK “” to LRCK Edge (Note 17)
BICK “” to SDTO1/2
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
1/64fs
1/32fs
16
16
10
10
10
ns
ns
ns
ns
ns
ns
ns
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “” (Note 17)
BICK “” to LRCK Edge (Note 17)
BICK “” to SDTO1/2
TDMIN1/2 Setup Time
TDMIN1/2 Hold Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tTDS
tTDH
1/256fs
32
32
20
20
10
10
20
ns
ns
ns
ns
ns
ns
ns
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(8kHz fs 96kHz)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “” (Note 17)
BICK “” to LRCK Edge (Note 17)
BICK “” to SDTO1/2
TDMIN1/2 Setup Time
TDMIN1/2 Hold Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tTDS
tTDH
1/128fs
32
32
20
20
10
10
20
ns
ns
ns
ns
ns
ns
ns
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(96kHz < fs 192kHz)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “” (Note 17)
BICK “” to LRCK Edge (Note 17)
BICK “” to SDTO1/2
TDMIN1/2 Setup Time
TDMIN1/2 Hold Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tTDS
tTDH
1/128fs
16
16
10
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
[AK5397]
014011535-E-00 2014/11
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Parameter
Symbol
Min.
Typ.
Max.
Unit
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Frequency (8kHz fs 192kHz)
(192kHz < fs 384kHz)
BICK Duty
BICK “” to LRCK
BICK “” to SDTO1/2
fBCK
fBCK
dBCK
tMBLR
tBSD
12
20
64fs
32fs
50
12
20
Hz
Hz
%
ns
ns
Normal mode (TDM1=“L”, TDM0=“L”)
(384KHz < fs ≦ 768KHz)
BICK Frequency
BICK Duty
BICK “” to LRCK
BICK “” to SDTO1/2
fBCK
dBCK
tMBLR
tBSD
6
10
32fs
50
6
10
Hz
Hz
%
ns
ns
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Frequency
BICK Duty (Note 18)
BICK “” to LRCK
BICK “” to SDTO1/2
TDMIN1/2 Setup Time
TDMIN1/2 Hold Time
fBCK
dBCK
tMBLR
tBSD
tTDS
tTDH
12
20
10
10
256fs
50
12
20
Hz
%
ns
ns
ns
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(8kHz fs 96kHz)
BICK Frequency
BICK Duty
BICK “” to LRCK
BICK “” to SDTO1/2
TDMIN1/2 Setup Time
TDMIN1/2 Hold Time
fBCK
dBCK
tMBLR
tBSD
tTDS
tTDH
12
20
10
10
128fs
50
12
20
Hz
%
ns
ns
ns
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(96kHz < fs 192kHz)
BICK Frequency
BICK Duty
BICK “” to LRCK
BICK “” to SDTO1/2
TDMIN1/2 Setup Time
TDMIN1/2 Hold Time
fBCK
dBCK
tMBLR
tBSD
tTDS
tTDH
6
10
10
10
128fs
50
6
10
Hz
%
ns
ns
ns
ns
Reset timing
RSTN Pulse width
tRTW
150
ns
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs.
[AK5397]
014011535-E-00 2014/11
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■ Timing Diagrams
1/fCLK
tCLKL
VIH
tCLKH
MCLK
VIL
Figure 14. MCLK Timing (TDM0 pin = “L” or “H”)
1/fs
LRCK
VIH
VIL
tLRL
tLRH
Figure 15. LRCK Timing (TDM0 pin = “L” or “H”)
tBCK
tBCKL
VIH
tBCKH
BICK
VIL
Figure 16.BICK Timing (TDM0 pin = “L” or “H”)
LRCK VIH
VIL
tBLR
BICK VIH
VIL
tLRS
SDTO 50%OVDD
tLRB
tBSD
Figure 17. Audio Interface Timing (Slave mode, TDM0 pin = “L”)
50%DVDD
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014011535-E-00 2014/11
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LRCK VIH
VIL
tBLR
BICK VIH
VIL
SDTO 50%OVDD
tLRB
tBSD
TDMIN VIH
VIL
tTDS tTDH
Figure 18. Audio Interface Timing (Slave mode, TDM0 pin = “H”)
LRCK
BICK 50%OVDD
SDTO 50%OVDD
tBSD
tMBLR dBCK
50%OVDD
TDMIN VIH
VIL
tTDS tTDH
Figure 19. Audio Interface Timing (Master mode, TDM0 pin= “H” or “L”)
PDN
tPDW
Figure 20. Reset & Calibration Timing
Note: SDTO shows SDTO1 and SDTO2. TDMIN shows TDMIN1 and TDMIN2.
50%DVDD
50%DVDD
50%DVDD
50%DVDD
[AK5397]
014011535-E-00 2014/11
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9. Functional Descriptions
■ System Clock
MCLK, BICK and LRCK (fs) clocks are required in slave mode. A stable clock must be supplied when the
AK5397 is in operation (PDN pin = “H”). The LRCK clock input must be synchronized with MCLK,
however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the
system clock frequency. MCLK frequency, BICK frequency and master/slave mode are selected by
CKS2-0 and MSN pins as shown in Table 2.
The MSN pin controls Master/Slave mode switching. The AK5397 outputs BICK and LRCK in master
mode when inputting MCLK. When the AK5397 is in slave mode, MCLK, BICK and LRCK should be
input. (Table 4)
For synchronization between multiple devices, the AK5397 should be reset by the PDN pin after an
operation clock change, clock mode switching, digital I/F change and Master/Slave mode switching.
Clock and Mode changes should only be made during the reset.
fs
MCLK
32fs
64fs
128fs
256fs
512fs
32kHz
N/A
N/A
N/A
8.192MHz
16.384MHz
44.1kHz
N/A
N/A
N/A
11.2896MHz
22.5792MHz
48kHz
N/A
N/A
N/A
12.288MHz
24.576MHz
96kHz
N/A
N/A
N/A
24.576MHz
N/A
192kHz
N/A
N/A
24.576MHz
N/A
N/A
384kHz
N/A
24.576MHz
N/A
N/A
N/A
768kHz
24.576MHz
N/A
N/A
N/A
N/A
Table 1. System Clock Example (N/A: Not Available)
[AK5397]
014011535-E-00 2014/11
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MSN pin
CKS2
pin
CKS1
pin
CKS0
pin
MCLK
BICK
Sampling Speed
L
(Slave)
0
0
0
256fs
64fs BICK
128fs
Normal Speed Mode
(8kHz fs 48kHz)
0
0
1
(Table 3)
Auto Setting Mode
0
1
0
256fs
64fs
Double Speed Mode
(48kHz < fs 96kHz)
0
1
1
128fs
64fs
Quad Speed Mode
(96kHz < fs 192kHz)
1
0
0
64fs
64fs
Octal Speed Mode
(fs = 384kHz)
1
0
1
32fs
32fs
Hex Speed Mode
(fs = 768kHz)
1
1
0
N/A
1
1
1
H
(Master)
0
0
0
256fs
64fs
Normal Speed Mode
(8kHz fs 48kHz)
0
0
1
512fs
64fs
0
1
0
256fs
64fs
Double Speed Mode
(48kHz < fs 96kHz)
0
1
1
128fs
64fs
Quad Speed Mode
(96kHz < fs 192kHz)
1
0
0
64fs
64fs
Octal Speed Mode
(fs = 384kHz)
1
0
1
32fs
32fs
Hex Speed Mode
(fs = 768kHz)
1
1
0
N/A
1
1
1
Table 2. Setting of MCLK /BICK/Sampling Speed
MCLK
BICK
Sampling Speed
512fs
64fs BICK 128fs
Normal Speed Mode (8kHz fs 48kHz)
256fs
64fs
Double Speed Mode (48kHz < fs 96kHz)
128fs
64fs
Quad Speed Mode (96kHz < fs 192kHz)
64fs
64fs
Octal Speed Mode (fs = 384kHz)
32fs
32fs
Hex Speed Mode (fs = 768kHz)
Table 3. Auto Setting Mode (Slave Mode)
■ Master Mode/Slave Mode
The MSN pin selects either master or slave modes as shown in Table 4. The AK5397 outputs BICK and
LRCK in master mode. In slave mode, provide MCLK, BICK and LRCK.
MSN pin
Mode
BICK, LRCK
L
Slave Mode
BICK = Input
LRCK = Input
H
Master Mode
BICK = Output
LRCK = Output
Table 4. Master mode/Slave mode
[AK5397]
014011535-E-00 2014/11
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■ Audio Interface Format
12 types of audio data interface can be selected by the TDM1-0, MSN and DIF pins as shown in Table 5.
The audio data format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's
complement format. The SDTO1/2 is clocked out on the falling edge of BICK.
In normal mode, Mode 0-1 are the slave mode, and Mode 2-3 are the master mode. BICK frequency is
shown in Table 2.
In TDM256 mode, BICK must be fixed to 256fs. In the slave mode, “H” time and “L” time of LRCK must be
1/256fs at least. In the master mode, “H” time (“L” time at I2S mode) of LRCK is 1/8fs typically. TDM256
mode supports only Normal Speed.
In TDM128 mode, BICK must be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK must be
1/128fs at least. In the master mode, “H” time (“L” time at I2S mode) of LRCK is 1/4fs typically. TDM128
mode supports Normal/Double/Quad Speed.
TDM1
pin
TDM0
pin
MSN
pin
DIF
pin
Mode
SDTO
LRCK
BICK
I/O
I/O
L
L
L
(Slave)
L
0
Normal
32bit, MSB justified
H/L
I
(Table 2)
I
H
1
32bit, I2S Compatible
L/H
I
I
H
(Master)
L
2
32bit, MSB justified
H/L
O
O
H
3
32bit, I2S Compatible
L/H
O
O
L
H
L
(Slave)
L
4
TDM256
32bit, MSB justified
I
256fs
I
H
5
32bit, I2S Compatible
I
256fs
I
H
(Master)
L
6
32bit, MSB justified
O
256fs
O
H
7
32bit, I2S Compatible
O
256fs
O
H
H
L
(Slave)
L
8
TDM128
32bit, MSB justified
I
128fs
I
H
9
32bit, I2S Compatible
I
128fs
I
H
(Master)
L
10
32bit, MSB justified
O
128fs
O
H
11
32bit, I2S Compatible
O
128fs
O
H
L
N/A
N/A
12
N/A
N/A
N/A
N/A
N/A
N/A
Table 5. Audio Interface Format (N/A: Not available)
Sampling Speed
Audio Interface Format
The maximum number of channels
Normal
2ch
Normal Speed
TDM256
8ch
TDM128
4ch
Normal
2ch
Double Speed
TDM256
N/A
TDM128
4ch
Normal
2ch
Quad Speed
TDM256
N/A
TDM128
4ch
Octal Speed
Normal
2ch
TDM256
N/A
TDM128
N/A
Hex Speed
Normal
2ch
(SDTO1: Lch, SDTO2: Rch)
TDM256
N/A
TDM128
N/A
Table 6. Relationship between Sampling Speed and Audio Interface Format (N/A: Not available)
[AK5397]
014011535-E-00 2014/11
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LRCK
BICK(128fs)
SDTO
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
31
1
30
0
31
30
12
11
10
0
31
12
11
10
BICK(64fs)
SDTO
0
1
2
12
13
14
23
24
31
0
1
2
12
13
14
23
24
31
0
31
1
30
9
31
30
20
19
18
9
31
20
19
18
31: MSB, 0:LSB @ 32bit
8
0
1
8
0
1
Lch Data
Rch Data
Figure 21. Mode 0/2 Timing (Normal mode, MSB justified, Normal/Double/Quad/Octal speed mode)
LRCK
31: MSB, 0:LSB @ 32bit
BICK(32fs)
SDTO1(Lch)
31
30
14
31
30
18
17
16
14
31
18
17
14
18
16
15
16
0
1
8
0
1
0
1
2
14
15
16
18
29
31
0
1
2
0
1
2
15
13
17
30
15
2
14
15
16
18
29
31
13
17
30
31
30
14
18
16
15
17
14
18
16
15
17
14
18
16
15
0
1
2
31
30
14
18
15
17
14
18
16
15
16
31
8
0
1
2
SDTO2(Rch)
Figure 22. Mode 0/2 Timing (Normal mode, MSB justified, Hex speed mode)
LRCK
BICK(128fs)
SDTO
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
0
1
31
0
31
13
12
11
0
13
12
11
BICK(64fs)
SDTO
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
0
1
31
9
0
31
21
20
19
9
0
21
20
19
31: MSB, 0:LSB @ 32bit
8
1
2
8
1
2
Lch Data
Rch Data
Figure 23. Mode 1/3 Timing (Normal mode, I2S Compatible, Normal/Double/Quad/Octal Speed)
[AK5397]
014011535-E-00 2014/11
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LRCK
31: MSB, 0:LSB @ 32bit
BICK(32fs)
SDTO1(Lch)
0
31
15
0
31
19
18
17
15
0
19
18
17
1
2
8
1
2
0
1
2
14
15
16
18
29
31
0
1
2
0
1
3
16
13
17
30
16
3
14
15
16
18
29
31
13
17
30
0
31
15
19
18
16
18
17
14
18
16
15
1
2
3
0
31
15
19
9
16
18
14
18
16
15
17
0
8
1
2
3
SDTO2(Rch)
Figure 24. Mode 1/3 Timing (Normal mode, I2S Compatible, Hex Speed)
31
LRCK (Mode 4)
BICK (256fs)
SDTO
30
0
Lch
32 BICK
256 BICK
Rch
32 BICK
30
31
LRCK (Mode 6)
31
30
0
Figure 25. Mode 4/6 Timing (TDM256 mode, MSB justified)
31
LRCK (Mode 5)
BICK (256fs)
SDTO
30
0
Lch
32 BICK
256 BICK
Rch
32 BICK
31
LRCK (Mode 7)
31
30
0
32 BICK
Figure 26. Mode 5/7 Timing (TDM256 mode, I2S Compatible)
[AK5397]
014011535-E-00 2014/11
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LRCK (Mode 8)
BICK (128fs)
128 BICK
Lch
32 BICK
Rch
32 BICK
SDTO
30
0
30
0
31
31
30
31
LRCK (Mode 10)
Figure 27. Mode 8/10 Timing (TDM128 mode, MSB justified)
LRCK (Mode 9)
BICK (128fs)
128 BICK
Lch
32 BICK
Rch
32 BICK
SDTO
30
0
30
0
31
31
31
LRCK (Mode 11)
32 BICK
Figure 28. Mode 9/11 Timing (TDM128 mode, I2S Compatible)
[AK5397]
014011535-E-00 2014/11
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■ Cascade TDM Mode
(1) TDM256 mode
The AK5397 supports cascading of up to four devices in a daisy chain configuration at TDM256 mode. In
this mode, the SDTO1 pin (SDTO2 pin) is connected to the TDMIN1 pin (TDMIN2 pin) of next device.
When four devices are connected by daisy-chaining as Figure 29, the SDTO1 pin (SDTO2 pin) of device
#4 can send 8ch TDM data.
48kHz
256fs
8ch TDM
256fs or 512fs
GND
LRCK
AK5397 #1
BICK
TDMIN1
SDTO1
SDTO2
MCLK
TDMIN2
8ch TDM
LRCK
AK5397 #2
BICK
TDMIN1
SDTO1
SDTO2
MCLK
TDMIN2
LRCK
AK5397 #3
BICK
TDMIN1
SDTO1
SDTO2
MCLK
TDMIN2
LRCK
AK5397 #4
BICK
TDMIN1
SDTO1
SDTO2
MCLK
TDMIN2
Figure 29. Cascade TDM Connection Diagram
[AK5397]
014011535-E-00 2014/11
- 30 -
LRCK
BICK(256fs)
#1 SDTO1/2(o)
256 BICK
30
31
#2 SDTO1/2(o)
L#1
32 BICK
R#1
32 BICK
30
1
30
1
31
31
0
0
30
1
L#2
32 BICK
30
1
R#2
32 BICK
31
31
0
0
30
1
L#1
32 BICK
30
1
R#1
32 BICK
31
31
0
0
L#3
32 BICK
R#3
32 BICK
L#2
32 BICK
R#2
32 BICK
L#1
32 BICK
R#1
32 BICK
L#4
32 BICK
R#4
32 BICK
L#3
32 BICK
R#3
32 BICK
L#2
32 BICK
R#2
32 BICK
L#1
32 BICK
R#1
32 BICK
#3 SDTO1/2(o)
#4 SDTO1/2(o)
30
31
30
31
30
31
30
1
30
1
31
31
0
0
30
1
30
1
31
31
0
0
30
1
30
1
31
31
0
0
30
1
30
1
31
31
0
0
30
1
30
1
31
31
0
0
30
1
30
1
31
31
0
0
30
1
30
1
31
31
0
0
Figure 30. Cascade TDM Timing (Mode 4; TDM256 mode, MSB justified, Slave mode)
[AK5397]
014011535-E-00 2014/11
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(2) TDM128 mode
The AK5397 supports cascading of two devices in a daisy chain configuration at TDM128 mode. In this
mode, the SDTO1 pin (SDTO2 pin) is connected to the TDMIN1 pin (TDMIN2 pin) of next device. When
two devices are connected by daisy-chaining as Figure 31, the SDTO1 pin (SDTO2 pin) of device #2 can
send 4ch TDM data.
48kHz or 96kHz or 192kHz
128fs
4ch TDM
256fs or 512fs
GND
LRCK
AK5397 #1
BICK
TDMIN1
SDTO1
SDTO2
MCLK
TDMIN2
4ch TDM
LRCK
AK5397 #2
BICK
TDMIN1
SDTO1
SDTO2
MCLK
TDMIN2
Figure 31. Cascade TDM Connection Diagram
LRCK
BICK(128fs)
128 BICK
#1 SDTO1/2(o)
32 BICK
L#1
32 BICK
R#1
32 BICK
32 BICK
L#2
32 BICK
R#2
L#1
32 BICK
R#1
#2 SDTO1/2(o)
30
31
30
31
30
28
3
1
31
4
0
29
2
30
28
3
1
31
4
0
29
2
30
28
3
1
31
4
0
29
2
30
28
3
1
31
4
0
29
2
30
28
3
1
31
4
0
29
2
30
28
3
1
31
4
0
29
2
Figure 32. Cascade TDM Timing (Mode 8; TDM128 mode, MSB justified, Slave mode)
[AK5397]
014011535-E-00 2014/11
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When using multiple devices in slave mode on cascade connection, internal operation timing of each
device may differ for one MCLK cycle depending on PDN, MCLK and BICK input timings. To prevent this
timing difference, BICK “↓” should be more than ± 10ns from MCLK “↑” and PDN “↑” should be more than
± 15ns from MCLK “↑” as shown in Table 7.
This timing can be achieved by inputting BICK divided half on MCLK “↓” when MCLK=2 x BICK (Normal
512fs, Double Speed) (Figure 33), and can be achieved by inputting BICK synchronized to MCLK when
MCLK=BICK (Normal 256fs mode, Quad speed) (Figure 34).
Parameter
Symbol
min
typ
max
Unit
MCLK “” to BICK “↓”
BICK “↓” to MCLK “”
MCLK “↑” to PDN “↑”
PDN “↑” to MCLK “↑”
tMCB
tBIM
tMPD
tPDM
10
10
15
15
ns
ns
ns
ns
Table 7. TDM Mode Clock Timing
tBIM
VIH
tMCB
MCLK
VIL
VIH
BICK
VIL
Figure 33. Audio Interface Timing (Slave mode, TDM Mode MCLK=2 x BICK)
tBIM
VIH
tMCB
MCLK
VIL
VIH
BICK
VIL
Figure 34. Audio Interface Timing (Slave mode, TDM Mode MCLK=BICK)
PDN
tPDM
MCLK
VIH
VIL
VIH
VIL
tMPD
Figure 35. Reset Timing (Slave mode, TDM Mode)
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014011535-E-00 2014/11
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■ Digital High Pass Filter
The AK5397 has a digital high pass filter for DC offset cancellation. The high pass filter is controlled by
the HPFE pin as shown by Table 8 and is reflected in both SDTO1 and SDTO2. The cut-off frequency of
the high pass filter is fixed 1.0Hz. The high pass filter is disabled in fs=384KHz mode or fs=768KHz
mode, and the setting of HPFE pin is ignored. The high pass filter setting should only be changed when
the PDN pin = “L”.
HPFE pin
HPF
L
OFF
H
ON
Table 8. Setting of HPF
■ Overflow Detection
The AK5397 has an overflow detect function for the analog input. The OVF pin becomes “H” for one cycle
after LRCK “↑” if either channel overflows (more than -0.276dBFS). The OVF output for overflowed
analog input has the same group delay as the ADC. The OVF pin is “L” for 1028/fs
(=21.41ms@fs=48kHz) after the PDN pin=“”, and then overflow detection is enabled.
■ Mono Mode
When the MONO pin is set to “H”, the AK5397 becomes MONO mode. In the Mono mode, L channel and
R channel data are summed digitally and divided into half. The dynamic range and S/N can be improved
about 3dB when the same analog signal is input to left and right channels. In this mode, the left and right
channel data on SDTO1 and SDTO2 are the same data.
MONO pin
SDTO1/2 Output Data
L
Stereo Mode
H
Mono Mode
Table 9. The setting of MONO mode.
LRCK
31: MSB, 0:LSB @ Lch 32bit
BICK(64fs)
SDTO1/2(Normal)
31
30
14
31
30
18
17
16
14
31
18
17
14
18
16
15
16
0
1
8
0
1
0
1
2
14
15
16
18
29
31
32
33
34
0
1
2
15
13
17
30
15
2
45
46
47
49
61
63
44
48
62
31
30
14
18
16
15
17
14
18
16
15
17
14
18
16
15
0
1
2
31
30
14
18
15
17
14
18
16
15
16
31
0
1
2
SDTO1/2(MONO)
31: MSB, 0:LSB @ Rch 32bit
31: MSB, 0:LSB @ Lch 32bit
31: MSB, 0:LSB @ Rch 32bit
Same Data
Figure 36. Audio Interface Timing (Normal mode or MONO mode, MSB justified)
[AK5397]
014011535-E-00 2014/11
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■ Digital Output Data
The AK5397 has two kinds of output data. These data are sent from SDTO1 and SDTO2 pins at the
same time. The SDTO1 pin is passed through “Sharp Roll-off” and the SDTO2 pin is passed through
“Short Delay Filter” or “Minimum Phase Filter” selected by the SDFIL pin as shown by Table 12.
When fs=384kHz, 768kHz, the AK5397 does not support “Short Delay Filter” and “Minimum Phase
Filter”. When fs=384kHz, the SDTO1 pin is passed through “Sharp Roll-off Filter”, and the SDTO2 pin is
“L”. When fs=768kHz, the SDTO1 and SDTO2 pins are passed through “Sharp Roll-off Filter” as shown
in Table 10. However, in MONO mode, the SDTO1 pin outputs the data of (Lch+Rch)/2, and the SDTO2
pin is “L” as shown in Table 11.
The output data of SDTO1 and SDTO2 pins can be disabled by using SDM1 and SDM2 pins respectively
as shown in Figure 37, Table 13 and Table 14. However, the SDM2 pin can output data if fs=768KHz
even when the SDM2 pin = “H”.
Sampling Speed
SDTO1 Output Data
SDTO2 Output Data
48kHz
Sharp Roll-off Filter
Short Delay Filter
96kHz
Sharp Roll-off Filter
Short Delay Filter
192kHz
Sharp Roll-off Filter
Short Delay Filter
384kHz
Sharp Roll-off Filter
“L” Output
768kHz
Sharp Roll-off Filter (Lch)
Sharp Roll-off Filter (Rch)
Table 10. SDTO1 / SDTO2 Output Data (MONO = “L”)
Sampling Speed
SDTO1 Output Data
SDTO2 Output Data
48kHz
Sharp Roll Off Filter
Short Delay Filter
96kHz
Sharp Roll Off Filter
Short Delay Filter
192kHz
Sharp Roll Off Filter
Short Delay Filter
384kHz, 768kHz
Sharp Roll Off filter
(Lch+Rch)/2
“L “Output
Table 11. SDTO1 / SDTO2 Output Data (MONO = “H”)
Delta-Sigma
Modulator
Digital Filter (Sharp)
Audio Interface
Digital Filter (Short)
Audio Interface
17
14
18
16
15
Sharp Roll Off Filter Block
Short Delay Filter Block
SDTO2
SDTO1
Figure 37. Digital Filter Block
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014011535-E-00 2014/11
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SDFIL pin
SDTO2 Output Data
L
Short Delay Filter
H
Minimum Phase Filter
Table 12. The setting of SDFIL pin
SDM1 pin
SDTO1 Output Data
L
Normal output
H
“L” output
Table 13. The setting of SD1M pin
SDM2 pin
SDTO2 Output Data
L
Normal output
H
“L” output
Table 14. The setting of SD2M pin
The SDTO1/2 outputs settle to data correspondent to the analog input signals after group delay time
when SDM1/2 pins are changed “H” → “L” and SDTO1/2 pins are in Normal Output Mode.
[AK5397]
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■ Power Down & Reset
The AK5397 is placed in the power-down mode by bringing the PDN pin “L” and the digital filter is also
reset at the same time. This reset should always be made after power-up. In the power-down mode, the
VCOM is AVSS level. An analog initialization cycle starts after exiting the power-down mode. The output
data SDTO1/2 are valid after 1028 cycles of LRCK clock in master mode (1029 cycles in slave mode).
During initialization, the ADC digital data outputs of both channels are forced to “0”. The ADC outputs
settle to data correspondent to the input signals after the end of initialization (This settling takes
approximately the group delay time).
The AK5397 should be reset once by bringing the PDN pin “L” after power-up. The AK5397 exits reset
and power down state by MCLK rising edge after setting the PDN pin to “H”. The internal timing starts
clocking by the rising edge (falling edge in I2S mode) of LRCK after exiting reset and power down state
by MCLK.
Normal Operation
Internal
State
PDN
Power-down
Initialize
Normal Operation
(1)
Idle Noise
GD
GD
“0”data
A/D In
(Analog)
A/D Out
(Digital)
OVF
(3)
(4)
“0”data
Idle Noise
VCOM
(2)
“0”data
“0”data
Notes:
(1) 1030/fs in slave mode, 1031/fs in master mode.
(2) The VCOM voltage reaches 2.5V in 1.53 ms (typ), 2.64ms (max) after the PDN pin = “H”.
(3) Analog output corresponding to digital input has group delay (GD).
(4) ADC and OVF outputs are “0” data in the power-down mode.
Figure 38. Power-down/up sequence example
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014011535-E-00 2014/11
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10. SYSTEM DESIGN
Figure 39 shows the system connection diagram. An evaluation board (AKD5397) is available for fast
evaluation as well as suggestions for peripheral circuitry.
LIN1+
VREFLL
1
LIN1-
44
2
TEST1
3
AVSS
4
HPFE
5
CKS0
6
CKS1
7
CKS2
8
PDN
9
DVDD
10
DVSS
11
VREFHL
43
AVSS
42
AVDD
41
TEST3
40
VCOM
39
TOUT
38
AVDD
37
AVSS
36
VREFHR
35
VREFLR
34
MCLK
12
BICK
13
LRCK
14
SDTO1
15
SDTO2
16
OVF
17
SDM1
18
SDM2
19
SDFIL
20
DIF
21
MSN
22
33
32
31
30
29
28
27
26
25
24
23
RIN2+
RIN2-
TEST2
AVSS
MONO
TDM1
TDM0
TDMIN2
TDMIN1
DVDD
DVSS
AK5397
Top View
+
Digital3.3v
0.1u
10u
Analog5.0V
0.1u
10u
+
0.1u
10u
+
0.1u
+
0.1u
+
Analog5.0V
10u
10u
Ceramic Capacitor
+
Electrolytic Capacitor
0.1u
+
10u
Digital3.3v
10u
0.1u
+
+
Micro-Controller
Micro-Controller
Note:
- AVSS and DVSS of the AK5397 must be distributed separately from the ground of external
controllers.
- All digital input pins should not be left floating.
Figure 39. System Design
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014011535-E-00 2014/11
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1. Grounding and Power Supply Decoupling
The AK5397 requires careful attention to power supply and grounding arrangements. To minimize digital
noise coupling, AVDD and DVDD should be individually de-coupled at the AK5397. AVDD is usually
supplied from analog supply in system and DVDD is supplied from digital supply in system. Power lines
of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc.
AVSS and DVSS must be connected to the same analog ground plane. Decoupling capacitors for high
frequency should be placed as near as possible to the supply pin.
2. Voltage Reference Inputs
The reference voltage for A/D converter is the difference between VREFHL/R pin and VREFLL/R pin.
VREFLL/R pins are connected to AVSS and an electrolytic capacitor over 10µF parallel with a 0.1µF
ceramic capacitor between the VREFHL/R pin and the VREFLL/R pin eliminates the effects of high
frequency noise. It is important that a ceramic capacitor should be as near to the pins as possible. All
digital signals, especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order
to avoid unwanted coupling into the AK5397.
VCOM is a signal ground of this chip. A 10µF electrolytic capacitor in parallel with a 0.1µF ceramic
capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may
be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in
order to avoid unwanted coupling into the AK5397.
3. Analog Inputs
The Analog input signal is differentially supplied into the modulator via the LIN+ (RIN+) and the LIN-
(RIN-) pins. The input voltage is the difference between the LIN+ (RIN+) and LIN- (RIN-) pins. The full
scale signal on each pin is nominally ±2.80V (typ). The output code format is two’s complement. The
output voltage (VAOUT) is positive full scale for 7FFFFFFFH (@32bit) and negative full scale for
80000000H (@32bit). The ideal VAOUT is 0V for 00000000H (@32bit). The internal HPF removes DC
offset.
The AK5397 samples the analog inputs at 128fs (6.144MHz@fs=48kHz, Normal Speed Mode). The
digital filter rejects noise above the stop band except for multiples of 128fs. The AK5397 includes an
anti-aliasing filter (RC filter) to attenuate a noise around 128fs.
The AK5397 requires a +5V analog supply voltage. Any voltage which exceeds the upper limit of
AVDD+0.3V and lower limit of AVSS-0.3V and any current beyond 10mA for the analog input pins
(LIN+/-, RIN+/-) should be avoided. Excessive currents to the input pins may damage the device. Hence
input pins must be protected from signals at or beyond these limits. Use caution especially when using
±15V for other analog circuits in the system.
[AK5397]
014011535-E-00 2014/11
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4. External Analog Circuit Examples
Figure 40 shows an input buffer circuit example 1. (1st order HPF; fc=0.795Hz, 2nd order LPF; fc=438kHz,
gain=-9.63dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for
BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is 17.0Vpp (AK5397: 5.6Vpp
Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=124dB, S/(N+D)=108dB.
Resistor values should be in ±1% accuracy.
When the bias voltage is more than 0.28xAVDD+0.6 [V], the internal diode is powered up.
1.0k
-
+
-
+
100
910
300
-
+
100
300
Analog In
8.5Vpp
220µ
LME49710
VA=+5V
VP=15V
1.0k
10µ
+
680
1100
0.1µ
Bias
VA+
2.80Vpp
2.80Vpp
VP+
VP-
Bias
910
Bias
33n
220µ
XLR
Vin+
Vin-
JP1
JP2
LME49710
LME
LME49710
AK5397 AIN+
AK5397 AIN-
5
5
+
+
Figure 40. Analog Input Buffer Circuit Example 1
fin
1Hz
10Hz
Frequency Response
-2.13dB
-0.03dB
Table 15. Frequency Response of HPF
fin
20kHz
40kHz
80kHz
6.144MHz
Frequency Response
0.01dB
-0.04dB
-0.14dB
30.31dB
Table 16. Frequency Response of LPF
[AK5397]
014011535-E-00 2014/11
- 40 -
Figure 41 shows an input buffer circuit example 1. (1st order HPF; fc=0.795Hz, 2nd order LPF; fc=290kHz,
gain=963 dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for
BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is 17.0Vpp (AK5397: 5.6Vpp
Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=127dB, S/(N+D)=100dB.
Resistor values should be in ±1% accuracy.
When the bias voltage is more than 0.28xAVDD+0.6 [V], the internal diode is powered up.
1.0k
-
+
-
+
100
910
300
-
+
100
300
Analog In
8.5Vpp
220µ
LME49990
VA=+5V
VP=15V
1.0k
10µ
+
680
1100
0.1µ
Bias
VA+
2.80Vpp
2.80Vpp
VP+
VP-
Bias
910
Bias
33n
220µ
XLR
Vin+
Vin-
JP1
JP2
LME49990
LME49990
AK5397 AIN+
AK5397 AIN-
5
5
33n
33n
+
+
Figure 41. Analog Input Buffer Circuit Example 2
fin
1Hz
10Hz
Frequency Response
-2.1dB
-0.03dB
Table 17. Frequency Response of HPF
fin
20kHz
40kHz
80kHz
6.144MHz
Frequency Response
-0.01dB
-0.02dB
-0.08dB
33.82dB
Table 18. Frequency Response of LPF
[AK5397]
014011535-E-00 2014/11
- 41 -
11. PACKAGE
■ Outline Dimensions
0.09~0.20
0.37
10.0±0.20
1.60 Max
1
11
23
33
44pin LQFP (Unit: mm)
10.0±0.20
12.0±0.20
34
44
0.80 BSC
22
12
12.0±0.20
0.05~0.15
07
0.60.15
1.40 0.05
+0.08
–0.07
0.10
C
C
1.00 Ref
0.20
M
C
A-B
A
B
[AK5397]
014011535-E-00 2014/11
- 42 -
■ Material & Lead finish
Package molding compound: Epoxy, Halogen (bromine and chlorine) free
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
■ MARKING
AK5397EQ
XXXXXXX
AKM
1
1) Pin #1 indication
2) Audio 4 pro Logo
3) Date Code: XXXXXXX(7 digits)
4) Marking Code: AK5397
5) AKM Logo
12. Ordering Guide
AK5397EQ 10 +70C 44pin LQFP (0.8mm pitch)
AKD5397 Evaluation Board for AK5397
[AK5397]
014011535-E-00 2014/11
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13. Revision History
Date (Y/M/D)
Revision
Reason
Page
Contents
14/11/14
00
First Edition
[AK5397]
014011535-E-00 2014/11
- 44 -
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other
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explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or
related technology or any information contained in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws
and regulations. The Products and related technology may not be used for or incorporated into
any products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
and regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as
a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
