LM3409,LM3409HV Application Note 1953 LM3409HV Evaluation Board Literature Number: SNVA390C National Semiconductor Application Note 1953 James Patterson November 20, 2009 EFFICIENCY WITH 12 SERIES LEDS AT 1.5A Introduction This evaluation board showcases the LM3409HV PFET controller for a buck current regulator. It is designed to drive 12 LEDs (VO = 42V) at a maximum average LED current (ILED = 1.5A) from a DC input voltage (VIN = 48V). The switching frequency (fSW = 400 kHz) is targeted for the nominal operating point, however fSW varies across the entire operating range. The circuit can accept an input voltage of 6V-75V. However, if the input voltage drops below the regulated LED string voltage, the converter goes into dropout and VO = VIN ideally. The PCB is made using 4 layers of 2 oz. copper with FR4 dieletric. The evaluation board showcases all features of the LM3409HV including analog dimming using the IADJ pin and internal PWM dimming using the EN pin. High frequency external parallel FET shunt PWM dimming can also be evaluated. The board has a header (J1) with a removable jumper, which is used to select the PWM dimming method. The evaluation board has a right angle connector (J2) which can mate with an external LED load board allowing for the LEDs to be mounted close to the driver. This reduces potential ringing when there is no output capacitor. Alternatively, the LED+ and LED- turrets can be used to connect the LED load. This board can be easily modified to demonstrate other operating points as shown in the Alternate Designs section. The LM3409/09HV datasheet Design Procedure can be used to design for any set of specifications. LM3409HV Evaluation Board LM3409HV Evaluation Board 30093549 Since the board contains a buck regulator designed for 48V input, the efficiency is very high at input voltages near or less than 48V. The switching frequency increases as input voltage increases, yielding lower efficiency at higher input voltages. Note that increasing the off-time resistor (R6) will increase the efficiency at high input voltage. Schematic (c) 2009 National Semiconductor Corporation 300935 www.national.com AN-1953 30093501 AN-1953 Pin Descriptions Pin(s) Name Description 1 UVLO Input under-voltage lockout Application Information Connect to a resistor divider from VIN and GND. Turn-on threshold is 1.24V and hysteresis for turn-off is provided by a 22A current source. 2 IADJ Analog LED current adjust Apply a voltage between 0 - 1.24V, connect a resistor to GND, or leave open to set the current sense threshold voltage. 3 EN Logic level enable / PWM dimming 4 COFF Off-time programming Apply a voltage >1.74V to enable device, a PWM signal to dim, or a voltage <0.5V for low power shutdown. Connect resistor to VO, and capacitor to GND to set the off-time. 5 GND Ground 6 PGATE Gate drive Connect to the system ground. 7 CSN Negative current sense Connect to the negative side of the sense resistor. 8 CSP Positive current sense Connect to the positive side of the sense resistor (VIN). 9 VCC VIN- referenced linear regulator output Connect at least a 1F ceramic capacitor to VIN. The regulator provides power for the PFET drive. 10 VIN Input voltage DAP DAP Thermal pad on bottom of IC Connect to the gate of the external PFET. Connect to the input voltage. Connect to pin 5 (GND). Place 4-6 vias from DAP to bottom GND plane. Bill of Materials Qty Part ID Part Value Manufacturer Part Number 1 U1 Buck controller NSC LM3409HVMY 2 C1, C2 2.2F X7R 10% 100V MURATA GRM43ER72A225KA01L 1 C3 0.1F X7R 10% 100V MURATA GRM188R72A104KA35D 1 C4 1.0F X7R 10% 16V TDK C1608X7R1C105K 1 C5 0.1F X7R 10% 50V MURATA GRM319R71H104KA01D 1 C6 0.1F X7R 10% 50V MURATA GCM188R71H104KA57D 1 C7 470pF X7R 10% 50V TDK C1608X7R1H471K 3 C8, D2, R11 No Load 1 C9 2200pF X7R 10% 50V MURATA GRM188R71H222KA01D 1 Q1 PMOS 100V 3.8A ZETEX ZXMP10A18KTC 1 Q2 CMOS 30V 2A FAIRCHILD FDC6333C 1 Q3 NMOS 100V 7.5A FAIRCHILD FDS3672 1 D1 Schottky 100V 3A VISHAY SS3H10-E3/57T 1 L1 33 H 20% 3.2A TDK SLF12575T-330M3R2 2 R1, R2 1 1% VISHAY CRCW06031R00FNEA 1 R3 10k 1% VISHAY CRCW060310K0FKEA 1 R4 100 1% VISHAY CRCW0603100RFKEA 1 R5 0 1% VISHAY CRCW06030000Z0EA 1 R6 16.5k 1% VISHAY CRCW060316K5FKEA 1 R7 6.98k 1% VISHAY CRCW06036K98FKEA 1 R8 49.9k 1% VISHAY CRCW060349K9FKEA 1 R9 0.15 1% 1W VISHAY WSL2512R1500FEA 1 R10 1k 1% VISHAY CRCW06031K00FKEA 1 J1 3 pin header MOLEX 22-28-4033 1 J2 2x7 pin RA shrouded SAMTEC TSSH-107-01-S-D-RA 2 VIN, GND banana jack KEYSTONE 575-8 7 EN, Vadj, +5V, GND2, PWM2, LED+, LED- turret KEYSTONE 1502-2 www.national.com 2 AN-1953 PCB Layout The 2 inner planes are GND and VIN. 30093540 Top Layer 30093541 Bottom Layer 3 www.national.com AN-1953 The chosen component from step 2 is: Design Procedure SPECIFICATIONS VIN = 48V; VIN-MAX = 75V VO = 42V fSW = 400kHz ILED = 1.5A 3. AVERAGE LED CURRENT Determine IL-MAX: iLED-PP = iL-PP = 300mA vIN-PP = 1.44V VTURN-ON = 10V; VHYS = 1.1V = 0.97 Assume VADJ = 1.24V and solve for R9: 1. NOMINAL SWITCHING FREQUENCY Assume C7 = 470pF and = 0.97. Solve for R6: The closest 1% tolerance resistor is 0.15 therefore the ILED is: The chosen component from step 3 is: The closest 1% tolerance resistor is 16.5 k therefore the actual tOFF and target fSW are: 4. OUTPUT CAPACITANCE No output capacitance is necessary. 5. INPUT CAPACITANCE Determine tON: Solve for CIN-MIN: The chosen components from step 1 are: Choose CIN: 2. INDUCTOR RIPPLE CURRENT Solve for L1: Determine IIN-RMS: The closest standard inductor value is 33 H therefore the actual iL-PP is: www.national.com The chosen components from step 5 are: 4 AN-1953 Solve for R7: 6. P-CHANNEL MOSFET Determine minimum Q1 voltage rating and current rating: The closest 1% tolerance resistor is 6.98 k so VTURN-ON is: A 100V 3.8A PFET is chosen with RDS-ON = 190m and Qg = 20nC. Determine IT-RMS and PT: The chosen components from step 8 are: 9. IADJ CONNECTION METHOD The IADJ pin controls the high-side current sense threshold in three ways outlined in the datasheet. The LM3409HV evaluation board allows for all three methods to be evaluated using C6, R10, and the VADJ terminal. Method #1: If the VADJ terminal is not connected to the power supply, then the internal Zener diode biases the pin to 1.24V and the current sense threshold is nominally 248mV. Method #2: Applying an external voltage to the VADJ terminal between 0 and 1.24V linearly scales the current sense threshold between 0 and 248mV nominally. It can be necessary to have an RC filter when using an external power supply in order to remove any high frequency noise or oscillations created by the power supply and the connecting cables. The filter is chosen by assuming a standard value of C6 = 0.1F and solving for a cut-off frequency fC < 2kHz: The chosen component from step 6 is: 7. RE-CIRCULATING DIODE Determine minimum D1 voltage rating and current rating: Since an exact fC is not critical, a standard value of 1k is used. The Typical Waveforms section shows a typical LED current waveform when analog dimming using an external voltage source. Method #3: (This method requires modification of the received evaluation board). The internal 5A current source can be used to bias the voltage across an external resistor to ground (REXT) across C6 on the evaluation board. The resistor is sized knowing the desired average LED current ILED (must be < 1.5A which is default using method #1): A 100V 3A diode is chosen with VD = 750mV. Determine PD: The chosen component from step 7 is: 8. INPUT UNDER-VOLTAGE LOCKOUT (UVLO) Solve for R8: The chosen components from step 9 are: The closest 1% tolerance resistor is 49.9 k so VHYS is: 5 www.national.com AN-1953 erly translates the duty cycle to the shunt dimming FET. Q2 also needs to be fast and rated for 5V and fairly small current, therefore a 30V, 2A fast CMOS FET was chosen. R1 and R2 are 1 resistors to slow down the rising edge of the FETs slightly to prevent the gate from ringing. R3 is a 10k pull-up resistor to ensure the CMOS gate is pulled all the way to 5V if a sub-5V PWM signal is applied to PWM2. The bypass capacitor (C5) for the 5V power supply is chosen to be 0.1F. See the Shunt FET Circuit Modification section for an improvement that can be made to this circuit. Method #3: Internal PWM dimming using the EN pin can be evaluated by removing the jumper from header J1. An external PWM signal can then be applied to the EN terminal to provide PWM dimming. The Typical Waveforms section shows typical LED current waveforms during both types of PWM dimming. The chosen components from step 10 are: 10. PWM DIMMING METHOD The LM3409HV evaluation board allows for PWM dimming to be evaluated as follows: 30093502 Method #1: If no PWM dimming is desired, a jumper should be placed in position 1 (shorts pins 1 and 2) on header J1. This shorts VIN and EN which ensures the controller is always enabled if an input voltage greater than 1.74V is applied. Method #2: External parallel FET shunt dimming can be evaluated by placing the jumper in position 2 (shorts pins 2 and 3) on header J1. This connects the capacitive coupling circuit to the EN pin as suggested in the datasheet. The resistor (R4) can be solved for assuming a standard capacitor value C9 = 2.2nF and a desired time constant (t C = 220ns < tOFF) as follows: The external shunt FET dimming circuit shown below is designed using an N-channel MosFET (Q3), a CMOS FET (Q2), two gate current limiting resistors (R1 and R2), a pull-up resistor (R3), and a bypass capacitor (C5). With an external 5V power supply attached to the 5V terminal and an external PWM signal attached to the PWM2 terminal, the shunt dimming circuit is complete. Q3 is the shunt dimFET which conducts the LED current when turned on and blocks the LED voltage when turned off. Q3 needs to be fast and rated for VO and ILED. For design flexibility, a fast 100V, 7.5A NFET is chosen. Q2 is necessary to invert the PWM signal so it prop- 11. BYPASS CAPACITOR The internal regulator requires at least 1F of ceramic capacitance with a voltage rating of 16V. The chosen component from step 11 is: 30093533 External shunt FET dimming circuit with EN pin coupling www.national.com 6 When the shunt FET (Q3) is on, the LM3409 is driving current into a short, therefore a maximum off-time (typical 300 s) occurs followed by a minimum on-time. Maximum off-time followed by minimum on-time continues until Q3 is turned off. At low dimming frequencies and depending on the duty cycle, the inductor current may be at a very low level when the Q3 turns off. This will eliminate the benefits of using the shunt FET over the EN pin because the inductor will have to slew the current back to the nominal value anyways. A simple modification to the external parallel FET dimming circuit will keep the inductor current close to its nominal value when Q3 is turned off. This modification will ensure that the rise time of the LED current is only limited by the turn-off time of the shunt FET as desired. The following circuit additions 30093550 Multiple off-timers for shunt FET dimming circuit 7 www.national.com AN-1953 allow for two different off-times to occur. When Q3 is off, the standard off-timer referenced from VO is set. However when the Q3 is on, a second off-timer referenced to the gate signal of the Q3 is enabled and a controlled (non-maximum) off-time is set. This modification includes 2 extra diodes (i.e. BAT54H) and one resistor (ROFF2) and is only relevant when shunt FET PWM dimming below 10 kHz or so. In general, this second off-timer should be set to allow the inductor current to fall no more than 10% of its nominal value. A simple approximation can be used to find ROFF2: Shunt FET Circuit Modification AN-1953 Typical Waveforms TA = +25C, VIN = 48V and VO = 42V. 30093543 30093544 20kHz 50% EN pin PWM dimming 20kHz 50% EN pin PWM dimming (rising edge) 30093548 30093547 100kHz 50% External FET PWM dimming (rising edge) 100kHz 50% External FET PWM dimming 30093545 30093546 Analog dimming minimum (VADJ = 0V) www.national.com Analog dimming maximum (VADJ open) 8 Alternate designs with the LM3409HV evaluation board are possible with very few changes to the existing hardware. The evaluation board FETs and diodes are already rated higher than necessary for design flexibility. The input UVLO can remain the same and the input capacitance is sufficient for most designs, though the input voltage ripple will change. Other designs can evaluated by changing R6, R9, L1, and C8. Specification / Component Design 1 Design 2 Design 3 Design 4 Design 5 Dimming Method PWM PWM Analog PWM Analog VIN 24V 36V 48V 65V 75V VO 14V 24V 35V 56V 42V fSW 500 kHz 450 kHz 300 kHz 350 kHz 300 kHz ILED 1A 700 mA 2A 3A 1.5A iLED 450 mA 250 mA 70 mA 1A 80 mA R6 15.4 k 25.5 k 46.4 k 24.9 k 95.3 k R9 L1 0.2 22 H 0.3 68 H 0.12 150 H 0.07 15 H 0.15 330 H C8 None None 2.2 F None 2.2 F 9 www.national.com AN-1953 The table below gives the main specifications for five different designs and the corresponding values for R6, R9, L1 and C8. The RMS current rating of L1 should be at least 50% higher than the specified ILED. Designs 3 and 5 are optimized for best analog dimming range, while designs 1, 2, and 4 are optimized for best PWM dimming range. These are just examples, however any combination of specifications can be achieved by following the Design Procedure in the LM3409/09HV datasheet. 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