MC10H131P - ON Semiconductor

 Semiconductor Components Industries, LLC, 2003

November, 2003 − Rev. 1 1Publication Order Number:

AND8090/D

AC Characteristics of ECL

Devices

APPLICATION NOTE USAGE

This application note provides a general overview of the

AC characteristics that are specified on the

ON Semiconductor data sheets for MECL 10K, 10H,

100H, ECLinPS, ECLinPS Lite, and GigaComm SiGe

devices. Data sheet information takes precedence over this

application note if there are differences. This application

note includes the following information:

•AC Test Bench Information

•AC Characteristic Definitions

•AC Characteristic Test Methods

•AC Characteristic Examples

•AC Characteristic Symbols

•AC Characteristic References

TABLE OF CONTENTS

Lab Testing

Test Bench Overview 2. . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Initialization 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Bench Equipment 3. . . . . . . . . . . . . . . . . . . . . . . . . .

AC Test Boards 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Levels

AC HIGH and LOW Levels 5. . . . . . . . . . . . . . . . . . . . . .

Oscilloscope Averaging 5. . . . . . . . . . . . . . . . . . . . . . . . .

Input Levels 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Levels 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Swing 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Timing

Duty Cycle 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Input Frequency 6. . . . . . . . . . . . . . . . . . . . . .

Differential Characteristics

Differential Input Application 7. . . . . . . . . . . . . . . . . . . . .

Unused Output Termination 7. . . . . . . . . . . . . . . . . . . . . .

Differential Crosspoint 7. . . . . . . . . . . . . . . . . . . . . . . . . .

Input Voltage Swing 7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Input Swing 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential Characteristics (continued)

Common Mode Range 7. . . . . . . . . . . . . . . . . . . . . . . . . .

Differential Input Example 8. . . . . . . . . . . . . . . . . . . . . . .

Single−Ended Characteristics

Single−Ended Inputs 8. . . . . . . . . . . . . . . . . . . . . . . . . . .

Single−Ended 50% Points 8. . . . . . . . . . . . . . . . . . . . . . .

Single–Ended Input Voltage Range 8. . . . . . . . . . . . . . .

Single–Ended Input Test Level 8. . . . . . . . . . . . . . . . . . .

Differential Inputs (Single–Ended Mode) 9. . . . . . . . . . .

Timing Characteristics

Output Rise and Fall Times 9. . . . . . . . . . . . . . . . . . . . . .

Propagation Delay 10. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Skew (Duty Cycle) 11. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Skew (Within Device) 11. . . . . . . . . . . . . . . . . . . . . . . . . .

Skew (Device to Device) 11. . . . . . . . . . . . . . . . . . . . . . .

Minimum Input Pulse Width 11. . . . . . . . . . . . . . . . . . . . .

Setup and Hold Time 12. . . . . . . . . . . . . . . . . . . . . . . . . .

Set and Reset Recovery Time 14. . . . . . . . . . . . . . . . . .

Jitter

Jitter Overview 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Random Jitter 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RJ Confidence Levels 15. . . . . . . . . . . . . . . . . . . . . . . . .

Total RJ Test Setup 16. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Equipment RJ Test Setup 16. . . . . . . . . . . . . . . . . .

DUT RJ Calculation 16. . . . . . . . . . . . . . . . . . . . . . . . . . .

Deterministic Jitter 17. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Total DJ Test Setup 17. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Equipment DJ Test Setup 18. . . . . . . . . . . . . . . . . .

DUT DJ Calculation 18. . . . . . . . . . . . . . . . . . . . . . . . . . .

Symbols and Acronyms

Symbols and Acronyms Table 19. . . . . . . . . . . . . . . . . . .

References

AC Characteristic References 20. . . . . . . . . . . . . . . . . . .

APPLICATION NOTE

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LAB TESTING

Test Bench Overview

Specialized test benches are used to determine the AC

characteristics o f the Device−Under−Test (DUT). A typical

test bench setup for a differential device is shown in

Figure 1.

Test Initialization

•The test cables are connected from the pulse generator to

the appropriate DUT test board input connectors.

•The test cables are connected from the DUT test board

output connectors to the appropriate digital sampling

oscilloscope input connectors.

•The power supply cables are connected to the DUT test

board power supply connectors.

•The airflow regulator is set to 500 lfpm and the desired

DUT ambient air temperature. The DUT is in this

environment for a minimum of 3 minutes before testing

begins. Data sheet specifications are typically given for

−40°C, 25°C, and 85°C.

CHANNEL A (50 

CHANNEL B (50 

TRIGGER

CHANNEL C (50 

CHANNEL D (50 

TRIGGER

PULSE

GENERATOR

OSCILLOSCOPE

VCC

50  COAX

VEE

50  COAX

50  COAX50  COAX

50  COAX

Figure 1. AC Characterization Test Bench Setup

Test Board

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Test Bench Equipment

AC characterization equipment is carefully selected to

ensure that the test equipment is suitable for the devices

to be tested, and that the measurements are accurate

and repeatable. For example, sampling head bandwidth

must be wide enough for accurate rise and fall time

measurements. The test equipment that is currently used by

ON Semiconductor is listed in Table 1. Further information

on the test equipment can be found at the respective

manufacturer’s website.

Table 1. ON Semiconductor Test Bench Equipment

Test Equipment Manufacturer/Model Equipment Notes

Digital Sampling Oscilloscope Tektronix 11801C

SD24/26 20 GHz Module Customers can use lower performance equipment for evaluation,

but may not be able to duplicate all of ON Semiconductor

measurements (e.g., rise/fall and propagation delay times).

Digital Sampling Oscilloscope Tektronix TDS8000

80E03 20 GHz Module

80E01 50 GHz Module

Customers can use lower performance equipment for evaluation,

but may not be able to duplicate all of ON Semiconductor

measurements (e.g., rise/fall and propagation delay times). Note

that the 50 GHz sampling module is required for GigaComm

devices as they typically have rise and fall times between 20 ps

and 50 ps.

Pulse/Pattern Generators Tektronix HFS 9009 Maximum pulse frequency of 630 MHz.

Agilent 8133A Maximum pulse frequency of 3.0 GHz.

Advantest D3186 Maximum pulse frequency of 12 GHz.

DC Power Supplies Agilent HP6624A Used to supply VCC, VEE, and specialized bias voltages.

Low−resistance supply voltage connections and RF quality supply

filter capacitors are designed into the AC test boards that are used

to mount the DUT.

Test Cables Various Manufacturers High bandwidth, low−loss matched cables are used to ensure

accurate measurements. Each cable of an input/output cable pair

is the same length and has a characteristic impedance of 50 ohms.

Air Flow Regulator Temptronics Thermostream Establishes the DUT ambient temperature.

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AC Test Boards

Each test device is mounted on a controlled impedance

test board that is specifically designed to measure AC

characteristics. Test boards typically have multiple layers.

An example of an AC characteristic test board is shown in

Figures 2 through 4. This particular test board is used to test

ECLinPS Lite SOIC−8 devices.

Figure 2. Top Photo of the AC Test Board

Figure 3. Top Schematic of the AC Test Board Figure 4. Bottom Schematic of the AC Test Board

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SIGNAL LEVELS

AC HIGH and LOW Levels − The HIGH level referred

to in this application note corresponds to the IEEE “topline,”

and the LOW level corresponds to the IEEE “baseline” as

shown in Figure 5. The 50% point lies halfway between the

HIGH and LOW levels. Refer to IEEE Standard 194−1977

for further voltage level information.

Figure 5. HIGH and LOW Waveform Definition

HIGH

LOW

50%

(topline)

(baseline)

VIH/VOH

VIL/VOL

Input Levels − Operational differential input levels are

specified by V PP and the V IHCMR range as described in the

“Differential Characteristics” section. Operational

single−ended input levels are specified by VIL and VIH as

described in the “Single−Ended Characteristics” section.

Output Levels − Output signals may be differential or

single−ended. AC characteristics for ON Semiconductor

devices with ECL outputs are typically measured for an

output termination of 50  to VTT (the termination voltage

equal to V CC − 2.0 V). HIGH and LOW output levels range

between the boundary and threshold values for the

respective HIGH and LOW input levels specified on data

sheets. Output logic levels are shown in Figure 6.

VOHmax

HIGH

VOHmin

VOLmax

LOW

VOLmin

Boundary

Threshold

Boundary

Figure 6. Output Logic Levels

Oscilloscope Averaging − Digital sampling oscilloscopes

use an algorithm to determine the average level over a pulse

width to e stablish t he H IGH and L OW l evels. A n example i s

shown in Figure 7. The horizontal cursors at the HIGH and

LOW levels indicate the determined average levels.

Figure 7. HIGH and LOW Waveform Levels

HIGH

LOW

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Output Swing − The output swing (VOUTpp) is measured

between the HIGH and LOW levels of each individual

differential or single−ended output. The output voltage

swing for each individual output is defined by the following

equation and Figure 8.

VOUTPP VOH VOL

VOUTpp

VOH

VOL

50%

Figure 8. Output Voltage Swing

The V OUTpp value is shown as the vertical axis in the data

sheet maximum frequency plots (refer to the “Maximum

Input Frequency” section).

SIGNAL TIMING

Duty Cycle − The duty cycle is the ratio of the HIGH pulse

width (PW) to the signal period and is described by the

following equations:

Signal Period = Time between adjacent rising edges

Duty Cycle = (HIGH Pulse Width/Signal Period) * 100%

The 50% points are used to measure the HIGH pulse

width and the signal period. AC characteristics for

ON Semiconductor devices are typically measured for a

50% duty cycle input. A 50% duty cycle input/output is

shown in Figure 9. Note that the HIGH and LOW pulse

widths (PWH and PWL respectively) are equal for a 50%

duty cycle signal.

PWH

HIGH

LOW

50%

PWL

Fifty Percent Duty Cycle: PWH = PWL

Figure 9. Input/Output Duty Cycle

Maximum Input Frequency − This is a typical device

performance value. It is the highest allowable input

frequency for proper device operation (fMAX). For shift

registers, it is referred to as the Maximum Shift Frequency

(fSHIFT). It is the frequency where the output voltage swing

(VOUTpp) is equal to a minimum value that is determined by

the device type, or it is the frequency where the device no

longer functions properly.

An output voltage swing versus input frequency plot is

typically included with data sheets. For the MC100EP90

example shown in Figure 10, the maximum listed input

frequency of 3.0 GHz occurs at an output voltage swing of

approximately 400 mV. The jitter shown in Figure 10 is

described in a later section.

100

200

300

400

500

600

700

800

900

0 1000 2000 3000 4000

Figure 10. Output Voltage vs. Input Frequency Example

FREQUENCY (MHz)

VOLTAGE (mV)

ps (RMS)

(JITTER)

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

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DIFFERENTIAL CHARACTERISTICS

Section Note − This section explains concepts that only

apply for differential inputs and/or outputs. Differential

inputs and outputs have true and inverted pins, and are often

referred to as “complimentary” inputs and outputs. An

example of a differential input is a true data input (D), and

an inverted data input (D).

Differential Input Application – True and inverted input

signals must be applied in order to obtain accurate

differential test measurements for differential input devices.

The true output of the pulse generator is connected to the true

input of the DUT, and the inverted output of the pulse

generator is connected to the inverted input of the DUT.

Unused Output Termination – An unused output of a

differential pair must be terminated in the same manner as

the used output in order to obtain accurate measurements.

Differential Crosspoint – Differential crosspoints are

used as a measurement point for differential input and

differential output signals. A differential crosspoint (Xpt) is

located where the true and inverted inputs or outputs

intersect as shown in Figure 11.

Figure 11. Differential Input/Output Crosspoint

D or Q

Xpt

Input Voltage Swing – The minimum input voltage

swing (VPPmin) is found by decreasing the swing between

the true and inverted inputs until the device no longer

performs its specified function. The maximum input voltage

swing (VPPmax) is determined by the internal circuitry of a

specific device. The differential input voltage swing is

defined by the following equations and Figure 12.

Figure 12. Differential Input Voltage Swing

Xpt

VPP = | VIN(true) − VIN(inverted) |

VPP(min)  VPP  VPP(max)

VPP(min) VPP(max)

Test Input Swing – The typical AC test input swing for

differential inputs is shown below:

VPP(AC Test) |VIN(true) VIN(inverted) |750 mV

Common Mode Range – The most positive of the true

and inverted input voltages (i.e., the HIGH level) must be

within the differential HIGH input common mode range

(VIHCMR) for proper operation. To restate, the common

mode range places an upper and lower boundary on the

differential HIGH input level. The HIGH input common

mode range is specified in relation to the input voltage swing

(VPP). The relationship is determined by the device type, so

refer to the device data sheet for specific information. The

differential HIGH input common mode range is defined by

the following equations.

VIHCMR(min) VIH VIHCMR(max)

VIHCMR(max) varies 1 : 1 with VCC

VIHCMR(min) varies1:1withV

The example shown in Figure 13 is typical, and specifies

the common mode range with respect to the entire VPP

range.

Figure 13. Common Mode Range

VIHCMR(max)

VIH for all VPP

VIHCMR(min)

The MC100LVEL14 example shown in Figure 14

specifies the common mode range with respect to two VPP

ranges.

Figure 14. MC100LVEL14 Common Mode Range

1.2 V

2.9 V

VIH for VPP < 0.5 V

VIHCMR(max)

VIHCMR(min)

VIHCMR(max)

VIH for VPP  0.5 V

VIHCMR(min)

2.9 V

1.4 V

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Differential Input Example – The relationship between

VPP and VIHCMR is used to completely define valid

differential input signals. The following MC100EP116

example is for the 5.0 V PECL mode (VCC = 5.0 V, VEE =

GND), and illustrates the valid input voltages for an

application which uses the minimum and maximum input

voltage swings for the device. Note that both the VPP and the

VIHCMR conditions are satisfied for each of the two

waveforms.

VIHCMR(min) 2.0 V VIH VIHCMR(max) 5.0 V

VPP(min) 150 mV VPP VPP(max) 1200 mV

The top waveform in Figure 15 represents the highest

possible LOW input value where:

VIL(max) VIH(max) VPP(min) 5.0 0.15 4.85 V

The bottom waveform in Figure 15 represents the lowest

possible LOW input value where:

VIL(min) VIH(min) VPP(max) 2.0 1.2 0.80 V

Figure 15. MC100EP116 Differential Input Voltage

5.0 V

4.8 V

3.0 V

2.0 V

1.0 V

VIH = 5.0 V

VPP = 0.15 V

VIL = 4.85 V

VIHCMR(min)

VIHCMR(max)

VPP = 1.2 V

VIH = 2.0 V

VIL = 0.8 V

SINGLE−ENDED CHARACTERISTICS

Section Note – This section explains concepts that only

apply to single−ended inputs and/or outputs.

Single−Ended Inputs – Many inputs/outputs are

single−ended instead of differential, i.e. they have a single

input/output instead of a pair of true and inverted

inputs/outputs.

Single−Ended 50% Points – Single−ended 50% points

are used as a measurement point for single−ended input and

output signals. A 50% point is the single−ended signal level

which lies halfway between the HIGH and LOW

input/output levels as shown in Figure 16.

Figure 16. Single−Ended Input/Output 50% Point

VIH or VOH

VIL or VOL

50%

Note from the following MC100EP116 calculations for

the 5.0 V PECL mode that the 50% point voltage is not a

fixed voltage. The 50% point varies with the input voltage

range.

50% Point(max) [VIH(max) VIL(max)]2

(4120 3375)23748 mV

50% Point(min) [VIH(min) VIL(min)]2

(3775 3190)23483 mV

Single−Ended Input Voltage Range – Single−ended

input HIGH and LOW levels have a boundary and a

threshold as shown in Figure 17. Once an input crosses a

logic threshold, the logic state is guaranteed to change to the

new state.

Figure 17. Single−Ended Input Logic Levels

VIHmax

HIGH

VIHmin

VILmax

LOW

VILmin

Boundary

Threshold

Boundary

The MC100EP116 example shown in Figure 18 is for the

5.0 V PECL mode.

Figure 18. MC100EP116 Single−Ended Input Example

VIHmax

HIGH

VIHmin

VILmax

LOW

VILmin

4120 mV

3775 mV

3375 mV

3190 mV

Single−Ended Input Test Level – The AC test

single−ended input swing is typically given by the following

equation:

VIN(swing) |VIH VIL|750 mV

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Differential Inputs (Single−Ended Mode) – Either input

of a differential pair may be used individually if the unused

input of the differential pair is connected to VBB (the

switching reference voltage). The switching reference

voltage is provided by many differential devices. Figure 19

illustrates the use of the true input as the single−ended input.

Note that the unused inverted output is terminated in the

same fashion as the true output.

Figure 19. Differential Input in Single−Ended Mode

VIH

VIL

50% 50%

VOH

VOL

VBB

Q1 Use Q1 Termination

The switching reference voltage provides a switching

point that is approximately halfway between the HIGH and

LOW levels. As an example, the MC100EP116 data sheet

specifies the following switching reference voltage range

for the 5.0 V PECL mode. The MC100EP116 50% point

range previously calculated is listed below the VBB range.

3475 mV VBB 3675 mV

3483 mV 50% Point 3748 mV

Note that the VBB range is very close to the 50% point

range. This is true because the switching reference voltage

provides a switching point for a differential input in

single−ended mode that is analogous to the 50% point range

for normal single−ended inputs.

TIMING CHARACTERISTICS

Output Rise and Fall Times

ECL Output Devices – The output rise time for ECL

devices is the time required to rise from the 20% level to the

80% level of the output rising edge. The output fall time for

ECL devices is the time required to fall from the 80% level

to the 20% level of the output falling edge. The output rise

and fall times for devices with ECL outputs is shown in

Figure 20.

Figure 20. ECL Output Rise and Fall Times

tRtF

HIGH

LOW 20%

80%

Non−ECL Output Devices – Refer to the translator data

sheets as different conditions are used to specify the output

rise and fall times. One type of condition specifies output

rise and fall times between the 10% and 90% output levels.

For example, the rise and fall times for the MC100ELT21

PECL to TTL translator are specified between the 10% and

90% output levels as shown in Figure 21.

Figure 21. TTL Output Rise and Fall

Time Percentages

tRtF

90%

10%

HIGH

LOW

Another type of test condition specifies non−ECL output

rise and fall times between fixed output voltage levels. For

example, the rise and fall times for the MC100EPT21

LVPECL to LVTTL translator are specified between fixed

output voltages of 0.8 V and 2.0 V as shown in Figure 22.

Figure 22. LVTTL Output Rise and Fall

Time Levels

tRtF

HIGH

LOW

VO = 2.0 V

VO = 0.8 V

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Propagation Delay

Rising Edge Propagation – The rising edge (LOW−

to−HIGH transition) propagation delay (tPLH or tP++) is the

time needed to propagate an input rising edge to the output.

Falling Edge Propagation – The falling edge (HIGH−

to−LOW transition) propagation delay (tPHL or tP− −) is the

time needed to propagate an input falling edge to the output.

Single−Ended ECL Devices– Single−ended propagation

delay is measured between the 50% point of the input rising

or falling edge, and the 50% point of the identical output

edge. There are many types of single−ended propagation

delays such as a clock input to data output (CLK to Q)

propagation delay. Single−ended output propagation delay

is shown in Figure 23.

tPLH

50%

OUT

50%

Figure 23. Single−Ended Propagation Delay

tPHL

Differential ECL Devices – Differential propagation

delay is measured between the crosspoint of the input rising

or falling edge, and the crosspoint of the identical output

edge. There are many types of differential input/output pairs

such as inverted clock inputs to inverted data outputs (CLK

to Q). Differential output propagation delay is shown in

Figure 24.

Xpt Xpt

Figure 24. Differential Propagation Delay

tPLH

OUT

tPHL

OUT

Xpt Xpt

ECL Inputs and Non−ECL Outputs – Refer to the

device data sheet as several methods are used to measure the

output propagation delays. One method specifies the output

propagation delays from an ECL input crosspoint to a

non−ECL fixed output voltage. For example, the output

propagation delays for the MC100ELT21 PECL to TTL

translator are specified between the ECL input crosspoint

and a TTL output fixed voltage equal to 1.5 V as shown in

Figure 25.

Figure 25. TTL Output Propagation Delay

tPLH

OUT

1.5 V 1.5 V

tPHL

Xpt Xpt

Non−ECL Input and ECL Outputs – Refer to the device

data sheet as several methods are used to measure the output

propagation delays. One method specifies the output

propagation delays from a non−ECL input fixed voltage to

an ECL output 50% point. For example, the output

propagation delays for the MC10H352 CMOS to PECL

translator are specified between a CMOS input fixed voltage

equal to VCC/2 and the ECL output 50% point as shown in

Figure 26.

Figure 26. CMOS Input Propagation Delay

tPLH

VCC/2

OUT

50% 50%

tPHL

VCC/2

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Skew (Duty Cycle)

Duty cycle skew is also referred to as pulse skew. Duty

cycle skew is mathematically calculated by taking the

difference between the rising and falling edge propagation

delays. Unequal tPLH and tPHL values cause pulse width

distortion which affects the duty cycle. Duty cycle skew is

defined by the following equation and Figures 27 and 28 fo r

an input and its associated output.

tSKEW(Duty Cycle) |t

PLH−tPHL |

Figure 27. Single−Ended Duty Cycle Skew

tPLH

50% 50%

tPHL

50% 50%

IN2

tPLH

IN2

Xpt

OUT2

Xpt

tPHL

OUT2

Xpt Xpt

Figure 28. Differential Duty Cycle Skew

Skew (Within Device)

Within device skew is the difference between the identical

transition propagation delays of a single multiple output

device with a common input. It is mathematically calculated

by obtaining the rising and falling output propagation delays

for each individual output of the device. The minimum

output propagation delay from the set of delays is then

subtracted from the maximum output propagation delay

from the set of delays as shown in the following equations.

The higher of the two equation results is taken as the within

device skew specification.

tSKEW (Within Device Rising Edge)

tPLH(max from set) tPLH(min from set)

tSKEW (Within Device Falling Edge)

tPHL(max from set) tPHL(min from set)

The example shown in Figure 29 defines the within

device skew parameters for a device with two inputs (D1,

D2) and their two associated outputs (Q1, Q2). The within

device skew for this example would be the higher of the

following two equation results:

tSKEW(Within Device) tPLH2 tPLH1

tSKEW(Within Device) tPHL2 tPHL1

Figure 29. Within Device Skew

tPLH1

D1 = D2

50% 50%

tPHL1

50% 50%

tPLH2

50%

tPHL2

50%

Skew (Device to Device)

Device to device skew is the difference between the

identical transition propagation delays of two devices with

a common input signal under identical operating conditions

(identical ambient temperature, VCC, VEE, etc). It is

mathematically calculated from data sheet propagation

delay values as shown below.

tSKEW (Device to Device) tPLH(max) tPLH(min)

tPHL(max) tPHL(min)

Minimum Input Pulse Width

The minimum input pulse width (tPW) is the shortest pulse

width that will guarantee proper device operation. It is

measured b y decreasing the test signal generator pulse width

(i.e., DUT input pulse width) until the DUT outputs no

longer function properly. For single−ended inputs, it is

measured between the 50% points of the rise and fall

transitions as shown in Figure 30.

Figure 30. Single−Ended Input Pulse Width

tPW

VIH

VIL

50%

tPW

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For differential inputs, it is measured between the

crosspoints of the rise and fall transitions as shown in

Figure 31.

Figure 31. Differential Input Pulse Width

tPW

VIH

VIL

Xpt Xpt

Setup and Hold Time

Applicability – Only synchronous clocked devices have

setup (tS or tSETUP) and hold (tH or tHOLD) times.

Timing Window – The minimum setup requirement and

the minimum hold requirement specify the timing window

where the input must not change in order to successfully

clock the input. The setup time specifies the left edge of the

timing window, and the hold time specifies the right edge of

the window. Both timing requirements must be met in order

to successfully clock the input.

Measur ement Points – Differential crosspoints (refer to

the “Differential Characteristics” section) and single−end

50% points (refer to the “Single−Ended Characteristics”

section) are used as time measurement points. Note from the

following figures that the 50% point of the active clock edge

is the time origin of all setup and hold time measurements.

Minimum Setup Time – The following is true of

minimum setup times.

•Minimum setup times are usually positive, and they

specify the minimum length of time that the input must

remain unchanged before the active clock edge in order

to successfully clock the input. Positive setup times

therefore indicate that the left edge of the timing window

is before the active clock edge.

•Negative minimum setup times specify the minimum

length of time that the input must remain unchanged

after the active clock edge in order to successfully clock

the input. Negative setup times therefore indicate that

the left edge of the timing window is after the active

clock edge.

Minimum Hold Time – The following is true of

minimum setup times.

•Minimum hold times are usually positive, and they

specify the minimum length of time that the input must

remain unchanged after the active clock edge in order

to successfully clock the input. Positive hold times

therefore indicate that the right edge of the timing

window is after the active clock edge.

•Negative hold times specify the minimum length of

time that the input must remain unchanged before the

active clock edge in order to successfully clock the

input. Negative hold times therefore indicate that the

right edge of the timing window is before the active

clock edge.

Typical Setup and Hold Times – The typical setup and

hold times specified on data sheets are not guaranteed, and

they are only included for failure analysis calculations. They

are measured by independently moving the left and right

edges o f the timing window about the active clock edge until

the outputs no longer function properly.

Positive Setup and Positive Hold Example – The

MC100EP29 data sheet specifies the following:

•The minimum setup time of positive 100 ps indicates

that the left edge of the timing window is 100 ps before

the active rising clock edge.

•The minimum hold time of positive 100 ps specifies

that the right edge of the timing window is 100 ps after

the active rising clock edge.

The setup time requirement and the hold time requirement

were both met in the example shown in Figure 32, therefore

the LOW−to−HIGH output transition occurs after the CLK

rising edge propagation delay of 420 ps. Note that the input

cannot change within the timing window of 200 ps. Only

one side of the differential clocks, inputs, and outputs are

shown in Figure 32.

Figure 32. Positive Setup and Positive Hold Example

t(ps)

CLK

50%

50% 50%

INPUT

OUTPUT tPHL

420 ps

+100

ts(min) +100

th(min)

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Negative Setup and Positive Hold Example – The

MC100E445 4−Bit Serial/Parallel Converter data sheet

specifies the following:

•The minimum setup time of negative 200 ps indicates

that the left edge of the timing window is 200 ps after

the active rising clock edge.

•The minimum hold time of positive 300 ps specifies

that the right edge of the timing window is 300 ps after

the active rising clock edge.

The setup time requirement and the hold time requirement

were both met in the example shown in Figure 33, therefore

the LOW−to−HIGH output transition occurs after the CLK

rising edge propagation delay of 1800 ps. Note that the input

cannot change within the timing window of 100 ps. Only

one of the differential clocks and dif ferential inputs is shown

in Figure 33.

Positive Setup and Negative Hold Example – The

MC100E136 6−Bit Universal Up/Down Counter data sheet

specifies the following:

•The minimum setup time of positive 400 ps indicates

that the left edge of the timing window is 400 ps before

the active rising clock edge.

•The minimum hold time of negative 250 ps specifies

that the right edge of the timing window is 250 ps

before the active rising clock edge.

The setup time requirement and the hold time requirement

were both met in the example shown in Figure 34, therefore

the LOW−to−HIGH output transition occurs after the CLK

rising edge propagation delay of 1150 ps. Note that the input

cannot change within the timing window of 150 ps.

Figure 33. Negative Setup and Positive Hold Example

t(ps)

CLK

50%

50% 50%

INPUT

OUTPUT tPLH

1800 ps

−200

ts(min) +300

th(min)

50%

Figure 34. Positive Setup and Negative Hold Example

t(ps)

CLK

50%

50% 50%

INPUT

OUTPUT tPLH

1150 ps

+400

ts(min) −250

th(min)

50%

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Negative Setup and Negative Hold Comment – The left

edge of the timing window is the setup edge, and the right

edge of the window is the hold edge. A negative setup time

with a negative hold time cannot occur as this principle

would be violated (i.e., the hold edge would occur before the

set edge).

Set and Reset Recovery Time

Applicability – Only devices with a Set input have set

recovery times (tSR), and only devices with a Reset input

have reset recovery times (tRR).

Measur ement Points – Differential crosspoints (refer to

the “Differential Characteristics” section) and single−end

50% points (refer to the “Single−Ended Characteristics”

section) are used as time measurement points. Note from the

following figures that the 50% point of the active clock edge

is the time origin of all set and reset recovery time

measurements.

Minimum Set Recovery Time – This parameter defines

the minimum length of time that Set has to be inactive before

an active clock edge in order for the output to enter the

non−Set state. In the non−Set state, the output is no longer

dependent upon the Set state.

In the MC100EP29 example shown in Figure 35, the

minimum set recovery time of 150 ps specifies that the

system must be designed so that Set transitions from the

active HIGH state to the inactive LOW state at least 150 ps

before the active rising clock edge. The set recovery timing

requirement (150 ps) and the input setup time requirement

(100 ps) were both met in the example shown in Figure 35,

therefore the output transitions from the Set state (HIGH) to

the input state (LOW). The transition takes place after the

specified 420 ps HIGH−to−LOW CLK propagation delay.

Minimum Reset Recovery Time – This parameter

defines the minimum length of time that Reset has to be

inactive before an active clock edge in order for the output

to enter the non−Reset state. In the non−Reset state, the

output is no longer dependent upon the Reset state.

In the MC100EP29 example shown in Figure 36, the

minimum reset recovery time of 150 ps specifies that the

system must be designed so that Reset transitions from the

active HIGH state to the inactive LOW state at least 150 ps

before the active rising clock edge. The reset recovery

timing requirement (150 ps) and the input setup time

requirement (100 ps) were both met in the example shown

in Figure 36, therefore the output transitions from the Set

state (HIGH) to the input state (LOW). The transition takes

place after the specified 420 ps HIGH−to−LOW CLK

propagation delay.

Figure 35. Set Recovery Time Example

tSR(ps)

CLK

50%

INPUT

OUTPUT

150

tSR(min)

tPHL

420 ps

SET

100

ts(min)

ts(ps)

50%

Figure 36. Reset Recovery Time Example

tRR(ps)

CLK

50%

INPUT

OUTPUT

150

tRR(min)

tPLH

420 ps

RESET

100

ts(min)

50%

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Typical Set and Reset Recovery Times – The typical set

and reset recovery times specified on data sheets are not

guaranteed, and they are only included for failure analysis

calculations. They are measured by moving the

active−to−inactive Set and Reset transitions towards the

active clock edge until the outputs no longer enter the

respective non−Set or non−Reset state.

JITTER

Jitter Definition

Jitter is defined as the deviation of an actual edge location

from its ideal location. The possibility of a data transmission

error increases as jitter increases. Total jitter consists of

“Random Jitter” and “Deterministic Jitter” as described in

the following sections.

Random Clock Jitter

Random jitter (RJ, also referred to as “non−systematic”

jitter) is characterized by an unbounded Gaussian

probability density function as shown in Figure 37. Random

jitter is specified on data sheets as Cycle−to−Cycle Jitter, and

is specified as an RMS value (the one sigma value). The

function is described below, followed by a description of the

Cycle−to−Cycle Jitter specification.

The center of the symmetrical probability distribution is

the mean and represents an ideal edge location. The area

under the distribution represents the probability that an

actual edge location will lie within the range surrounding the

ideal edge location. For instance, note from Figure 37 that

a distribution range of plus/minus one sigma from the mean

includes 68.27% of the total distribution area. This means

that there is a 68.27% probability that the actual edge

location will be within the plus/minus one sigma window.

RJ Confidence Levels

As sigma increases, the confidence that the actual edge

location will lie within the distribution range surrounding

the ideal edge location increases. This is why the sigma level

is commonly referred to as the “Confidence Level.”

Confidence levels per sigma are specified in Table 2 where

“Sigma” represents the distribution range for one side of the

mean, and “Total Sigma” represents the distribution range

for both sides of the mean.

Table 2. Confidence Level per Sigma

Sigma Total Sigma Confidence Level

plus/minus 1 2 68.27%

plus/minus 2 4 95.45%

plus/minus 3 6 99.73%

plus/minus 4 8 99.99%

Figure 37. Gaussian Random Clock Jitter Distribution

  1 = 68.27%

  2 = 95.45%

  3 = 99.73%

0.4

0.3

0.2

0.1

−3 −2 −1 +1 +2 +3

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As an example, the NBSG14 data sheet specifies the

typical Cycle−to−Cycle Jitter as 0.5 ps RMS which is the one

sigma value.

Total RJ Test Setup

The test setup shown in Figure 38 is used to sample edge

locations over a large number of periods, and then measure

the total RMS random jitter.

Total Jitter (RJ) [Pattern Generator (RJ)]2[DUT (RJ)]2[Oscilloscope (RJ)]2



Figure 38. Total Random Jitter Test

50% Duty

Trigger

Pattern Generator

Oscilloscope

RJ (RMS)

50% Duty

DUT

Cycle Pulse Cycle Pulse

Test Equipment RJ Test Setup

The test setup shown in Figure 39 is used to measure the test equipment RMS random jitter.

Test Equipment Jitter (RJ) [Pattern Generator (RJ)]2[Oscilloscope (RJ)]2



Figure 39. Test Equipment Random Jitter Test

50% Duty Cycle Pulse

Trigger

Pattern Generator Oscilloscope

RJ (RMS)

DUT RJ Calculation

The DUT RMS random clock jitter determined with the following equation is specified as Cycle−to−Cycle Jitter.

DUT (RJ) [Total Jitter (RJ)]2[Test Equipment Jitter (RJ)]

2

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Deterministic Jitter

Deterministic jitter (DJ, also referred to as “data” or

“systematic” jitter) is characterized by bounded

non–Gaussian probability density functions. Deterministic

jitter includes Duty Cycle Distortion (DCD) which is

specified as Duty Cycle Skew or Pulse Skew on data sheets

(refer to the “Duty Cycle Skew” section). Determistic jitter

is defined for a specific test pattern, and is specified as a

peak−to−peak value.

Total DJ Test Setup

The total DJ test setup shown in Figure 40 is used to

produce an eye diagram. An eye diagram is useful as it

provides a qualitative view of peak−to−peak deterministic

jitter . To form an eye diagram, a PRBS (Pseudo−Random Bit

Sequence) signal is sent to the DUT input, and the DUT

output (the eye diagram) is observed on the oscilloscope.

The NBSG14 eye diagram in Figure 41 was created by an

Advantest D3186 generating a 231−1 PRBS data pattern at

10.8 Gbps. The Tektronix TDS8000 oscilloscope with an

80E01 50 GHz sampling module acquired 7000 samples.

The total deterministic jitter represented by the histogram at

the top left of the eye diagram is 18.00 ps peak−to−peak. As

deterministic jitter increases, the eye closes (i.e., the eye

width decreases) which increases the probability of a data

transmission error.

Figure 40. Total Deterministic Jitter Test

Oscilloscope (DJ)

Total Jitter(DJ) Pattern Generator (DJ) DUT (DJ)

PRBS

Trigger

Pattern Generator

Oscilloscope

DJ (PP)

PRBS

DUT

Figure 41. Total Deterministic Jitter Eye Diagram

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Test Equipment DJ Test Setup

The general test setup shown in Figure 42 is used to

measure the test equipment peak−to−peak deterministic

jitter.

The NBSG14 test equipment deterministic jitter eye

diagram in Figure 43 was created by the identical pattern

generator and oscilloscope setup that was used to generate

the total deterministic jitter eye diagram. The test equipment

deterministic jitter represented by the histogram at the upper

right of the eye diagram is 10.88 ps pp.

Test Equipment Jitter (DJ) Pattern Generator (DJ)Oscilloscope (DJ)

Figure 42. Test Equipment Deterministic Jitter Test

PRBS

Trigger

Pattern Generator

Oscilloscope

DJ (PP)

Figure 43. Test Equipment Deterministic Jitter Eye Diagram

DUT DJ Calculation

The DUT peak−to−peak deterministic jitter is determined

with the following equation.

DUT (DJ) Total Jitter (DJ) Test Equipment Jitter (DJ)

The DUT peak−to−peak deterministic jitter for the above

NBSG14 example is calculated below.

DUT (DJ) 18.00 ps 10.88 ps 7.12 ps pp

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Table 3. Symbols and Acronyms

A Amperes

BER Bit Error Rate

DUT Device Under Test

ECL Emitter Coupled Logic

ECLinPS Emitter Coupled Logic in PicoSeconds

fMAX Maximum Toggle Frequency

fSHIFT Maximum Shift Frequency

Gbps Gigabits (109 bits) per second

GHz Gigahertz (109 Hz)

JitterPP Peak−to−Peak Jitter

JitterRMS RMS Jitter

lfpm Linear Feet Per Minute

LVECLinPS Low Voltage Emitter Coupled Logic in PicoSeconds

MHz Megahertz (106 Hz)

NBSG GigaComm Product Prefix

ns Nanoseconds (10−9 sec)

pp Peak−to−Peak

PRBS Pseudo−Random Binary Sequence

ps Picoseconds (10−12 sec)

RF Radio Frequency

SOIC Small Outline Integrated Circuit

tfFall Time

thHold Time

tJITTER Jitter

tPHL Falling Edge Propagation Delay

tPLH Rising Edge Propagation Delay

tPWmin Minimum Input Pulse Width

trRise Time

tRR Set and Reset Recovery

tSSetup Time

tSK++ Input Rising Edge to Output Rising Edge Skew

tSK− − Input Falling Edge to Output Falling Edge Skew

tSKEW Skew

VBB Switching Reference Voltage

VCC The Most Positive Supply Voltage

VCMR Common Mode Range

VEE The Most Negative Supply Voltage

VIH Input High Voltage Level

VIL Input Low Voltage Level

VIN Input Voltage

VOH Output High Voltage Level

VOL Output Low Voltage Level

VOUT Output Voltage

VOUTpp Output Peak−to−Peak Voltage Swing

VPPmin (Or VINPPmin) Minimum Input Peak−to−Peak Voltage Swing

VPPmax (Or VINPPmax) Maximum Input Peak−to−Peak Voltage Swing

VTT Termination V oltage Typically Equal to VCC – 2.0 V

Xpt Crosspoint of the True and Inverted Waveforms

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REFERENCES

Johnson, Howard and Graham, Martin. High−Speed Digital Design: A Handbook of Black Magic. PTR Prentice−Hall.

New Jersey, 1993.

INCITS. Methodologies for Jitter Specification. T11.2 Project 1230. http://www.t11.org.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

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