5962-8876101EA - TEXAS INSTRUMENTS

THIS SPEC IS OBSOLETE

Spec No

002

01235

Spec Title

S29AL004D, 4

MBIT (512K X 8

BIT/256K X 16

BIT), 3 V BOOT SECTOR FLASH

Replaced by

NONE

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 002-01235 Rev. *B Revised January 25, 2017

S29AL004D

4-Mbit (512K x 8-Bit/256K x 16-Bit), 3 V

Boot Sector Flash

This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supe rcedes

S29AL004D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and

ordering information.

Distinctive Characteristics

Architectural Advantages

Single Power Supply Operation

– 2.7 to 3.6 volt read and write operations for battery-powered

applications

Manufactured on 200 nm Process Technology

– Compatible with 0.32 µm Am29LV400B and MBM29LV400T/BC

Flexible Sector Architecture

– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte

sectors (byte mode)

– One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword

sectors (word mode)

– Supports full chip erase

Unlock Bypass Program Command

– Reduces overall programming time when issuing multiple program

command sequences

Top or Bottom Boot Block Configurations Available

Embedded Algorithms

– Embedded Erase algorithm automatically preprograms and

erases the entire chip or any combination of designated sectors

– Embedded Program algorithm automatically writes and verifies

data at specified addresses

Compatibility with JEDEC Standards

– Pinout and software compatible with single-power supply Flash

– Superior inadvertent write protection

Sector Protection Features

– A hardware method of locking a sector to prevent any program or

erase operations within that sect or

– Sectors can be locked in-system or via programming equipment

– Temporary Sector Unprotect feature allows code changes in

previously locked sectors

Performance Chara cte ri st ic s

High Performance

– Access times as fast as 55 ns

– Extended temperature range (-40°C to +125°C)

Ultra-low Power Consumption (typical values at 5 MHz)

– 200 nA Automatic Sleep mode current

– 200 nA standby mode current

– 9 mA read current

– 20 mA program/erase current

Cycling Endurance: 1,000,000 cycles per sector typical

Data Retention: 20 years typical

Package Options

48-ball FBGA

48-pin TSOP

44-pin SO

Software Features

Data# Polling and Toggle Bits

– Provides a software method of detecting program or erase

operation completion

Erase Suspend/Erase Resume

– Suspends an erase operation to read data from, or program data

to, a sector that is not being erased, then resumes the erase

operation

Hardware Features

Ready/Busy# Pin (RY/BY#)

– Provides a hardware method of detecting program or erase cycle

completion

Hardware Reset Pin (RESET#)

– Hardware method to reset the device to reading array data

Document Number: 002-01235 Rev. *B Page 2 of 46

S29AL004D

General Description

The S29AL004D is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-

ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wi de data (x16) appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. Th is device requires only a single, 3.0 volt VCC supply to perform read, program, and erase operations. A

standard EPROM programmer can al so be used to program and erase th e device.

This device is manufactured using Spansion’s 200 nm process technology, and offers all the features and benefits of the

Am29LV400B and MBM29LV400T/BC, which were manufactured using 320 nm process technology.

The standard device offers access times of 70 and 90 ns, allowing high spe ed microprocessors to operate without wait states. To

eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power su pply for both read and write functions. Internally generated and regulated

voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to

the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine

that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming

and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an

internal algorithm that automati cally times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode

facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. Th is initiates the Embedded Erase algorithm—an internal

algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During

erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7

(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle is completed, the device is ready to read array data or

accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other

sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power

transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors

of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any

sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progres s and resets the internal state machine to reading array data. The

RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system

microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the

automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in

both these modes.

Spansion’s Flash technology combines years of Flash memory manufacturing experi ence to produce the highest levels of quality,

reliab ility a nd cos t ef fectiven e ss . Th e de v ic e el e ct r i ca l ly e ra s e s a l l b it s w i th i n a s e ct o r simultaneously via Fowler-Nordheim

tunneling. The data is programmed using hot electro n inje ction.

Document Number: 002-01235 Rev. *B Page 3 of 46

S29AL004D

Contents

1. Product Selector Guid e............................................... 4

2. Block Diagram.............................................................. 4

3. Connection Diagrams.................................................. 5

3.1 Special Handling Instructions for FBGA Package.......... 6

4. Pin Configu rati on......................................................... 6

5. Logic Symbol ............................................................... 7

6. Ordering Information (Standard Products)................ 7

7. Device Bus Operations................................................ 9

8.1 Word/Byte Configuration...................... ... ....................... 9

8.2 Requirements for Reading Array Data........................... 9

8.3 Writing Commands/Command Sequences.................. 10

8.4 Program and Erase Operation Status.......................... 10

8.5 Standby Mode.............................................................. 10

8.6 Automatic Sleep Mode................................................. 10

8.7 RESET#: Hardware Reset Pin..................................... 11

8.8 Output Disable Mode................................................... 11

10.1 Autoselect Mode.......................................................... 12

11.1 Sector Protection/Unprotection.................................... 12

11.2 Temporary Sector Unprotect........................................ 13

11.3 Hardware Data Protection....................... ... .................. 15

12. Command Definitions................................................ 15

12.1 Reading Array Data ..................................................... 15

12.2 Reset Command.......................... ... .............. .. ............. 15

12.3 Autoselect Command Sequence ................................. 16

12.4 Word/Byte Program Command Sequence................... 16

12.5 Chip Erase Command Sequence ................................ 17

12.6 Sector Erase Command Sequence ............................. 18

12.7 Erase Suspend/Erase Resume Commands................ 18

14. Write Operation Status.............................................. 20

14.1 DQ7: Data# Polling...................................................... 20

14.2 RY/BY#: Ready/Busy#................................................. 21

14.3 DQ6: Toggle Bit I ......................................................... 22

14.4 DQ2: Toggle Bit II ........................................................ 22

14.5 Reading Toggle Bits DQ6/DQ2.................................... 22

14.6 DQ5: Exceeded Timing Limits ..................................... 23

14.7 DQ3: Sector Erase Timer............................................. 23

16. Absolute Maximum Ratings...................................... 24

17. Operating Ranges...................................................... 25

18. DC Cha racterist ic s..................................................... 25

18.1 Zero Power Flash......................................................... 26

19. Test Conditions.......................................................... 27

21. Key to Switching Waveforms.................................... 28

22. AC Cha racterist ic s..................................................... 29

22.1 Read Operations.......................................................... 29

25.1 Erase/Program Operations.......................................... 32

28. Erase And Programming Performance.................... 37

30. Physical Dimensions................................................. 39

30.1 TS 048—48-Pin Standard TSOP................................. 39

30.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15

x 6.15 mm .....................................................................40

30.3 SO 044—44-Pin Small Outline Package ...................... 41

31. Revision Summary...................................................... 42

31.1 Revision A0 (November 12, 2004)................................ 42

31.2 Revision A1 (February 18, 2005)...................... ... .. ... ... . 42

31.3 Revision A2 (June 1, 2005).............. ... ................. ......... 42

31.4 Revision A3 (June 21, 2005)............ ... ................. ......... 43

31.5 Revision A4 (May 22, 2006).......................................... 43

31.6 Revision A5 (June 22, 2006)............ ... ................. ......... 43

31.7 Revision A6 (February 27, 2009)...................... ... .. ... ... . 43

Document Number: 002-01235 Rev. *B Page 4 of 46

S29AL004D

1. Product Selector Guide

Note

See AC Characteristics on page 29 for full specifications.

2. Block Diagram

Family Part Number S29AL004D

Speed Options Full Voltage Range: VCC = 2.7–3.6 V 55 70 90

Max access time, ns (tACC) 557090

Max CE# access time, ns (tCE) 557090

Max OE# access time, ns (tOE) 253035

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

BYTE#

CE#

OE#

STB

DQ0–DQ15 (A-1)

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A17

Document Number: 002-01235 Rev. *B Page 5 of 46

S29AL004D

3. Connection Diagrams

A15

A14

A13

A12

A11

A10

WE#

ESET#

RY/BY#

A17

A16

DQ2

BYTE#

DQ15/A

-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

CE#

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

Standard TSOP

RY/BY#

A17

CE#

VSS

OE#

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

RESET#

WE#

A10

A11

A12

A13

A14

A15

A16

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

Document Number: 002-01235 Rev. *B Page 6 of 46

S29AL004D

3.1 Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is

exposed to temperatures above 150C for prolonged periods of time.

4. Pin Configuration

A0–A17 18 addresses

DQ0–DQ14 15 data inputs/outputs

DQ15/A-1 DQ15 (dat a input/output, word mode), A-1 (LSB address input, byte mode)

BYTE# Selects 8-bit or 16-bit mode

CE# Chip enable

OE# Output enable

WE# Write enable

RESET# Hardware reset pin, active low

RY/BY# Ready/Busy# output

VCC 3.0 volt-only single power supply

(see Product Selector Guide on page 4 for speed options and voltage supply tolerances)

VSS Device ground

NC Pin not connected inter nally

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1 V

BYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

DQ4DQ12DQ5NCNCRESET#WE#

DQ11 DQ3DQ10DQ2NCNCNCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# V

CE#A0A1A2A4A3

FBGA

Top View, Balls Facing Down

Document Number: 002-01235 Rev. *B Page 7 of 46

S29AL004D

5. Logic Symbol

6. Ordering Information (Standard Products)

This product has been retired and is not recommended for designs. For new and curre nt design s, S29AL008J supercedes

S29AL004D. This is the factory-recommended migration path. Please refer to the S29AL 008J data sheet for specifications and

ordering information.

Spansion standard products are available in several packages and operating ranges. The order number (Va lid Combination) is

formed by a combination of the elements below.

S29AL004D 55 T A I 01 0

Packing Type

0=Tray

1 = Tube

2 = 7” Tape and Reel

3 = 13” Tape and Reel

Model Number

01 = VCC = 2.7 - 3.6V, top boot sector device

R1 = VCC = 3.0 - 3.6V, top boot sector device

02 = VCC = 2.7 - 3.6V, bottom boot sector device

R2 = VCC = 3.0 - 3.6V, bottom boot sector device

Temperature Range

I = Industrial (-40°C to +85°C)

N = Extended (-40°C to +125°C)

Package Material Set

A = Standard

F = Pb-Free

Package Type

T = Thin Small Outline Package (TSOP) Standard Pinout

B = Fine-pitch Ball-Grid Array Package

M = Small Outline Package (SOP) Standard Pinout

Speed Option

55 = 55 ns Access Speed

70 = 70 ns Access Speed

90 = 90 ns Access Speed

Device Number/Description

S29AL004D

4 Megabit Flash Memory manufactured using 200 nm process technology

3.0 Volt-only Read, Program, and Erase

16 or 8

DQ0–DQ15

(A-1)

A0–A17

CE#

OE#

WE#

RESET#

BYTE# RY/BY#

Document Number: 002-01235 Rev. *B Page 8 of 46

S29AL004D

Notes

1. Type 0 is standard. Specify other options as required.

2. Type 1 is standard. Specify other options as required.

3. TSOP and SOP package markings omit packing type designator from ordering part number.

4. BGA package marking omits leading S29 and packing type designator from ordering part number.

Valid Combinations

Valid Combinations list configuration s pl anned to be supported in volume for this device. Consult your local sales office to confirm

availability of specific valid combinations and to check on newly released combinations.

S29AL004D Valid Combinations

Package Description

Device Number Speed

Option

Package Type,

Material, and

Temperature Range

Model

Number Packing Type

S29AL004D

55 TAI, TFI 01, 02

0, 3 (Note 1) TS048 (Note 3) TSOPTAN, TFN R1, R2

70, 90 TAI, TFI, TAN, TFN 01, 02

55 BAI, BFI 01, 02

0, 2, 3 (Note 1) VBK048 (Note 4) Fine-Pitch

BGA

BAN, BFN R1, R2

70, 90 BAI, BFI, BAN, BFN 01, 02

55 MAI, MFI 01, 02

0, 1, 3 (Note 2) SO044 (Note 3) SOPMAN, MFN R1, R2

70, 90 MAI, MFI, MAN, MFN 01, 02

Document Number: 002-01235 Rev. *B Page 9 of 46

S29AL004D

7. Device Bus Operations

This section describes the re quirements and use of the device bus operations, which are initiated through the internal command

register. The command register itself doe s not occupy any addressable memory location. Th e register is composed of latches that

store the commands, along with the address and data information needed to execute the command. The contents of the register

serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 8 lists the device

bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these

operations in further detail.

Legend

L = Logic Low = VIL

H = Logic High = VIH

VID = 12.0 0.5 V

X = Don’t Care

AIN = Address In

DIN = Data In

DOUT = Data Out

Notes

1. Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection/Unpro tection on page 12.

8.1 Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is

set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and control led by

CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

8.2 Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power contro l and selects the

device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pi n determines

whether the device outputs array da ta in words or bytes.

The internal state machine is set for reading array data upon device power-up, or afte r a hardware reset. This ensures that no

spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the

device data outputs. The device remains enabled fo r read access until the command regi ster contents are altered.

Table 8. S29AL004D Device Bus Operations

Operation CE# OE# WE# RESET# Addresses

(Note 1) DQ0–

DQ7

DQ8–DQ15

BYTE#

= VIH BYTE# = VIL

Read L L H H AIN DOUT DOUT DQ8–DQ14 = High-Z,

DQ15 = A-1

Write L H L H AIN DIN DIN

Standby VCC  0.3V X X VCC  0.3V X High-Z High-Z High-Z

Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) LHLV

Sector Address,

A6 = L, A1 = H,

A0 = L DIN XX

Sector Unprotect (Note 2) LHLV

Sector Address,

A6 = H, A1 = H,

A0 = L DIN XX

Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z

Document Number: 002-01235 Rev. *B Page 10 of 46

S29AL004D

See Reading Array Data on page 15 for more information. Refer to the AC Read Operations on page 29 for timing specifications and

to Figure 23.1 on page 29 for the ti ming diagram. ICC1 in DC Characteristics on page 25 represents the active current specification

for reading array data.

8.3 Writing Commands/Command Sequences

To write a command or comma nd sequence (which includes programming data to the device and erasing sectors of memory), the

system must drive WE# and CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte

Configuration on page 9 for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode ,

only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Command Sequence

on page 16 has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 9 on page 11 and Table 10 on page 11

indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a

sector. The Command Definitions on page 15 has details on erasing a sector or the entire chip, or suspending/resuming the erase

operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read

autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standa rd read cycle timings

apply in this mode. Refer to Autoselect Mode on page 12 and Autoselect Command Sequence on page 16 for more information.

ICC2 in DC Characteristics on page 25 represents the active current specification for the write mode. The AC Characteristics

on page 29 contains timing specification tables and timing diagrams for write operations.

8.4 Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by re ading the status bits on DQ7–DQ0.

Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 20 for more information, and

to AC Characteristics on page 29 for timing diagrams.

8.5 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current

consumption is greatly reduced, and the outputs are placed in the high imped ance state, independent of th e OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC  0.3 V. (Note that this is a more

restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC  0.3 V, the device is in the standby mode,

but the standby current is greater. The device requires sta ndard access time (tCE) for read access when the device is in either of

these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operati on is completed.

In the DC Characteristics on page 25 table, ICC3 and ICC4 represents the standby current specification.

8.6 Automatic Sleep Mode

The automatic sleep mode minimize s Flash device energy consumption . The device automati cally enables this mode when

addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.

Standard address access timings provide ne w data when ad dresses are changed. While in sleep m ode, output data is latched and

always available to the system. ICC4 in DC Characteristics on page 25 represents the automatic sl eep mode current specification.

Document Number: 002-01235 Rev. *B Page 11 of 46

S29AL004D

8.7 RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for

at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/

write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The

operation that was interrupted shoul d be reinitiated once the device is ready to accept another command sequ ence, to ensure data

integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby

current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus als o res et the Flash memory, enabling the

system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is

complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine

whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is

1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after

the RESET# pin returns to VIH.

Refer to the tables in AC Characteristics on page 29 for RESET# parameters an d to Figure 24.1 on page 30 for the timing diagram.

8.8 Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Note

The address range is A17:A-1 in byte mode and A1 7:A0 in word mode. See Word/ Byte Configuration on page 9.

Table 9. S29AL004D Top Boot Block Sector Addresses

Sector A17 A16 A15 A14 A13 A12 Sector Size

(Kbytes/Kwords) Address Range (in hexadecimal)

(x8) Address Range (x16) Address Range

SA0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh

SA1 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh

SA2 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

SA3 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

SA4 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh

SA5 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh

SA6 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh

SA71110XX 32/16 70000h–7FFFFh 38000h–38FFFh

SA8111100 8/4 78000h–79FFFh 3C000h–3CFFFh

SA9111101 8/4 7A000h–7BFFFh 3D000h–3DFFFh

SA1011111X 16/8 7C000h–7FFFFh 3E000h–3FFFFh

Table 10. S29AL004D Bottom Boot Block Sector Addresses

Sector A17 A16 A15 A14 A13 A12 Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range (x16)

Address Range

SA0 0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh

SA1 0 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh

SA2 0 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh

SA3 0 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh

SA4 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh

SA5 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

SA6 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

SA7 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh

Document Number: 002-01235 Rev. *B Page 12 of 46

S29AL004D

Note

The address range is A17:A-1 in byte mode and A1 7:A0 in word mode. See Word/ Byte Configuration on page 9.

10.1 Autoselect Mode

The autoselect mode provid es manufacturer and device identifica tion, and sector protection verifi cation, through identifier codes

output on DQ7–DQ0. This mode is primarily intende d for programming equipment to automatically match a device to be

programmed with its corresponding programming algorithm. However, th e autosele ct codes can also be accessed in-system

through the command register.

When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1,

and A0 must be as shown in Table 11. In addition, when verifying sector protection, the sector address must appear on the

appropriate highest order address bits (see Tab le 9 on page 11 and Table 10 on page 11). Table 11 on page 12 shows th e

remaining address bits that are don’t care. When all necessary bits are set as required, the programming equipment may then read

the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the c ommand register, as shown

in Table 12.2 on page 19. This method does not require VID. See Command Definitions on page 15 for details on using the

autoselect mode.

Legend

L = Logic Low = VIL

H = Logic High = VIH

SA = Sector Address

X = Don’t care.

11.1 Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection

feature re-enables both program and erase operations in previ ously protected sectors.

The device is shipped with all sectors unprotected. Spansion offe rs the option of programming and protecting sectors at its factory

prior to shipping the device through Spansi on’s ExpressFlash™ Service. Contact an Spansion representative for details.

It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 12 for details.

SA8 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh

SA9 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh

SA10 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh

Table 11. S29AL004D Autoselect Codes (High Voltage Method)

Description Mode CE# OE# WE# A17

A12

A11

A10 A9 A8

A7 A6 A4

A2 A1 A0 DQ8

DQ15

DQ7

DQ0

Manufacturer ID: Spansion L L H X X VID XLXLLL X 01h

Device ID:

S29AL004D

(Top Boot Block)

Word L L H XXV

ID XLXLLH

22h B9h

Byte L L H X B9h

Device ID:

S29AL004D

(Bottom Boot

Block)

Word L L H

XXV

ID XLXLLH

22h BAh

Byte L L H X BAh

Sector Protection

Verification LLHSAXV

ID XLXLHL X01h

(protected)

X00h

(unprotected)

Table 10. S29AL004D Bottom Boot Block Sector Addresses

Sector A17 A16 A15 A14 A13 A12 Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range (x16)

Address Range

Document Number: 002-01235 Rev. *B Page 13 of 46

S29AL004D

Sector Protection/unprotection can be implemented via two methods.

The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment.

Figure 11.2 on page 14 shows the algorithms and Figure 26.2 on page 36 shows the timing diag ram. This method uses standard

microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector

unprotect write cycle.

The alternate meth od intended only for programming equipment requires VID on address pin A9 and OE#. This method is

compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices.

11.2 Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is

activated by sett ing the R ESET# pi n to VID. During this mode, formerly protected sectors can be programmed or erased by selecting

the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again.

Figure 11.1 shows the algorithm and Figure 26.1 on page 35 shows the timing diagrams, for this feature.

Figure 11.1 Temporary Sector Unprotect Operation

Notes

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID (Note 1)

Document Number: 002-01235 Rev. *B Page 14 of 46

S29AL004D

Figure 11.2 In-System Sector Protect/Sector Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 μs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 μs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 μs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm

Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

Document Number: 002-01235 Rev. *B Page 15 of 46

S29AL004D

11.3 Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent

writes (refer to Table 12.2 on page 19 fo r command defini tions). In addition, the following hardware data protection measures

prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC

power-up and power-down transitions, or from system noise.

11.3.1 Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.

The command register and all internal program/er ase circuits are disabled, and the devi ce resets. Subsequent writes are ignored

until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when

VCC is greater than VLKO.

11.3.2 Write Pulse Glitch Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

11.3.3 Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be

a logical zero while OE# is a logical one.

11.3.4 Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal

state machine is automatically rese t to read i n g array data on power -up .

12. Command Definitions

Writing specific address and data commands or sequences into the command register initiates device operations. Figure 12.2

on page 19 defines the valid register command sequences. Writing incorrect ad dress and data values or writing them in the

improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE#

or CE#, whichever happens first. Refer to the appropriate timing diagrams in AC Characteristics on page 29.

12.1 Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device

is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data

using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data.

After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same

exception. See Erase Suspend/Erase Resume Commands on page 18 for more information on this mode.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect

mode. See Reset Command on page 15.

See also Requirements for Reading Array Data on page 9 for more information. The Read Operations on page 29 provides the read

parameters, and Figure 23.1 on page 29 shows the timing diagr am.

12.2 Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.

Document Number: 002-01235 Rev. *B Page 16 of 46

S29AL004D

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This

resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is

complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins.

This resets the device to reading array data (also applies to programming in Erase Suspen d mode). Once programming begins,

however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect

mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also

applies during Erase Suspend).

12.3 Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether

or not a sector is protected. Table 12.2 on page 19 shows the address and data requirements. This method is an alternative to that

shown in Table 11 on page 12, which is intended for PROM programmers and requires VID on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then

enters the autoselect mode, and the system may read at any address any number of times, without initiating another command

sequence.

A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode)

returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode)

returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 9 on page 11 and Table 10 on page 11 for valid

sector addresses.

The system must write the reset command to exit the autoselect mode and return to reading array data.

12.4 Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle

operation. The program command sequence is initiated by writing two unlock write cycles, followed by the prog ram set-up

command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is

not required to provide further controls or timings. The device automatica lly provides internally generated program pulses and

verifies the programmed cell margin. Table 12.2 on page 19 shows the address and data requirements for the byte program

command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer

latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status

on page 20 for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately

terminates the programming operation. The program command sequence should be reinitiated once the device has reset to reading

array data, to ensure data inte grity.

Programming is allowed in any sequence and across sector boun daries. A bit cannot be programmed from a 0 back to a 1.

Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algo rithm to indicate the operation was

successful. However, a succeeding read shows that the data is still 0. On ly erase operations can convert a 0 to a 1.

12.4.1 Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program

command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a thi rd

write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock

bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the

unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial tw o unlock cycles required in the standard program command sequence ,

resulting in faster total programming time. Table 12.2 on page 19 shows the requirements for the command sequen ce.

Document Number: 002-01235 Rev. *B Page 17 of 46

S29AL004D

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock

bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data

90h; the second cycle the data 00h (F0h). Addresses are don’t care for both cycles. The device then returns to reading array data.

Figure 12.1 illustrates the algorithm for the program operation. See Table 25 on page 30 for parameters, and Figure 25.3

on page 32 for timing diagrams.

Figure 12.1 Program Operation

Note

See Table 13 on page 19 for program command sequence.

12.5 Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a

set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the

Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Emb edded Erase algorithm

automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not

required to provide any controls or timings during these operations. Table 12.2 on page 19 shows the address and data

requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip

erase operation immediately terminate s the operation. The Chip Erase command sequence should be reinitiated once the device

has returned to reading array data, to ensure data integrity.

The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status

on page 20 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading

array data and addresses are no longer latched.

Figure 12.2 on page 19 illustrates the algorithm for the erase operation. See Table 25 on page 30 for parameters and Figure 25.4

on page 33 for timing diagrams.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Document Number: 002-01235 Rev. *B Page 18 of 46

S29AL004D

12.6 Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by

a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector

erase command. Table 12.2 on pa ge 19 shows the address and data requirements for the sector erase command sequence.

The device does not requ ire the system to preprogram the memory prior to erase. The Embedded Erase alg orithm automatically

programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any

controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector

addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the

number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs,

otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor

interrupts be disabled during this ti me to ensure all commands are accepted. The interrupts can be re-enab led after the last Sector

Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system

need not monitor DQ3. Any comman d o ther than Sector Erase or Erase Suspen d during the time-out period resets the

device to reading array data. The system must rewrite the command sequence and any additional sector addresses and

commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer on page 23). The

time-out begins from the rising edge of the final WE# pulse in the command sequen ce.

Once the sector erase operation has begun, only the Erase Suspend command is valid . A ll other commands are ignored. Note that

a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence

should be reinitiated once the device has returned to reading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the device returns to reading array data and ad dresses are no longer latched.

The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status

on page 20 for information on these status bits.

Figure 12.2 on page 19 illustrates the algorithm for the erase operation. Refer to Table 25 on page 30 for parameters, and to

Figure 25.4 on page 33 for timing diagrams.

12.7 Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to,

any sector not selected for erasure. This command is valid only during the sector erase op eration, including the 50 µs time-out

period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase

operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately

terminates the time-out period and suspends the erase op eration. Addresses are don’t-cares when writing the Erase Suspend

command.

When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend

the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends the erase operation.

After the erase operation is suspended, the system can read array data from or program data to any sector not selected for erasure.

(The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply.

Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and

DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 20 for

information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data within non-suspended

sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard

program operation. See Write Operation Status on page 20 for more information.

The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows

reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See

Autoselect Command Sequence on page 16 for more information.

Document Number: 002-01235 Rev. *B Page 19 of 46

S29AL004D

The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the

sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after

the device has resumed erasing.

Figure 12.2 Erase Operation

Notes

1. See Sector Erase Command Sequence on page 18 for erase command sequence.

2. See DQ3: Sector Erase Timer on page 23 for more information.

Table 13. S29AL004D Command Definitions

Command

Sequence

(Note 1)

Cycles

Bus Cycles (No t es 2-5)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 6) 1RARD

Reset (Note 7) 1XXX F0

Autoselect (Note 8)

Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01

Byte AAA 555 AAA

Device ID,

Top Boot Block Word 4555 AA 2AA 55 555 90 X01 22B9

Byte AAA 555 AAA X02 B9

Device ID,

Bottom Boot Block Word 4555 AA 2AA 55 555 90 X01 22BA

Byte AAA 555 AAA X02 BA

Sector Protect Verify

(Note 9)

Word

555

2AA

555

(SA)X02 XX00

XX01

Byte AAA 555 AAA (SA)X04 00

Program Word 4555 AA 2AA 55 555 A0 PA PD

Byte AAA 555 AAA

Unlock Bypass Word 3555 AA 2AA 55 555 20

Byte AAA 555 AAA

Unlock Bypass Program (Note 10) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00

(F0h)

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

Document Number: 002-01235 Rev. *B Page 20 of 46

S29AL004D

Legend

X = Don’t care

RA = Address of the memory location to be read

RD = Data read from location RA during read operation, and

PA = Address of the memory location to be programmed. Addresses latc h on the falling edge of the WE# or CE# pulse, whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens f i rst.

SA = Address of the sector to be verified ( i n autoselect mode) or erased. Address bits A17–A12 uniquely select any sector.

Notes

1. See Table 8 on page 9 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write ope rations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.

5. Address bits A17–A11 are don’t cares for unlock and command cycles, unless PA or SA required.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (whi le the device is

providing status data).

8. The fourth cycle of the autoselect command sequence is a read cycle.

9. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect Command Sequence on page 16 for more

information.

10.The Unlock Bypass command is required prior to t he Unlock Bypass Program command.

11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.

12.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase

Suspend command is valid only during a sector erase operat ion.

13.The Erase Resume command is valid only during the Erase Suspend mode.

14. Write Operation Status

The device provides several bits to dete rmine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 15

on page 24 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for

determining whether a prog ram or erase operation is complete or in progress. These three bits are discussed first.

14.1 DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether

the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command

sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7

status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs

the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program

address fall s wi th i n a p r otected sec to r, Da ta# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if

the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. Th is is analogous to the complement/true datum

output described for the Embedded Program alg orithm: the erase function changes all the bits in a sector to 1; prior to this, the

device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read

valid status information on DQ7.

Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Byte AAA 555 AAA AAA 555 AAA

Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Byte AAA 555 AAA AAA 555

Erase Suspend (Note 12) 1XXX B0

Erase Resume (Note 13) 1XXX 30

Table 13. S29AL004D Command Definitions

Document Number: 002-01235 Rev. *B Page 21 of 46

S29AL004D

After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Poll ing on DQ7 is active for

approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following

read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low.

Figure 25.6 on page 34 illustrates this.

Table 15 on page 24 shows the outputs for Data# Polling on DQ7. Fig ure 14.1 on page 21 shows the Data# Polling algorithm.

Figure 14.1 Data# Polling Algorithm

Notes

1. VA = Valid address for programmin g. During a sector erase operat ion, a valid address is an address within any sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.

14.2 RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The

RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,

several RY/BY# pins can be tied togethe r in parallel with a pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)

If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby

mode.

Table 15 on page 24 shows the outputs for RY/BY#. Figure 23.1 on page 29, Figure 24.1 on page 30, Figure 25.3 on page 32, and

Figure 25.4 on page 33 shows RY/BY# for read, reset, program, and erase operations, respectively.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Document Number: 002-01235 Rev. *B Page 22 of 46

S29AL004D

14.3 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Era s e algorithm is in progress or complete, or whether the device

has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE#

pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operati on, succes si ve read cycles to any address cause DQ6 to toggle. (The

system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,

then returns to reading array data. If not all selected sectors are protected, the Embedded Era s e algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the

device is actively erasing (that is, the Embedded Erase algorithm is in progre ss), DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-

suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 20).

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is

written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.

Table 15 on page 24 shows the outputs for Toggle Bit I on DQ6. Figure 14.2 on page 23 shows the toggle bit algorithm. Figure 25.7

on page 34 shows the toggle bit timing diagrams. Figure 25.8 on page 34 shows the differences between DQ2 and DQ6 in graphical

form. See also DQ2: Toggle Bit II on page 22.

14.4 DQ2: Toggle Bit II

The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, th e Embedded

Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#

pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that are selected for erasure. (The system may use either

OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended.

DQ6, by comparison, indicates whether the devic e is actively erasing, or is in Erase Suspend, but cannot disti nguish which sectors

are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Tabl e 15 on page 24 to

compare outputs for DQ2 and DQ6.

Figure 14.2 on page 23 shows the toggle bit algorithm in flowchart form, and the section DQ2: Toggle Bit II on page 22 explains the

algorithm. See also the DQ6: Toggle Bit I on page 22 subsection. Figure 25.7 on page 34 shows the toggle bit timing diagram.

Figure 25.8 on page 34 shows the differences between DQ2 and DQ6 in graphical form.

14.5 Reading Toggle Bits DQ6/DQ2

Refer to Figure 14.2 on page 23 for the following discussion. When ever the system initially begins reading toggle bit status, it must

read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typical ly , the system would note and store the

value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, th e device has completed the program or erase operation . The system can read array data on

DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note

whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 23). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the

operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system

may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous

paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the operation (top of Figure 14.2 on page 23)

Document Number: 002-01235 Rev. *B Page 23 of 46

S29AL004D

14.6 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5

produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.

The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an

erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the ope ration has

exceeded the timing limits, DQ5 produces a 1.

Under both these conditions, the system must issue the reset comma nd to return the device to reading array data.

14.7 DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has

begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire

time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The

system may ignore DQ3 i f the system can guarantee that the ti me between additional sector erase commands is always less than

50 µs. See also the Sector Erase Command Sequence on page 18.

Figure 14.2 Toggle Bit Algorithm

Notes

1. Read toggle bit twice to determine whether or not it is toggling. See t ext.

2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

(Notes 1, 2)

(Note 1)

Document Number: 002-01235 Rev. *B Page 24 of 46

S29AL004D

After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit

I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle

has begun; all further commands (other than Erase Suspend) are ignored until the erase ope ration is complete. If DQ3 is 0, the

device accepts additional sector erase commands. To ensure the command is accepted, the system software should check the

status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last

command might not have been accepted. Table 15 shows the outputs for DQ3.

Notes

1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits

on page 23 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

16. Absolute Maximum Ratings

Storage Temperature Plastic Packages–65°C to +150°C

Ambient Temperature with Power Applied–65°C to +125°C

Voltage with Respect to Ground VCC (Note 1)–0.5 V to +4.0 V

A9, OE#, and RESET# (Note 2)–0.5 V to +12.5 V

All other pin s (Note 1) –0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3)200 mA

Notes

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for periods of up to 20 ns. See

Figure 17.1 on page 25. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transit i ons, input or I/O pins may overshoot to VCC +2.0 V for periods

up to 20 ns. See Figure 17.2 on page 25.

2. Minimum DC input voltage on pins A9, OE#, and RE SET# is –0. 5 V. During volt age tr ansitions, A9, OE#, an d RESET# may undershoot VSS to –2.0 V for periods of up

to 20 ns. See Figure 17.1 on page 25. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14. 0 V for periods up to 20 ns.

3. No more than one output may be sh orted to ground at a time. Duration of the short circuit should not be grea ter than one second.

4. Stresses above those listed under Absolute Maximum Ratings on page 24 may cause permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to

absolute maximum rating conditions for extended periods may affect device reliability.

Table 15. Write Oper ation Status

Operation DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Readin g w i thin Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

Document Number: 002-01235 Rev. *B Page 25 of 46

S29AL004D

17. Operating Ranges

Industrial (I) Devices

Ambient Temperature (TA) -40°C to +85°C

Extended (N) Devices

Ambient Temperature (TA) -40°C to +125°C

VCC Supply Voltages

VCC for full voltage range +2.7 V to +3.6 V

Operating ranges define those limit s between which the functionality of the device is guaranteed.

Figure 17.1 Maximum Negative Overshoot Waveform

Figure 17.2 Maximum Positive Overshoot Waveform

18. DC Characteristics

Parameter Des cription Test Conditions Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC,

VCC = VCC max 1.0 µA

ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA

ILO Output Leakage Current VOUT = VSS to VCC,

VCC = VCC max 1.0 µA

ICC1 VCC Active Read Current

(Notes 1, 2)

CE# = VIL, OE# = VIH,

Byte Mode

10 MHz 18 35

5 MHz 9 16

1 MHz 2 4

CE# = VIL, OE# = VIH,

Word Mode

10 MHz 15 30

5 MHz 9 16

1 MHz 2 4

ICC2 VCC Active Write Current

(Notes 2, 3, 6)CE# = VIL, OE# = VIH 20 35 mA

ICC3 VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC0.3 V 0.2 5 µA

ICC4 VCC Reset Current (Notes 2, 4) RESET# = VSS 0.3 V 0.2 5 µA

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

VCC

+2.0 V

VCC

+0.5 V

2.0 V

Document Number: 002-01235 Rev. *B Page 26 of 46

S29AL004D

Notes

1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.

2. Maximum ICC specifications are tested with VCC = VCCmax.

3. ICC active while Embedded Erase or Embedded Program is in progress.

4. At extended temperature range (>+85°C), typical current is 5µA and maximum current is 10µA.

5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.

6. Not 100% tested.

18.1 Zero Power Flash

Figure 18.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

Note

Addresses are switching at 1 MHz.

ICC5 Automatic Sleep Mode

(Notes 2, 4, 5)VIH = VCC  0.3 V;

VIL = VSS 0.3 V 0.2 5 µA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 x VCC VCC + 0.3 V

VID Voltage for Autoselect and

Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V

VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V

VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 2.4 V

VOH2 IOH = –100 µA, VCC = VCC min V

CC–0.4

VLKO Low VCC Lock-Out Voltage 2.3 2.5 V

Parameter Des cription Test Conditions Min Typ Max Unit

00 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in mA

Time in ns

Document Number: 002-01235 Rev. *B Page 27 of 46

S29AL004D

Figure 18.2 Typical ICC1 vs. Frequency

Note

T = 25 C

19. Test Conditions

Figure 19.1 Test Setup

Note

Nodes are IN3064 or equivalent.

1 2345

Frequency in MHz

Supply Current in mA

2.7 V

3.6 V

2.7 k

CL6.2 k

3.3 V

Device

Under

Test

Document Number: 002-01235 Rev. *B Page 28 of 46

S29AL004D

21. Key to Switching Waveforms

Figure 21.1 Input Waveforms and Measu r ement Levels

Table 20. Test Specifications

Test Condition 55 70 90 Uni t

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 30 100 pF

Input Rise and Fall Times 5ns

Input Pulse Levels 0.0 or VCC

VInput timing measurement reference levels 0.5VCC

Output timing measurement reference levels 0.5VCC

Waveform Inputs Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

0.0 V OutputMeasurement LevelInput 0.5VCC 0.5VCC

Document Number: 002-01235 Rev. *B Page 29 of 46

S29AL004D

22. AC Characteristics

22.1 Read Operations

Notes

1. Not 100% tested.

2. See Figure 19.1 on page 27 and Table 20 on page 28 for test specifications.

Figure 23.1 Read Operations Timings

Table 23. Read Operations

Parameter Description Speed Options

JEDEC Std Test Setup 55 70 90 Unit

tAVAV tRC Read Cycle Time (Note 1) Min557090

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max557090

tELQV tCE Chip Enable to Output Delay OE# = VIL Max557090

tGLQV tOE Output Enable to Output Delay Max 25 30 35

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16

tSR/W Latency Between Read and Write Operations Min 20

tOEH Output Enable

Hold Time (Note 1) Read Min 0

Toggle and Data# Polling Min 10

tAXQX tOH Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First (Note 1) Min 0

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output Valid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tSR/W

tOH

Document Number: 002-01235 Rev. *B Page 30 of 46

S29AL004D

Note

Not 100% tested .

Figure 24.1 RESET# Timings

Table 24. Hardware Reset (RESET#)

Parameter Description All Speed Options

JEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded Algor ithms) to

Read or Writ e (See Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note) 500 ns

tRP RESET# Pulse Width

Min

500 ns

tRH RESET# High Time Before Read (See Note) 50 ns

tRPD RESET# Low to Standby Mode 20 µs

tRB RY/BY# Recovery Time 0 ns

Table 25. Word/Byte Configuration (BYTE#)

Parameter Description Speed Opti ons

JEDEC Std 55 70 90 Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5

nstFLQZ BYTE# Switching Low to Output HIGH Z Max 16

tFHQV BYTE# Switching High to Output Active Min 55 70 90

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

tRH

Document Number: 002-01235 Rev. *B Page 31 of 46

S29AL004D

Figure 25.1 BYTE# Timings for Read Operations

Figure 25.2 BYTE# Timings for Write Operations

Note

Refer to Erase/Program Operations on page 32 for tAS and tAH specifications.

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte to

word mode

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

Document Number: 002-01235 Rev. *B Page 32 of 46

S29AL004D

25.1 Erase/Program Operations

Notes

1. Not 100% tested.

2. See the Sector Erase Command Sequence on page 18 section for more information.

Figure 25.3 Program Operation T imings

Notes

1. PA = program address, PD = program data, DOUT is the true data at the program address.

2. Illustration shows device in word mode.

Parameter Description Speed Options

JEDEC Std 55 70 90 Unit

tAVAV tWC Write Cycle Time (Note 1)

Min

55 70 90

tAVWL tAS Address Setup Time 0

tWLAX tAH Address Hold Time 45

tDVWH tDS Data Setup Time 35 35 45

tWHDX tDH Data Hold Time 0

tOES Output Enable Setup Time 0

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) 0

tELWL tCS CE# Setup Time 0

tWHEH tCH CE# Hold Time 0

tWLWH tWP Write Pulse Width 35

tWHWL tWPH Write Pulse Width High 30

tSR/W Latency Between Read and Write Operations Min 20 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Byte

Typ

5µs

Word 7

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 0.7 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Recovery Time from RY/B Y# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Max 90

OE#

WE#

CE#

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC

tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

BUSY

tCH

Document Number: 002-01235 Rev. *B Page 33 of 46

S29AL004D

Figure 25.4 Chip/Sector Erase Operation Timings

Notes

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 20).

2. Illustration shows device in word mode.

Figure 25.5 Back to Back Read/Write Cycle Timing

OE#

CE#

Addresses

WE#

Data

2AAh SA

WPH

555h for chip erase

10 for Chip Erase

30h

VCS

55h

Progress Complete

WHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

BUSY

Addresses

CE#

OE#

WE#

Data Valid In Valid Out

Valid

In Valid

Out

PA PA PA PA

tWC

tACC

tCE

tOE

tCP

tAH tCPH

tGHWL

tWP

tWDH tDS

tDH

tOH

tDF

tSR/W

tRC

Document Number: 002-01235 Rev. *B Page 34 of 46

S29AL004D

Figure 25.6 Data# Polling Timings (During Embedded Algorithms)

Note

VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle

Figure 25.7 Toggle Bit Timings (During Embedded Algorithms)

Note

VA = Valid address; not required for DQ6. Illustration shows fir s t two status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 25.8 DQ2 vs. DQ6

Note

The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when rea d at an ad dress within an erase-suspended sector.

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

BUSY

Addresses VA

OEH

VA VA

ACC

Valid Data

Valid Status

(first read) (second read) (stops toggling)

Valid Status

Document Number: 002-01235 Rev. *B Page 35 of 46

S29AL004D

Note

Not 100% tested .

Figure 26.1 Temporary Sector Unprotect Timing Diagram

Table 26. Temporary Sector Unprotect

Parameter All Speed Options

JEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

RESET#

tVIDR

12 V

0 or 3 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 3 V

Document Number: 002-01235 Rev. *B Page 36 of 46

S29AL004D

Figure 26.2 Sector Protect/Unprotect Timing Diagram

Note

For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Note

1. Not 100% tested.

2. See Erase And Programming Performance on page 37 for more information.

Table 27. Alternate CE# Controlled Erase/Program Operation

Parameter Description Speed Options

JEDEC Std 55 70 90 Unit

tAVAV tWC Write Cycle Time (Note 1)

Min

55 70 90

tAVEL tAS Address Setup Time 0

tELAX tAH Address Hold Time 45

tDVEH tDS Data Setup Time 35 35 45

tEHDX tDH Data Hold Time 0

tOES Output Enable Setup Time 0

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) 0

tWLEL tWS WE# Setup Time 0

tEHWH tWH WE# Hold Time 0

tELEH tCP CE# Pulse Width 35

tEHEL tCPH CE# Pulse Width High 30

tSR/W Latency Between Read and Write Op erations Min 20 ns

tWHWH1 tWHWH1 Programming Operat ion

(Note 2) Byte

Typ

5µs

Word 7

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 0.7 sec

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Protect/Unprotect Verify

Document Number: 002-01235 Rev. *B Page 37 of 46

S29AL004D

Figure 27.1 Alternate CE# Contro lled Write Operation Timings

Notes

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

28. Erase And Programming Performance

Notes

1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern.

2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip prog ramming time listed, since most bytes progr am faster th an th e maxi mum progr am

times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time require d to exe cute the two- o r four -bus-cycl e sequence f or the pr ogram command . See Table 13 on page 19 for further informati on

on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 10 s Excludes 00h programming

prior to erasure

Chip Erase Time 11 s

Byte Programming Time 7 210 µs

Excludes system level

overhead (Note 5)

Word Programming Time 7 210 µs

Chip Programming Time

(Note 3) Byte Mode 4.2 12.5 s

Word Mode 2.9 8.5 s

GHEL

OE#

CE#

WE#

RESET#

Data

Addresses

DQ7# D

OUT

CPH

Data# Polling

A0 for program

55 for erase

WHWH1 or 2

RY/BY#

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

BUSY

Document Number: 002-01235 Rev. *B Page 38 of 46

S29AL004D

Notes

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

Table 29. TSOP, SO, And BGA Pin Capacitance

Parameter Symbol Parameter Description Test Setup Package Typ Max Unit

CIN Input Capacitance VIN = 0 TSOP, SO 6 7.5

BGA 4.2 5.0

COUT Output Capacitance VOUT = 0 TSOP, SO 8.5 12

BGA 5.4 6.5

CIN2 Control Pin Capacitance VIN = 0 TSOP, SO 7.5 9

BGA 3.9 4.7

Document Number: 002-01235 Rev. *B Page 39 of 46

S29AL004D

30. Physical Dimensions

30.1 TS 048—48-Pin Standard TSO P

Note

For reference only. BSC is an ANSI standard for Basic Space Cent ering.

MO-142 (D) DD

MIN

0.05

0.95

0.17

0.10

18.30

19.80

0.50

0˚

0.08

11.90

0.50 BASIC

MAX

0.15

1.20

0.27

0.16

0.21

8˚

0.20

18.50

12.10

0.70

20.20

0.23

1.05

0.20

1.00

0.22

18.40

20.00

0.60

12.00

NOM

Symbol

Jedec

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT

HORIZONTAL SURFACE.

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15mm (.0059") PER SIDE.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE

BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

REVERSE PIN OUT (TOP VIEW)

2X (N/2 TIPS)

0.10

SEATING

PLANE

SEE DETAIL A

2X (N/2 TIPS)

0.25

2X 0.10

0.10

STANDARD PIN OUT (TOP VIEW)

SEE DETAIL B

DETAIL A

(c)

θ°

0.25MM (0.0098") BSC

GAUGE PLANE

PARALLEL TO

SEATING PLANE

(c)

WITH PLATING

BASE METAL

0.08MM (0.0031") M C A - B S

SECTION B-B

DETAIL B

e/2

X = A OR B

3355 \ 16-038.10

Document Number: 002-01235 Rev. *B Page 40 of 46

S29AL004D

30.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm

3338 \ 16-038.25b

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

PACKAGE VBK 048

JEDEC N/A

8.15 mm x 6.15 mm NOM

PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 OVERALL THICKNESS

A1 0.18 --- --- BALL HEIGHT

A2 0.62 --- 0.76 BODY THICKNESS

D 8.15 BSC. BODY SIZE

E 6.15 BSC. BODY SIZE

D1 5.60 BSC. BALL FOOTPRINT

E1 4.00 BSC. BALL FOOTPRINT

MD 8 ROW MATRIX SIZE D DIRECTION

ME 6 ROW MATRIX SIZE E DIRECTION

N 48 TOTAL BALL COUNT

fb 0.35 --- 0.43 BALL DIAMETER

e 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

--- DEPOPULATED SOLDER BALLS

SIDE VIEW

TOP VIEW

SEATING PLANE

(4X)

0.10

C0.10

C0.08

BOTTOM VIEW

A1 CORNER

f 0.15 C

BCDEFG

f 0.08

PIN A1

CORNER

INDEX MARK

Document Number: 002-01235 Rev. *B Page 41 of 46

S29AL004D

30.3 SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

Document Number: 002-01235 Rev. *B Page 42 of 46

S29AL004D

31. Revision Summary

Spansion Publication Number: S29AL004D_00

31.1 Revision A0 (November 12, 2004)

Initial release

31.2 Revision A1 (February 18, 2005)

Added Cover Page

Ordering Information

Change package type from S to M.

Valid Combination Table

Package Type, Material, and Tempe r ature Range from SAL and SFI to MAL and MFI.

Changed Package Description from SSOP to SOP

Erase and Programming Performance Table

Changed chip erase time in table.

31.3 Revision A2 (June 1, 2005)

Global

Updated status from Advance Information to Pre liminary data sheet.

Distinctive Characteristics

Updated High Performance access time to 55 ns.

Product Selector Guide

Added 55 ns speed column.

Ordering Information

Added tube packing type.

Added Extended Temper ature range.

Added 55 ns speed option.

Valid Combinations Table

Added two designators to packing types.

Added speed option along with speed option package type nomenclature.

Added Note for this table.

Operating Range

Added extended temperature range information.

Moved Figures 7 and 8 under Operati ng Range area.

Erase and Programming Performance

Changed Byte Programing Time values for Typica l and Maximum.

Document Number: 002-01235 Rev. *B Page 43 of 46

S29AL004D

31.4 Revision A3 (June 21, 2005)

Global

Update from Preliminary status to full Data Sheet.

Ordering Information

Added two Model Numbers.

Valid Combinations Table

Updated table with new Model Numbers and Package Types.

31.5 Revision A4 (May 22, 2006)

AC Characteristics

Added tSR/W parameter to read and erase/program operations tables. Added back-to-back read/write cycle timing diagram.

Changed maximum value for tDF and tFLQZ.

31.6 Revision A5 (June 22, 2006)

Connection Diagrams

Changed inputs on pins 1 and 2 of SO package.

Read Operations Timings figure

Connected end of tRC period to start of tOH period.

Erase/Program Operations table

Changed tBUSY to a maximum specification.

31.7 Revision A6 (February 27, 2009)

Global

Added obsolescence information to Cover Shee t, Distinctive Char acteristics, and Ordering Information section s of data sheet.

Document Number: 002-01235 Rev. *B Page 44 of 46

S29AL004D

Document History Page

Documen t Title:S2 9 AL004D, 4- Mbi t (51 2K x 8-Bit/256K x 16-Bit), 3 V Boot Sector Flash

Document Number: 002-01235

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

** - BWHA

11/12/2004 Initial release

02/18/2005 Added Cover Page

Ordering Information

Change package type from S to M.

Valid Combin ation Table

Package Type, Material, and Temperature Range from SAL and SFI to

MAL and MFI.

Changed Package Description from SSOP to SOP

Erase and Programming Performance Table

Changed chip erase time in table.

06/01/2005 Global

Updated status from Advance Information to Preliminary data sheet.

Distinctive Characteristics

Updated High Performance access time to 55 ns.

Product Selector Guide

Added 55 ns speed column.

Ordering Information

Added tube packing type.

Added Extended Temperature range.

Added 55 ns speed option.

Valid Combin ations Table

Added two designators to packing types.

Added speed option along with sp eed option package type nomencl ature.

Added Note for this table.

Operating Range

Added extended temperature range information.

Moved Figures 7 and 8 under Operating Ra nge area.

Erase and Programming Performance

Changed Byte Programing Time va lues for Typical and Maximum.

06/21/2005 Global

Update from Preliminary status to full Data Sheet.

Ordering Information

Added two Model Numbers.

Valid Combin ations Table

Updated table with new Model Numbers and Package Types.

05/22/2006 AC Characteristics

Added tSR/W parameter to read and erase/program operations tables.

Added back-to-back read/write cycle

timing diagram. Changed maximu m value for tDF and tFLQZ.

Document Number: 002-01235 Rev. *B Page 45 of 46

S29AL004D

** - BWHA

06/22/2006 Connection Diagrams

Changed inputs on pins 1 and 2 of SO package.

Read Operations Timings figure

Connected end of tRC period to start of tOH period.

Erase/Program Operations table

Changed tBUSY to a maximum specification.

02/27/2009 Global

Added obsolescence information to Cover Sheet, Distinctive

Characteristics, and Ordering Information

sections of data sheet.

*A 5043522 BWHA 12/09/2015 Updated to Cypress template

*B 5602312 PRIT 01/25/2017 Obsolete document.

Completing Sunset Review.

Document History Page (Continued)

Documen t Title:S2 9 AL004D, 4- Mbi t (51 2K x 8-Bit/256K x 16-Bit), 3 V Boot Sector Flash

Document Number: 002-01235

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

Document Number: 002-01235 Rev. *B Revised January 25, 2017 Page 46 of 46

Cypress®, Span sio n®, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress

Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypres s pro d ucts ar e not war ran t ed no r int e nded to be used fo r

medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to an express written agreement wit h C ypr ess. Fu rth erm ore, Cyp ress doe s not author i ze i t s pro ducts for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress pr oducts in life-su pport systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunctio n with a Cypress

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without

the express written perm ission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cyp ress does not

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

S29AL004D

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