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Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
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contained therein.
2SJ553(L), 2SJ553(S)
Silicon P Channel MOS FET
High Speed Power Switching
ADE-208-650B (Z)
3rd. Edition
Jul. 1998
Features
Low on-resistance
RDS(on) = 0.028typ.
Low drive current.
4V gate drive devices.
High speed switching.
Outline
1. Gate
2. Drain
3. Source
4. Drain
123
4
123
4
LDPAK
D
G
S
2SJ553(L),2SJ553(S)
2
Absolute Maximum Ratings (Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS –60 V
Gate to source voltage VGSS ±20 V
Drain current ID–30 A
Drain peak current ID(pulse)Note1 –120 A
Body-drain diode reverse drain current IDR –30 A
Avalanche current IAP Note3 –30 A
Avalanche energy EAR Note3 77 mJ
Channel dissipation Pch Note2 75 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Note: 1. PW 10µs, duty cycle 1 %
2. Value at Tc = 25°C
3. Value at Tch = 25°C, Rg 50
2SJ553(L),2SJ553(S)
3
Electrical Characteristics (Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS –60 V ID = –10mA, VGS = 0
Gate to source breakdown voltage V(BR)GSS ±20——V I
G = ±100µA, VDS = 0
Zero gate voltege drain current IDSS –10 µAV
DS = –60 V, VGS = 0
Gate to source leak current IGSS ——±10 µAV
GS = ±16V, VDS = 0
Gate to source cutoff voltage VGS(off) –1.0 –2.0 V ID = –1mA, VDS = –10V
Static drain to source on state RDS(on) 0.028 0.037 ID = –15A, VGS = –10V Note4
resistance RDS(on) 0.038 0.055 ID = –15A, VGS = –4V Note4
Forward transfer admittance |yfs| 1525—S I
D = –15A, VDS = –10V Note4
Input capacitance Ciss 2500 pF VDS = –10V
Output capacitance Coss 1300 pF VGS = 0
Reverse transfer capacitance Crss 300 pF f = 1MHz
Turn-on delay time td(on) 25 ns VGS = –10V, ID = –15A
Rise time tr 150 ns RL = 2
Turn-off delay time td(off) 350 ns
Fall time tf 220 ns
Body–drain diode forward voltage VDF –0.95 V IF = –30A, VGS = 0
Body–drain diode reverse
recovery time trr 100 ns IF = –30A, VGS = 0
diF/ dt =50A/µs
Note: 4. Pulse test
2SJ553(L),2SJ553(S)
4
Main Characteristics
80
60
40
20
050 100 150 200
–100
–10
–1
–0.1
–0.1 –1 –10
0–2 –4 –6 –8 –10 0 1–2–3–45
–100
–1000
–50
–40
–30
–20
–10 -25 °C
25 °C
1 ms
Ta = 25 °C
10 µs
DS
Pulse Test
V = –10 V
PW = 10 ms (1 shot)
100 µs
–50
–40
–30
–20
–10 –2.5 V
–2 V
V = –10 V
GS
–8 V
–5 V
–3.5 V
–3 V
–4 V
Channel Dissipation Pch (W)
Power vs. Temperature Derating
Drain to Source Voltage V (V)
DS
Drain Current I (A)
D
Maximum Safe Operation Area
Drain to Source Voltage V (V)
DS
Drain Current I (A)
D
Typical Output Characteristics
Gate to Source Voltage V (V)
GS
Typical Transfer Characteristics
Operation in
this area is
limited by R
DS(on)
Drain Current I (A)
D
Case Temperature Tc (°C)
Tc = 75 °C
DC Operation
(Tc = 25 °C)
Pulse Test
2SJ553(L),2SJ553(S)
5
–5
–4
–3
–2
–1
0–4 –8 –12 –16 –20
0.1
0.08
0.06
0.04
0.02
–40 0 40 80 120 160
0
1
0.5
0.05
0.02
0.01–1 –3 –10 –30 –100 –300 –1000
–20 A
0.2
0.1
V = –4 V
GS
–10,–20A
Pulse Test
Pulse Test
Pulse Test
I = –50 A
D
GS
V = –10 V
–50 A
–20 A
–10 V
–10 A
GS
V = –4 V
–10 A
–0.1 –1 –10 –100
–0.3 –3 –30
100
10
0.1
1
0.3
3
30
25 °C
75 °C
V = –10 V
DS
Pulse Test
Gate to Source Voltage V (V)
GS
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
V (V)
DS(on)
Drain to Source Saturation Voltage
Drain Current I (A)
D
Drain to Source On State Resistance
R ( )
DS(on)
Static Drain to Source on State Resistance
vs. Drain Current
Case Temperature Tc (°C)
R ( )
DS(on)
Static Drain to Source on State Resistance
Static Drain to Source on State Resistance
vs. Temperature
Drain Current I (A)
D
Forward Transfer Admittance |y | (S)
fs
Forward Transfer Admittance vs.
Drain Current
Tc = –25 °C
I = –50 A
D
2SJ553(L),2SJ553(S)
6
1000
500
200
50
100
20
10
0.1 0.3 30 –10 –20 –30 –40 –50
10000
1000
300
100
0
–20
–40
–60
–80
0
0
–4
–8
–12
–16
–20–100 40 80 120 160 200
1000
200
500
100
20
50
10
–0.1 –0.3 –1 –3 –10
130
30
10
DS
V
GS
V
V = –10 V
–25 V
–50 V
DD
100
V = –10 V
–25 V
–50 V
DD
3000 Ciss
Coss
Crss
V = 0
f = 1 MHz
GS
–30 –100
r
t
d(off)
t
tf
d(on)
t
10
di / dt = 50 A / µs
V = 0, Ta = 25 °C
GS
Reverse Drain Current I (A)
DR
Reverse Recovery Time trr (ns)
Body–Drain Diode Reverse
Recovery Time
Capacitance C (pF)
Drain to Source Voltage V (V)
DS
Typical Capacitance vs.
Drain to Source Voltage
Gate Charge Qg (nc)
Drain to Source Voltage V (V)
DS
Gate to Source Voltage V (V)
GS
Dynamic Input Characteristics
Drain Current I (A)
D
Switching Time t (ns)
Switching Characteristics
V = –10 V, V = –30 V
PW = 5 µs, duty < 1 %
GS DD
=
I = –30 A
D
2SJ553(L),2SJ553(S)
7
–50
–40
–30
–20
–10
0–0.4 –0.8 –1.2 –1.6 –2.0
D. U. T
Rg
I
Monitor
AP
V
Monitor
DS
V
DD
50
Vin
–15 V
0
I
D
V
DS
I
AP
V
(BR)DSS
L
V
DD
E = • L • I •
2
1V
V – V
AR AP DSS
DSS DD
2
–10 V
–5 V
Pulse Test 100
80
60
40
20
25 50 75 100 125 150
0
V = 0
GS
I = –30 A
V = –25 V
duty < 0.1 %
Rg > 50
AP
DD
Channel Temperature Tch (°C)
Repetitive Avalanche Energy E (mJ)
AR
Maximum Avalanche Energy vs.
Channel Temperature Derating
Avalanche Test Circuit Avalanche Waveform
Source to Drain Voltage V (V)
SD
Reverse Drain Current I (A)
DR
Reverse Drain Current vs.
Source to Drain Voltage
2SJ553(L),2SJ553(S)
8
3
1
0.3
0.1
0.03
0.01
10 µ 100 µ 1 m 10 m 100 m 1 10
DM
P
PW
T
D = PW
T
ch – c(t) = s (t) • ch – c
ch – c = 1.67 °C/W, Tc = 25 °C
θ γ θ
θ
Tc = 25°C
D = 1
0.5
0.2
0.1
0.05
0.02
0.01
1shot pulse
Pulse Width PW (S)
Normalized Transient Thermal Impedance vs. Pulse Width
Normalized Transient Thermao Impedance s (t)
γ
Vin Monitor
D.U.T.
Vin
-10 V
RL
V
= –30 V
DD
tr
td(on)
Vin
90% 90%
10%
10%
Vout
td(off)
Vout
Monitor
50
90%
10%
tf
Switching Time Test Circuit Waveform
2SJ553(L),2SJ553(S)
9
Package Dimensions
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
LDPAK (L)
1.4 g
10.2 ± 0.3
0.86
0.76 ± 0.1
2.54 ± 0.5
2.54 ± 0.5
+ 0.2
– 0.1
1.2 ± 0.2
4.44 ± 0.2
1.3 ± 0.15
2.59 ± 0.2
0.4 ± 0.1
11.0 ± 0.5
8.6 ± 0.3
10.0
11.3 ± 0.5
+ 0.3
– 0.5
(1.4)
1.27 ± 0.2
As of January, 2001
Unit: mm
2SJ553(L),2SJ553(S)
10
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
LDPAK (S)-(1)
1.3 g
10.2 ± 0.3
1.27 ± 0.2
(1.5)
(1.4)
8.6 ± 0.3
10.0 + 0.3
– 0.5
4.44 ± 0.21.3 ± 0.15
0.1 + 0.2
– 0.1
0.4 ± 0.1
0.86 + 0.2
– 0.1
2.54 ± 0.5
2.54 ± 0.5
1.2 ± 0.2
3.0+ 0.3
– 0.5
(1.5)
7.8
6.6
2.2
1.7
7.8
7.0
As of January, 2001
Unit: mm
2SJ553(L),2SJ553(S)
11
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
LDPAK (S)-(2)
1.35 g
10.2 ± 0.3
1.27 ± 0.2
(1.5)
(1.4)
8.6 ± 0.3
10.0 + 0.3
– 0.5
4.44 ± 0.21.3 ± 0.2
0.1 + 0.2
– 0.1
0.4 ± 0.1
0.86 + 0.2
– 0.1
2.54 ± 0.5
2.54 ± 0.5
1.2 ± 0.2
5.0+ 0.3
– 0.5
(1.5)
7.8
6.6
2.2
1.7
7.8
7.0
As of January, 2001
Unit: mm
2SJ553(L),2SJ553(S)
12
Cautions
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copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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For further information write to:
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