© 2007 Microchip Technology Inc. Preliminary DS39887B
PIC18F2458/2553/4458/4553
Data Sheet
28/40/44-Pin High-Performance,
Enhanced Flash, USB Microcontrollers
with 12-Bit A/D and nanoWatt Technology
DS39887B-page ii Preliminary © 2007 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 1
PIC18F2458/2553/4458/4553
Universal Serial Bus Features:
• USB V2.0 Compliant
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
• Supports Control, Interrupt, Isochronous and Bulk
Transfers
• Supports up to 32 Endpoints (16 bidirectional)
• 1-Kbyte Dual Access RAM for USB
• On-Chip USB Transceiver with On-Chip Voltage
Regulator
• Interface for Off-Chip USB Transceiver
• Streaming Parallel Port (SPP) for USB Streaming
Transfers (40/44-pin devices only)
Power-Managed Modes:
• Run: CPU On, Peripherals On
• Idle: CPU Off, Peripherals On
• Sleep: CPU Off, Peripherals Off
• Idle mode Currents Down to 5.8 μA Typical
• Sleep mode Currents Down to 0.1 μA Typical
• Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V
• Watchdog Timer: 2.1 μA Typical
• Two-Speed Oscillator Start-up
Special Microcontroller Features:
• C Compiler Optimized Architecture with Optional
Extended Instruction Set
• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
• Flash/Data EEPROM Retention: > 40 Years
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
• Programmable Code Protection
• Single-Supply 5V In-Circuit Serial
Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Optional Dedicated ICD/ICSP Port (44-pin TQFP
package only)
• Wide Operating Voltage Range (2.0V to 5.5V)
Flexible Oscillator Structure:
• Four Crystal modes, Including High-Precision PLL
for USB
• Two External Clock modes, up to 48 MHz
• Internal Oscillator Block:
- 8 user-selectable frequencies, from 31 kHz
to 8 MHz
- User-tunable to compensate for frequency drift
• Secondary Oscillator using Timer1 @ 32 kHz
• Dual Oscillator Options allow Microcontroller and
USB module to Run at Different Clock Speeds
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
Peripheral Highlights:
• High-Current Sink/Source: 25 mA/25 mA
• Three External Interrupts
• Four Timer modules (Timer0 to Timer3)
• Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 5.2 ns (T
CY/16)
- Compare is 16-bit, max. resolution 83.3 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bits
• Enhanced Capture/Compare/PWM (ECCP) module:
- Multiple output modes
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
• Enhanced USART module:
- LIN bus support
• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I2C™
Master and Slave modes
• 12-Bit, up to 13-Channel Analog-to-Digital Converter
module (A/D) with Programmable Acquisition Time
• Dual Analog Comparators with Input Multiplexing
Note: This document is supplemented by
the “PIC18F2455/2550/4455/4550 Data
Sheet” (DS39632). See Section 1.0
“Device Overview”.
Device
Program Memory Data Memory
I/O 12-Bit
A/D (ch)
CCP/ECCP
(PWM) SPP
MSSP
EUSART
Comp.
Timers
8/16-Bit
Flash
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes) SPI Master
I2C™
PIC18F2458 24K 12288
2048 256
24 10 2/0 No
YY121/3
PIC18F2553 32K 16384
PIC18F4458 24K 12288 35 13 1/1 Yes
PIC18F4553 32K 16384
28/40/44-Pin High-Performance, Enhanced Flash, USB
Microcontrollers with 12-Bit A/D and nanoWatt Technology
PIC18F2458/2553/4458/4553
DS39887B-page 2 Preliminary © 2007 Microchip Technology Inc.
Pin Diagrams
40-Pin PDIP
PIC18F2458
28-Pin SPDIP, SOIC
PIC18F2553
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1
VUSB
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1/P1A
VUSB
RD0/SPP0
RD1/SPP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4458
PIC18F4553
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 3
PIC18F2458/2553/4458/4553
Pin Diagrams (Continued)
44-Pin TQFP
44-Pin QFN
PIC18F4458
PIC18F4458
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
NC/ICCK(2)/ICPGC(2)
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
NC/ICDT(2)/ICPGD(2)
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
NC/ICPORTS(2)
NC/ICRST(2)/ICVPP(2)
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
RD7/SPP7/P1D 5
4
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
NC
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
RD7/SPP7/P1D 5
4VSS
VDD
VDD
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: Special ICPORT features are available only in 44-pin TQFP packages. See Section 25.9 “Special ICPORT Features” in
the “PIC18F2455/2550/4455/4550 Data Sheet”’.
PIC18F4553
PIC18F4553
PIC18F2458/2553/4458/4553
DS39887B-page 4 Preliminary © 2007 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 19
3.0 Special Features of the CPU...................................................................................................................................................... 29
4.0 Electrical Characteristics ............................................................................................................................................................ 31
5.0 Packaging Information................................................................................................................................................................ 35
Appendix A: Revision History............................................................................................................................................................... 37
Appendix B: Device Differences........................................................................................................................................................... 37
Appendix C: Migration From Mid-Range to Enhanced Devices........................................................................................................... 38
Appendix D: Migration From High-End to Enhanced Devices ............................................................................................................. 38
Index .................................................................................................................................................................................................... 39
The Microchip Web Site....................................................................................................................................................................... 41
Customer Change Notification Service ................................................................................................................................................ 41
Customer Support ................................................................................................................................................................................ 41
Reader Response ................................................................................................................................................................................ 42
Product Identification System............................................................................................................................................................... 43
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2007 Microchip Technology Inc. Preliminary DS39887B-page 5
PIC18F2458/2553/4458/4553
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
The PIC18F4553 family of devices offers the advan-
tages of all PIC18 microcontrollers – namely, high
computational performance at an economical price –
with the addition of high-endurance, Enhanced Flash
program memory. In addition to these features, the
PIC18F4553 family introduces design enhancements
that make these microcontrollers a logical choice for
many high-performance, power sensitive applications.
1.1 Special Features
•12-Bit A/D Converter: The PIC18F4553 family
implements a 12-bit A/D Converter. The A/D
Converter incorporates programmable acquisi-
tion time. This allows for a channel to be selected
and a conversion to be initiated, without waiting
for a sampling period and thus, reducing code
overhead.
1.2 Details on Individual Family
Members
The PIC18F2458/2553/4458/4553 devices are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in the
following ways:
1. Flash program memory (24 Kbytes for
PIC18FX458 devices, 32 Kbytes for
PIC18FX553).
2. A/D channels (10 for 28-pin devices, 13 for
40-pin and 44-pin devices).
3. I/O ports (3 bidirectional ports and 1 input only
port on 28-pin devices, 5 bidirectional ports on
40-pin and 44-pin devices).
4. CCP and Enhanced CCP implementation
(28-pin devices have two standard CCP
modules, 40-pin and 44-pin devices have one
standard CCP module and one ECCP module).
5. Streaming Parallel Port (present only on
40/44-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Members of the PIC18F4553 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2458),
accommodate an operating VDD range of 4.2V to 5.5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2458), function over an extended VDD range
of 2.0V to 5.5V.
• PIC18F2458 • PIC18F4458
• PIC18F2553 • PIC18F4553
Note: This data sheet documents only the
devices’ features and specifications that are
in addition to the features and specifica-
tions of the PIC18F2455/2550/4455/4550
devices. For information on the features
and specifications shared by
the PIC18F2458/2553/4458/4553 and
PIC18F2455/2550/4455/4550 devices,
see the “PIC18F2455/2550/4455/4550
Data Sheet” (DS39632).
PIC18F2458/2553/4458/4553
DS39887B-page 6 Preliminary © 2007 Microchip Technology Inc.
TABLE 1-1: DEVICE FEATURES
Features PIC18F2458 PIC18F2553 PIC18F4458 PIC18F4553
Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz
Program Memory (Bytes) 24576 32768 24576 32768
Program Memory
(Instructions)
12288 16384 12288 16384
Data Memory (Bytes) 2048 2048 2048 2048
Data EEPROM Memory
(Bytes)
256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM
Modules
2 2 1 1
Enhanced Capture/
Compare/PWM Modules
0 0 1 1
Serial Communications MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
Universal Serial Bus (USB)
Module
1 1 1 1
Streaming Parallel Port (SPP) No No Yes Yes
12-Bit Analog-to-Digital
Converter Module
10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Comparators 2 2 2 2
Resets (and Delays) POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
Programmable High/
Low-Voltage Detect
Yes Yes Yes Yes
Programmable Brown-out
Reset
Yes Yes Yes Yes
Instruction Set 75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
Packages 28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
Corresponding Devices with
10-Bit A/D
PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 7
PIC18F2458/2553/4458/4553
FIGURE 1-1: PIC18F2458/2553 (28-PIN) BLOCK DIAGRAM
Data Latch
Data Memory
(2 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
44
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
8
8
ALU<8>
Address Latch
Program Memory
(24/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Tab l e L a tch
8
IR
12
3
ROM Latch
PCLATU
PCU
PORTE
MCLR/VPP/RE3(1)
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: RB3 is the alternate pin for CCP2 multiplexing.
W
Instruction Bus <16>
STKPTR Bank
8
8
8
BITOP
FSR0
FSR1
FSR2
inc/dec
Address
12
Decode
logic
EUSART
Comparator MSSP 12-Bit
ADC
Timer2Timer1 Timer3Timer0
HLVD
CCP2
BOR Data
EEPROM
USB
Instruction
Decode &
Control
State Machine
Control Signals
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Reference
Band Gap
VSS
MCLR(1)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
USB Voltage
Regulator
VUSB
PORTB
PORTC
RB0/AN12/INT0/FLT0/SDI/SDA
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(3)/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(3)/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
PORTA
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
OSC2/CLKO/RA6
CCP1
PIC18F2458/2553/4458/4553
DS39887B-page 8 Preliminary © 2007 Microchip Technology Inc.
FIGURE 1-2: PIC18F4458/4553(40/44-PIN) BLOCK DIAGRAM
Instruction
Decode &
Control
Data Latch
Data Memory
(2 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
44
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(24/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD
RD0/SPP0:RD4/SPP4
PCLATU
PCU
PORTE
MCLR/VPP/RE3(1)
RE2/AN7/OESPP
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: These pins are only available on 44-pin TQFP packages under certain conditions.
4: RB3 is the alternate pin for CCP2 multiplexing.
EUSART
Comparator MSSP 12-Bit
ADC
Timer2Timer1 Timer3Timer0
CCP2
HLVD
ECCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD, VSS
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Reference
Band Gap
MCLR(1)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RB0/AN12/INT0/FLT0/SDI/SDA
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(4)/VPO
OSC2/CLKO/RA6
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
USB
FSR0
FSR1
FSR2
inc/dec
Address
12
Decode
logic
USB Voltage
Regulator
VUSB
ICRST(3)
ICPGC(3)
ICPGD(3)
ICPORTS(3)
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 9
PIC18F2458/2553/4458/4553
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
SPDIP,
SOIC
MCLR/VPP/RE3
MCLR
VPP
RE3
1
I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
CLKI
9
I
I
Analog
Analog
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
PIC18F2458/2553/4458/4553
DS39887B-page 10 Preliminary © 2007 Microchip Technology Inc.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
4
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT/RCV
RA4
T0CKI
C1OUT
RCV
6
I/O
I
O
I
ST
ST
—
TTL
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 — — — See the OSC2/CLKO/RA6 pin.
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
SPDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 11
PIC18F2458/2553/4458/4553
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/FLT0/
SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
21
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.
I2C™ data I/O.
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
22
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
23
I/O
I
I
O
TTL
Analog
ST
—
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
24
I/O
I
I/O
O
TTL
Analog
ST
—
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
RB4/AN11/KBI0
RB4
AN11
KBI0
25
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
RB5/KBI1/PGM
RB5
KBI1
PGM
26
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
27
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
28
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
SPDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
PIC18F2458/2553/4458/4553
DS39887B-page 12 Preliminary © 2007 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
11
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/UOE
RC1
T1OSI
CCP2(2)
UOE
12
I/O
I
I/O
—
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
RC2/CCP1
RC2
CCP1
13
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
RC4/D-/VM
RC4
D-
VM
15
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
RC5
D+
VP
16
I
I/O
O
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
TX
CK
17
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
SDO
18
I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
RE3 — — — See MCLR/VPP/RE3 pin.
VUSB 14
O
P
—
—
Internal USB transceiver power supply.
When the internal USB regulator is enabled, VUSB is the
regulator output.
When the internal USB regulator is disabled, VUSB is the
power input for the USB transceiver.
VSS 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 P — Positive supply for logic and I/O pins.
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
SPDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 13
PIC18F2458/2553/4458/4553
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
VPP
RE3
11818
I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
CLKI
13 32 30
I
I
Analog
Analog
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 33 31
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
PIC18F2458/2553/4458/4553
DS39887B-page 14 Preliminary © 2007 Microchip Technology Inc.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
21919
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
32020
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/
CVREF
RA2
AN2
VREF-
CVREF
42121
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
52222
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT/
RCV
RA4
T0CKI
C1OUT
RCV
62323
I/O
I
O
I
ST
ST
—
TTL
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
72424
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 — — — — — See the OSC2/CLKO/RA6 pin.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 15
PIC18F2458/2553/4458/4553
PORTB is a bidirectional I/O port. PORTB can be soft-
ware programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/
FLT0/SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
33 9 8
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI data in.
I2C™ data I/O.
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
34 10 9
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
35 11 10
I/O
I
I
O
TTL
Analog
ST
—
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
36 12 11
I/O
I
I/O
O
TTL
Analog
ST
—
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
RB4/AN11/KBI0/CSSPP
RB4
AN11
KBI0
CSSPP
37 14 14
I/O
I
I
O
TTL
Analog
TTL
—
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.
RB5/KBI1/PGM
RB5
KBI1
PGM
38 15 15
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
39 16 16
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
40 17 17
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
PIC18F2458/2553/4458/4553
DS39887B-page 16 Preliminary © 2007 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
15 34 32
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/
UOE
RC1
T1OSI
CCP2(2)
UOE
16 35 35
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
RC2/CCP1/P1A
RC2
CCP1
P1A
17 36 36
I/O
I/O
O
ST
ST
TTL
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced CCP1 PWM output, channel A.
RC4/D-/VM
RC4
D-
VM
23 42 42
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
RC5
D+
VP
24 43 43
I
I/O
I
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
TX
CK
25 44 44
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
SDO
26 1 1
I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 17
PIC18F2458/2553/4458/4553
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). PORTD can be software
programmed for internal weak pull-ups on all inputs.
These pins have TTL input buffers when the SPP
module is enabled.
RD0/SPP0
RD0
SPP0
19 38 38
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD1/SPP1
RD1
SPP1
20 39 39
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD2/SPP2
RD2
SPP2
21 40 40
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD3/SPP3
RD3
SPP3
22 41 41
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD4/SPP4
RD4
SPP4
27 2 2
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD5/SPP5/P1B
RD5
SPP5
P1B
28 3 3
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel B.
RD6/SPP6/P1C
RD6
SPP6
P1C
29 4 4
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel C.
RD7/SPP7/P1D
RD7
SPP7
P1D
30 5 5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel D.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
PIC18F2458/2553/4458/4553
DS39887B-page 18 Preliminary © 2007 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/AN5/CK1SPP
RE0
AN5
CK1SPP
82525
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 5.
SPP clock 1 output.
RE1/AN6/CK2SPP
RE1
AN6
CK2SPP
92626
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
SPP clock 2 output.
RE2/AN7/OESPP
RE2
AN7
OESPP
10 27 27
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
SPP output enable output.
RE3 — — — — — See MCLR/VPP/RE3 pin.
VSS 12,
31
6, 30,
31
6, 29 P — Ground reference for logic and I/O pins.
VDD 11, 32 7, 8,
28, 29
7, 28 P — Positive supply for logic and I/O pins.
VUSB 18 37 37
O
P
—
—
Internal USB transceiver power supply.
When the internal USB regulator is enabled, VUSB is
the regulator output.
When the internal USB regulator is disabled, VUSB
is the power input for the USB transceiver.
NC/ICCK/ICPGC(3)
ICCK
ICPGC
——12
I/O
I/O
ST
ST
No Connect or dedicated ICD/ICSP™ port clock.
In-Circuit Debugger clock.
ICSP programming clock.
NC/ICDT/ICPGD(3)
ICDT
ICPGD
——13
I/O
I/O
ST
ST
No Connect or dedicated ICD/ICSP port clock.
In-Circuit Debugger data.
ICSP programming data.
NC/ICRST/ICVPP(3)
ICRST
ICVPP
——33
I
P
—
—
No Connect or dedicated ICD/ICSP port Reset.
Master Clear (Reset) input.
Programming voltage input.
NC/ICPORTS(3)
ICPORTS
— — 34 P — No Connect or 28-pin device emulation.
Enable 28-pin device emulation when connected
to VSS.
NC — 13 — — — No Connect.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 19
PIC18F2458/2553/4458/4553
2.0 12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
10 inputs for the 28-pin devices and 13 for the 40-pin
and 44-pin devices. This module allows conversion of an
analog input signal to a corresponding 12-bit digital
number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
REGISTER 2-1: ADCON0: A/D CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)(1,2)
0110 = Channel 6 (AN6)(1,2)
0111 = Channel 7 (AN7)(1,2)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12
1101 = Unimplemented(2)
1110 = Unimplemented(2)
1111 = Unimplemented(2)
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
Note 1: These channels are not implemented on 28-pin devices.
2: Performing a conversion on unimplemented channels will return a floating input measurement.
PIC18F2458/2553/4458/4553
DS39887B-page 20 Preliminary © 2007 Microchip Technology Inc.
REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W(1) R/W(1) R/W(1)
—— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
Note 1: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40-pin and 44-pin devices.
A = Analog input D = Digital I/O
PCFG3:
PCFG0
AN12
AN11
AN10
AN9
AN8
AN7(2)
AN6(2)
AN5(2)
AN4
AN3
AN2
AN1
AN0
0000(1) A A AAAAAAAAAAA
0001 A A AAAAAAAAAAA
0010 A A AAAAAAAAAAA
0011 DA AAAAAAAAAAA
0100 DD AAAAAAAAAAA
0101 DDDAAAAAAAAAA
0110 DDDDAAAAAAAAA
0111(1) DDDDDAAAAAAAA
1000 DDDDDDAAAAAAA
1001 DDDDDDDAAAAAA
1010 D D DDDDDDAAAAA
1011 D D DDDDDDDAAAA
1100 D D DDDDDDDDAAA
1101 D D DDDDDDDDDAA
1110 D D DDDDDDDDDDA
1111 D D DDDDDDDDDDD
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 21
PIC18F2458/2553/4458/4553
REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 T
AD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
PIC18F2458/2553/4458/4553
DS39887B-page 22 Preliminary © 2007 Microchip Technology Inc.
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
Converter, which generates the result via successive
approximation.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and the A/D Interrupt Flag bit, ADIF, is set. The
block diagram of the A/D module is shown in Figure 2-1.
FIGURE 2-1: A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREF+
Reference
Voltage
VDD
VCFG1:VCFG0
CHS3:CHS0
AN7(1)
AN6(1)
AN5(1)
AN4
AN3
AN2
AN1
AN0
0111
0110
0101
0100
0011
0010
0001
0000
12-Bit
A/D
VREF-
VSS
Converter
AN12
AN11
AN10
AN9
AN8
1100
1011
1010
1001
1000
Note 1: Channels AN5 through AN7 are not available on 28-pin devices.
0X
1X
X1
X0
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 23
PIC18F2458/2553/4458/4553
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets,
and is not affected by any other Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to perform an A/D
conversion:
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as T
AD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 2-2: A/D TRANSFER FUNCTION
FIGURE 2-3: ANALOG INPUT MODEL
Digital Code Output
FFEh
003h
002h
001h
000h
0.5 LSB
1 LSB
1.5 LSB
2 LSB
2.5 LSB
4094 LSB
4094.5 LSB
3 LSB
Analog Input Voltage
FFFh
4095 LSB
4095.5 LSB
VAIN CPIN
Rs ANx
5 pF
VT = 0.6V
VT = 0.6V ILEAKAGE
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD = 25 pF
VSS
VDD
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
various junctions
= Sampling Switch ResistanceRSS
VDD
6V
Sampling Switch
5V
4V
3V
2V
123 4
(kΩ)
PIC18F2458/2553/4458/4553
DS39887B-page 24 Preliminary © 2007 Microchip Technology Inc.
2.1 A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
the minimum acquisition time before starting a
conversion.
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (4096 steps for the 12-bit A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
Example 2-3 shows the calculation of the minimum
required acquisition time, T
ACQ. This calculation is
based on the following application system
assumptions:
CHOLD = 25 pF
Rs = 2.5 kΩ
Conversion Error ≤1/2 LSb
VDD =3V → Rss = 4 kΩ
Temperature = 85°C (system max.)
EQUATION 2-1: ACQUISITION TIME
EQUATION 2-2: A/D MINIMUM CHARGING TIME
EQUATION 2-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=T
AMP + TC + TCOFF
VHOLD = (VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/4096)
TACQ =TAMP + TC + TCOFF
TAMP =0.2 µs
TCOFF = (Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/4096) µs
-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs
1.56 µs
TACQ = 0.2 µs + 1.56 μs + 1.2 µs
2.96 µs
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 25
PIC18F2458/2553/4458/4553
2.2 Selecting and Configuring
Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>), which provides a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisi-
tion time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
Manual acquisition is selected when
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
2.3 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 13 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for T
AD:
•2 T
OSC
•4 TOSC
•8 TOSC
•16 TOSC
•32 TOSC
•64 TOSC
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(T
AD) must be as short as possible, but greater than the
minimum TAD (see parameter 130 for more
information).
Table 2-1 shows the resultant T
AD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 2-1: TAD vs. DEVICE OPERATING FREQUENCIES
A/D Clock Source (TAD)Assumes TAD Min. = 0.8 μs
Operation ADCS2:ADCS0 Maximum FOSC
2 TOSC 000 2.50 MHz
4 TOSC 100 5.00 MHz
8 T
OSC 001 10.00 MHz
16 TOSC 101 20.00 MHz
32 TOSC 010 40.00 MHz
64 TOSC 110 48.00 MHz
RC(1) x11 1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 2.5 μs.
2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.
PIC18F2458/2553/4458/4553
DS39887B-page 26 Preliminary © 2007 Microchip Technology Inc.
2.4 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the TAD time for the new clock speed. After
entering the mode, an A/D acquisition or conversion
may be started. Once started, the device should
continue to be clocked by the same clock source until
the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If bits ACQT2:ACQT0 are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN bit
(OSCCON<7>) must have already been cleared prior
to starting the conversion.
2.5 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog con-
version on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a dig-
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by control-
ling how the PCFG3:PCFG0 bits in
ADCON1 are reset.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 27
PIC18F2458/2553/4458/4553
2.6 A/D Conversions
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘010’, and selecting a
4TAD acquisition time before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
CY wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
2.7 Discharge
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
FIGURE 2-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 2-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10TCY – TAD
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b2
b11 b8 b7 b6 b5 b4 b3
b10 b9
On the following cycle:
Discharge
TAD13TAD12
b0b1
TAD1
(typically 200 ns)
1234567813
Set GO/DONE bit
(Holding capacitor is disconnected)
912
Conversion starts
1234
(Holding capacitor continues
acquiring input)
T
ACQT Cycles TAD Cycles
Automatic
Acquisition
Time
b0b11 b8 b7 b6 b5 b4 b1
b10 b9
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
TAD1
Discharge
10 11
b3 b2
(typically
200 ns)
PIC18F2458/2553/4458/4553
DS39887B-page 28 Preliminary © 2007 Microchip Technology Inc.
2.8 Use of the CCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion, and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automatically
repeat the A/D acquisition period with minimal software
overhead (firmware must move ADRESH:ADRESL to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate T
ACQ
time selected before the Special Event Trigger sets the
GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TABLE 2-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF (4)
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF (4)
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE (4)
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP (4)
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF (4)
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE (4)
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP (4)
ADRESH A/D Result Register High Byte (4)
ADRESL A/D Result Register Low Byte (4)
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 19
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 20
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 21
PORTA —RA6
(2) RA5 RA4 RA3 RA2 RA1 RA0 (4)
TRISA — TRISA6(2) PORTA Data Direction Control Register (4)
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (4)
TRISB PORTB Data Direction Control Register (4)
LATB PORTB Data Latch Register (Read and Write to Data Latch) (4)
PORTE(1) RDPU — — —RE3
(3) RE2(1) RE1(1) RE0(1) (4)
TRISE(1) — — — — — TRISE2 TRISE1 TRISE0 (4)
LATE(1) — — — — — PORTE Data Latch Register (4)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’.
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: For these Reset values, see the “PIC18F2455/2550/4455/4550 Data Sheet”.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 29
PIC18F2458/2553/4458/4553
3.0 SPECIAL FEATURES OF THE
CPU
PIC18F2458/2553/4458/4553 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These include:
• Device ID Registers
3.1 Device ID Registers
The Device ID registers are “read-only” registers.
They identify the device type and revision to device
programmers, and can be read by firmware using
table reads.
TABLE 3-1: DEVICE IDs
Note: For additional details on the Con-
figuration bits, refer to the
“PIC18F2455/2550/4455/4550 Data Sheet”,
Section 25.1 “Configuration Bits”. Device
ID information presented in this section is for
PIC18F2458/2553/4458/4553 only.
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx(1)
Legend: x = unknown, u = unchanged
Note 1: See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the
user.
PIC18F2458/2553/4458/4553
DS39887B-page 30 Preliminary © 2007 Microchip Technology Inc.
REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2458/2553/4458/4553 DEVICES
RRRRRRRR
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
bit 7-5 DEV2:DEV0: Device ID bits
See Register 3-2 for a complete listing.
bit 4-0 REV3:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2458/2553/4458/4553 DEVICES
RRRRRRRR
DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3
bit 7 bit 0
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
bit 7-0 DEV10:DEV3: Device ID bits
DEV10:DEV3
(DEVID2<7:0>)
DEV2:DEV0
(DEVID1<7:5>) Device
0010 1010 011 PIC18F2458
0010 1010 010 PIC18F2553
0010 1010 001 PIC18F4458
0010 1010 000 PIC18F4553
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 31
PIC18F2458/2553/4458/4553
4.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RE3 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC18F2458/2553/4458/4553
DS39887B-page 32 Preliminary © 2007 Microchip Technology Inc.
FIGURE 4-1: PIC18F2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
FIGURE 4-2: PIC18LF2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
48 MHz
5.0V
3.5V
3.0V
2.5V
PIC18F2458/2553/4458/4553
4.2V
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
40 MHz
5.0V
3.5V
3.0V
2.5V
For 2.0V ≤ VDD < 4.2V: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
4 MHz
4.2V
48 MHz
PIC18LF2458/2553/4458/4553
For 4.2V ≤ VDD: FMAX = 48 MHz
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 33
PIC18F2458/2553/4458/4553
TABLE 4-1: A/D CONVERTER CHARACTERISTICS: PIC18F2458/2553/4458/4553 (INDUSTRIAL)
PIC18LF2458/2553/4458/4553 (INDUSTRIAL)
Param
No. Sym Characteristic Min Typ Max Units Conditions
A01 NRResolution — — 12 bit ΔVREF ≥ 3.0V
A03 EIL Integral Linearity Error — ±1 ±2.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V
——±2.0LSBV
DD = 5.0V
A04 EDL Differential Linearity Error — ±1 +1.5/-1.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V
——+1.5/-1.0LSBV
DD = 5.0V
A06 EOFF Offset Error — ±1 ±5 LSB VDD = 3.0V ΔVREF ≥ 3.0V
——±3LSBV
DD = 5.0V
A07 EGN Gain Error — ±1 ±1.25 LSB VDD = 3.0V ΔVREF ≥ 3.0V
——±2.00LSBV
DD = 5.0V
A10 — Monotonicity Guaranteed(1) —VSS ≤ VAIN ≤ VREF
A20 ΔVREF Reference Voltage Range
(VREFH – VREFL)
3—V
DD – VSS V For 12-bit resolution
A21 VREFH Reference Voltage High VSS + 3.0V — VDD + 0.3V V For 12-bit resolution
A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V For 12-bit resolution
A25 VAIN Analog Input Voltage VREFL —VREFH V
A30 ZAIN Recommended
Impedance of Analog
Voltage Source
——2.5kΩ
A50 IREF VREF Input Current(2) —
—
—
—
5
150
μA
μA
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
PIC18F2458/2553/4458/4553
DS39887B-page 34 Preliminary © 2007 Microchip Technology Inc.
FIGURE 4-3: A/D CONVERSION TIMING
TABLE 4-2: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK(1)
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
11 10 9 3 2 1
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . . . . .
TCY
0
Param
No. Symbol Characteristic Min Max Units Conditions
130 TAD A/D Clock Period PIC18FXXXX 0.8 12.5(1) μsTOSC based, VREF ≥ 3.0V
PIC18LFXXXX 1.4 25.0(1) μsVDD = 3.0V;
T
OSC based, VREF full range
PIC18FXXXX — 1 μs A/D RC mode
PIC18LFXXXX — 3 μsV
DD = 3.0V; A/D RC mode
131 TCNV Conversion Time
(not including acquisition time)(2)
13 14 TAD
132 TACQ Acquisition Time(3) 1.4 — μs
135 TSWC Switching Time from Convert → Sample — (Note 4)
137 TDIS Discharge Time 0.2 — μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 35
PIC18F2458/2553/4458/4553
5.0 PACKAGING INFORMATION
For packaging information, see the “PIC18F2455/
2550/4455/4550 Data Sheet” (DS39632).
PIC18F2458/2553/4458/4553
DS39887B-page 36 Preliminary © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 37
PIC18F2458/2553/4458/4553
APPENDIX A: REVISION HISTORY
Revision A (May 2007)
Original data sheet for the PIC18F2458/2553/4458/
4553 devices.
Revision B (June 2007)
Changes to Figure 4-2: PIC18LF2458/2553/4458/4553
Voltage-Frequency Graph (Industrial).
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
TABLE B-1: DEVICE DIFFERENCES
Features PIC18F2458 PIC18F2553 PIC18F4458 PIC18F4553
Program Memory (Bytes) 24576 32768 24576 32768
Program Memory (Instructions) 12288 16384 12288 16384
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Capture/Compare/PWM Modules 2 2 1 1
Enhanced Capture/Compare/
PWM Modules
0011
Parallel Communications (SPP) No No Yes Yes
12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Packages 28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
PIC18F2458/2553/4458/4553
DS39887B-page 38 Preliminary © 2007 Microchip Technology Inc.
APPENDIX C: MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
This Application Note is available as Literature Number
DS00716.
APPENDIX D: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”.
This Application Note is available as Literature Number
DS00726.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 39
PIC18F2458/2553/4458/4553
INDEX
A
A/D ..................................................................................... 19
A/D Converter Interrupt, Configuring ......................... 23
Acquisition Requirements .......................................... 24
ADCON0 Register ...................................................... 19
ADCON1 Register ...................................................... 19
ADCON2 Register ...................................................... 19
ADRESH Register ................................................ 19, 22
ADRESL Register ...................................................... 19
Analog Port Pins, Configuring .................................... 26
Associated Registers ................................................. 28
Calculating the Minimum Required
Acquisition Time ................................................ 24
Configuring the Module .............................................. 23
Conversion Clock (TAD) ............................................. 25
Conversion Status (GO/DONE Bit) ............................ 22
Conversions ............................................................... 27
Converter Characteristics .......................................... 33
Discharge ................................................................... 27
Operation in Power-Managed Modes ........................ 26
Selecting and Configuring Acquisition Time .............. 25
Special Event Trigger (CCP) ...................................... 28
Use of the CCP2 Trigger ............................................ 28
Absolute Maximum Ratings ............................................... 31
ADCON0 Register .............................................................. 19
GO/DONE Bit ............................................................. 22
ADCON1 Register .............................................................. 19
ADCON2 Register .............................................................. 19
ADRESH Register .............................................................. 19
ADRESL Register ........................................................ 19, 22
Analog-to-Digital Converter. See A/D.
B
Block Diagrams
A/D ............................................................................. 22
Analog Input Model .................................................... 23
PIC18F2458/2553 ........................................................ 7
PIC18F4458/4553 ........................................................ 8
C
Compare (CCP Module)
Special Event Trigger ................................................. 28
Configuration Bits ............................................................... 29
Customer Change Notification Service .............................. 41
Customer Notification Service ............................................ 41
Customer Support .............................................................. 41
D
Device Differences ............................................................. 37
Device ID Registers ........................................................... 29
Device Overview .................................................................. 5
Other Special Features ................................................ 5
E
Electrical Characteristics .................................................... 31
Equations
A/D Acquisition Time .................................................. 24
A/D Minimum Charging Time ..................................... 24
Errata ................................................................................... 4
I
Internet Address ................................................................. 41
Interrupt Sources
A/D Conversion Complete ......................................... 23
M
Microchip Internet Web Site ............................................... 41
Migration from High-End to
Enhanced Devices ..................................................... 38
Migration from Mid-Range to
Enhanced Devices ..................................................... 38
P
Packaging Information ....................................................... 35
Pin Functions
MCLR/VPP/RE3 ........................................................... 9
MCLR/VPP/RE3 ......................................................... 13
NC/ICCK/ICPGC ....................................................... 18
NC/ICDT/ICPGD ........................................................ 18
NC/ICPORTS ............................................................ 18
NC/ICRST/ICVPP ....................................................... 18
OSC1/CLKI ............................................................ 9, 13
OSC2/CLKO/RA6 .................................................. 9, 13
RA0/AN0 .............................................................. 10, 14
RA1/AN1 .............................................................. 10, 14
RA2/AN2/VREF-/CVREF ....................................... 10, 14
RA3/AN3/VREF+ .................................................. 10, 14
RA4/T0CKI/C1OUT/RCV ..................................... 10, 14
RA5/AN4/SS/HLVDIN/C2OUT ............................ 10, 14
RB0/AN12/INT0/FLT0/SDI/SDA .......................... 11, 15
RB1/AN10/INT1/SCK/SCL .................................. 11, 15
RB2/AN8/INT2/VMO ............................................ 11, 15
RB3/AN9/CCP2/VPO .......................................... 11, 15
RB4/AN11/KBI0 ......................................................... 11
RB4/AN11/KBI0/CSSPP ............................................ 15
RB5/KBI1/PGM .................................................... 11, 15
RB6/KBI2/PGC .................................................... 11, 15
RB7/KBI3/PGD .................................................... 11, 15
RC0/T1OSO/T13CKI ........................................... 12, 16
RC1/T1OSI/CCP2/UOE ....................................... 12, 16
RC2/CCP1 ................................................................. 12
RC2/CCP1/P1A ......................................................... 16
RC4/D-/VM .......................................................... 12, 16
RC5/D+/VP .......................................................... 12, 16
RC6/TX/CK .......................................................... 12, 16
RC7/RX/DT/SDO ................................................. 12, 16
RD0/SPP0 ................................................................. 17
RD1/SPP1 ................................................................. 17
RD2/SPP2 ................................................................. 17
RD3/SPP3 ................................................................. 17
RD4/SPP4 ................................................................. 17
RD5/SPP5/P1B ......................................................... 17
RD6/SPP6/P1C ......................................................... 17
RD7/SPP7/P1D ......................................................... 17
RE0/AN5/CK1SPP .................................................... 18
RE1/AN6/CK2SPP .................................................... 18
RE2/AN7/OESPP ...................................................... 18
VDD ...................................................................... 12, 18
VSS ...................................................................... 12, 18
VUSB .................................................................... 12, 18
Pinout I/O Descriptions
PIC18F2458/2553 ....................................................... 9
PIC18F4458/4553 ..................................................... 13
Power-Managed Modes
and A/D Operation ..................................................... 26
PIC18F2458/2553/4458/4553
DS39887B-page 40 Preliminary © 2007 Microchip Technology Inc.
R
Reader Response .............................................................. 42
Registers
ADCON0 (A/D Control 0) ........................................... 19
ADCON1 (A/D Control 1) ........................................... 20
ADCON2 (A/D Control 2) ........................................... 21
DEVID1 (Device ID 1) ................................................ 30
DEVID2 (Device ID 2) ................................................ 30
Revision History ................................................................. 37
S
Special Features of the CPU ..............................................29
T
Timing Diagrams
A/D Conversion .......................................................... 34
Timing Diagrams and Specifications
A/D Conversion Requirements .................................. 34
W
WWW Address .................................................................. 41
WWW, On-Line Support ...................................................... 4
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 41
PIC18F2458/2553/4458/4553
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
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representatives
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SERVICE
Microchip’s customer notification service helps keep
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specified product family or development tool of interest.
To register, access the Microchip web site at
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Users of Microchip products can receive assistance
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Customers should contact their distributor,
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Technical support is available through the web site
at: http://support.microchip.com
PIC18F2458/2553/4458/4553
DS39887B-page 42 Preliminary © 2007 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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DS39887BPIC18F2458/2553/4458/4553
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
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© 2007 Microchip Technology Inc. Preliminary DS39887B-page 43
PIC18F2458/2553/4458/4553
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC18F2458/2553(1), PIC18F4458/4553(1),
PIC18F2458/2553T(2), PIC18F4458/4553T(2);
VDD range 4.2V to 5.5V
PIC18LF2458/2553(1), PIC18LF4458/4553(1),
PIC18LF2458/2553T(2), PIC18LF4458/4553T(2);
VDD range 2.0V to 5.5V
Temperature Range I = -40°C to +85°C (Industrial)
E= -40°C to +125°C (Extended)
Package PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny PDIP
P=PDIP
ML = QFN
Pattern QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC18LF4553-I/P 301 = Industrial temp., PDIP
package, Extended VDD limits, QTP pattern
#301.
b) PIC18LF2458-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
c) PIC18F4458-I/P = Industrial temp., PDIP
package, normal VDD limits.
Note 1: F = Standard Voltage Range
LF = Wide Voltage Range
2: T = In tape and reel TQFP
packages only.
DS39887B-page 44 Preliminary © 2007 Microchip Technology Inc.
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Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
06/25/07
