© 2007 Microchip Technology Inc. Preliminary DS39887B
PIC18F2458/2553/4458/4553
Data Sheet
28/40/44-Pin High-Performance,
Enhanced Flash, USB Microcontrollers
with 12-Bit A/D and nanoWatt Technology
DS39887B-page ii Preliminary © 2007 Microchip Technology Inc.
Information contained in this publication regarding device
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and may be superseded by updates. It is your responsibility to
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intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
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All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 1
PIC18F2458/2553/4458/4553
Universal Serial Bus Features:
USB V2.0 Compliant
Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
Supports Control, Interrupt, Isochronous and Bulk
Transfers
Supports up to 32 Endpoints (16 bidirectional)
1-Kbyte Dual Access RAM for USB
On-Chip USB Transceiver with On-Chip Voltage
Regulator
Interface for Off-Chip USB Transceiver
Streaming Parallel Port (SPP) for USB Streaming
Transfers (40/44-pin devices only)
Power-Managed Modes:
Run: CPU On, Peripherals On
Idle: CPU Off, Peripherals On
Sleep: CPU Off, Peripherals Off
Idle mode Currents Down to 5.8 μA Typical
Sleep mode Currents Down to 0.1 μA Typical
Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V
Watchdog Timer: 2.1 μA Typical
Two-Speed Oscillator Start-up
Special Microcontroller Features:
C Compiler Optimized Architecture with Optional
Extended Instruction Set
100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
Flash/Data EEPROM Retention: > 40 Years
Self-Programmable under Software Control
Priority Levels for Interrupts
8 x 8 Single-Cycle Hardware Multiplier
Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
Programmable Code Protection
Single-Supply 5V In-Circuit Serial
Programming™ (ICSP™) via Two Pins
In-Circuit Debug (ICD) via Two Pins
Optional Dedicated ICD/ICSP Port (44-pin TQFP
package only)
Wide Operating Voltage Range (2.0V to 5.5V)
Flexible Oscillator Structure:
Four Crystal modes, Including High-Precision PLL
for USB
Two External Clock modes, up to 48 MHz
Internal Oscillator Block:
- 8 user-selectable frequencies, from 31 kHz
to 8 MHz
- User-tunable to compensate for frequency drift
Secondary Oscillator using Timer1 @ 32 kHz
Dual Oscillator Options allow Microcontroller and
USB module to Run at Different Clock Speeds
Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
Peripheral Highlights:
High-Current Sink/Source: 25 mA/25 mA
Three External Interrupts
Four Timer modules (Timer0 to Timer3)
Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 5.2 ns (T
CY/16)
- Compare is 16-bit, max. resolution 83.3 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bits
Enhanced Capture/Compare/PWM (ECCP) module:
- Multiple output modes
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
Enhanced USART module:
- LIN bus support
Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I2C™
Master and Slave modes
12-Bit, up to 13-Channel Analog-to-Digital Converter
module (A/D) with Programmable Acquisition Time
Dual Analog Comparators with Input Multiplexing
Note: This document is supplemented by
the “PIC18F2455/2550/4455/4550 Data
Sheet” (DS39632). See Section 1.0
“Device Overview”.
Device
Program Memory Data Memory
I/O 12-Bit
A/D (ch)
CCP/ECCP
(PWM) SPP
MSSP
EUSART
Comp.
Timers
8/16-Bit
Flash
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes) SPI Master
I2C™
PIC18F2458 24K 12288
2048 256
24 10 2/0 No
YY121/3
PIC18F2553 32K 16384
PIC18F4458 24K 12288 35 13 1/1 Yes
PIC18F4553 32K 16384
28/40/44-Pin High-Performance, Enhanced Flash, USB
Microcontrollers with 12-Bit A/D and nanoWatt Technology
PIC18F2458/2553/4458/4553
DS39887B-page 2 Preliminary © 2007 Microchip Technology Inc.
Pin Diagrams
40-Pin PDIP
PIC18F2458
28-Pin SPDIP, SOIC
PIC18F2553
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1
VUSB
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1/P1A
VUSB
RD0/SPP0
RD1/SPP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4458
PIC18F4553
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 3
PIC18F2458/2553/4458/4553
Pin Diagrams (Continued)
44-Pin TQFP
44-Pin QFN
PIC18F4458
PIC18F4458
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
NC/ICCK(2)/ICPGC(2)
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
NC/ICDT(2)/ICPGD(2)
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
NC/ICPORTS(2)
NC/ICRST(2)/ICVPP(2)
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
RD7/SPP7/P1D 5
4
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
NC
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
RD7/SPP7/P1D 5
4VSS
VDD
VDD
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: Special ICPORT features are available only in 44-pin TQFP packages. See Section 25.9 “Special ICPORT Features” in
the PIC18F2455/2550/4455/4550 Data Sheet”’.
PIC18F4553
PIC18F4553
PIC18F2458/2553/4458/4553
DS39887B-page 4 Preliminary © 2007 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 19
3.0 Special Features of the CPU...................................................................................................................................................... 29
4.0 Electrical Characteristics ............................................................................................................................................................ 31
5.0 Packaging Information................................................................................................................................................................ 35
Appendix A: Revision History............................................................................................................................................................... 37
Appendix B: Device Differences........................................................................................................................................................... 37
Appendix C: Migration From Mid-Range to Enhanced Devices........................................................................................................... 38
Appendix D: Migration From High-End to Enhanced Devices ............................................................................................................. 38
Index .................................................................................................................................................................................................... 39
The Microchip Web Site....................................................................................................................................................................... 41
Customer Change Notification Service ................................................................................................................................................ 41
Customer Support ................................................................................................................................................................................ 41
Reader Response ................................................................................................................................................................................ 42
Product Identification System............................................................................................................................................................... 43
TO OUR VALUED CUSTOMERS
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2007 Microchip Technology Inc. Preliminary DS39887B-page 5
PIC18F2458/2553/4458/4553
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
The PIC18F4553 family of devices offers the advan-
tages of all PIC18 microcontrollers – namely, high
computational performance at an economical price
with the addition of high-endurance, Enhanced Flash
program memory. In addition to these features, the
PIC18F4553 family introduces design enhancements
that make these microcontrollers a logical choice for
many high-performance, power sensitive applications.
1.1 Special Features
12-Bit A/D Converter: The PIC18F4553 family
implements a 12-bit A/D Converter. The A/D
Converter incorporates programmable acquisi-
tion time. This allows for a channel to be selected
and a conversion to be initiated, without waiting
for a sampling period and thus, reducing code
overhead.
1.2 Details on Individual Family
Members
The PIC18F2458/2553/4458/4553 devices are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in the
following ways:
1. Flash program memory (24 Kbytes for
PIC18FX458 devices, 32 Kbytes for
PIC18FX553).
2. A/D channels (10 for 28-pin devices, 13 for
40-pin and 44-pin devices).
3. I/O ports (3 bidirectional ports and 1 input only
port on 28-pin devices, 5 bidirectional ports on
40-pin and 44-pin devices).
4. CCP and Enhanced CCP implementation
(28-pin devices have two standard CCP
modules, 40-pin and 44-pin devices have one
standard CCP module and one ECCP module).
5. Streaming Parallel Port (present only on
40/44-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Members of the PIC18F4553 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2458),
accommodate an operating VDD range of 4.2V to 5.5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2458), function over an extended VDD range
of 2.0V to 5.5V.
PIC18F2458 PIC18F4458
PIC18F2553 PIC18F4553
Note: This data sheet documents only the
devices’ features and specifications that are
in addition to the features and specifica-
tions of the PIC18F2455/2550/4455/4550
devices. For information on the features
and specifications shared by
the PIC18F2458/2553/4458/4553 and
PIC18F2455/2550/4455/4550 devices,
see the PIC18F2455/2550/4455/4550
Data Sheet” (DS39632).
PIC18F2458/2553/4458/4553
DS39887B-page 6 Preliminary © 2007 Microchip Technology Inc.
TABLE 1-1: DEVICE FEATURES
Features PIC18F2458 PIC18F2553 PIC18F4458 PIC18F4553
Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz
Program Memory (Bytes) 24576 32768 24576 32768
Program Memory
(Instructions)
12288 16384 12288 16384
Data Memory (Bytes) 2048 2048 2048 2048
Data EEPROM Memory
(Bytes)
256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM
Modules
2 2 1 1
Enhanced Capture/
Compare/PWM Modules
0 0 1 1
Serial Communications MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
Universal Serial Bus (USB)
Module
1 1 1 1
Streaming Parallel Port (SPP) No No Yes Yes
12-Bit Analog-to-Digital
Converter Module
10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Comparators 2 2 2 2
Resets (and Delays) POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
Programmable High/
Low-Voltage Detect
Yes Yes Yes Yes
Programmable Brown-out
Reset
Yes Yes Yes Yes
Instruction Set 75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
Packages 28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
Corresponding Devices with
10-Bit A/D
PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 7
PIC18F2458/2553/4458/4553
FIGURE 1-1: PIC18F2458/2553 (28-PIN) BLOCK DIAGRAM
Data Latch
Data Memory
(2 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
44
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
8
8
ALU<8>
Address Latch
Program Memory
(24/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Tab l e L a tch
8
IR
12
3
ROM Latch
PCLATU
PCU
PORTE
MCLR/VPP/RE3(1)
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: RB3 is the alternate pin for CCP2 multiplexing.
W
Instruction Bus <16>
STKPTR Bank
8
8
8
BITOP
FSR0
FSR1
FSR2
inc/dec
Address
12
Decode
logic
EUSART
Comparator MSSP 12-Bit
ADC
Timer2Timer1 Timer3Timer0
HLVD
CCP2
BOR Data
EEPROM
USB
Instruction
Decode &
Control
State Machine
Control Signals
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Reference
Band Gap
VSS
MCLR(1)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
USB Voltage
Regulator
VUSB
PORTB
PORTC
RB0/AN12/INT0/FLT0/SDI/SDA
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(3)/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(3)/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
PORTA
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
OSC2/CLKO/RA6
CCP1
PIC18F2458/2553/4458/4553
DS39887B-page 8 Preliminary © 2007 Microchip Technology Inc.
FIGURE 1-2: PIC18F4458/4553(40/44-PIN) BLOCK DIAGRAM
Instruction
Decode &
Control
Data Latch
Data Memory
(2 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
44
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(24/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD
RD0/SPP0:RD4/SPP4
PCLATU
PCU
PORTE
MCLR/VPP/RE3(1)
RE2/AN7/OESPP
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: These pins are only available on 44-pin TQFP packages under certain conditions.
4: RB3 is the alternate pin for CCP2 multiplexing.
EUSART
Comparator MSSP 12-Bit
ADC
Timer2Timer1 Timer3Timer0
CCP2
HLVD
ECCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD, VSS
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Reference
Band Gap
MCLR(1)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RB0/AN12/INT0/FLT0/SDI/SDA
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(4)/VPO
OSC2/CLKO/RA6
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
USB
FSR0
FSR1
FSR2
inc/dec
Address
12
Decode
logic
USB Voltage
Regulator
VUSB
ICRST(3)
ICPGC(3)
ICPGD(3)
ICPORTS(3)
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 9
PIC18F2458/2553/4458/4553
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
SPDIP,
SOIC
MCLR/VPP/RE3
MCLR
VPP
RE3
1
I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
CLKI
9
I
I
Analog
Analog
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10
O
O
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
PIC18F2458/2553/4458/4553
DS39887B-page 10 Preliminary © 2007 Microchip Technology Inc.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
4
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT/RCV
RA4
T0CKI
C1OUT
RCV
6
I/O
I
O
I
ST
ST
TTL
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7
I/O
I
I
I
O
TTL
Analog
TTL
Analog
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 See the OSC2/CLKO/RA6 pin.
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
SPDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 11
PIC18F2458/2553/4458/4553
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/FLT0/
SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
21
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.
I2C™ data I/O.
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
22
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
23
I/O
I
I
O
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
24
I/O
I
I/O
O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
RB4/AN11/KBI0
RB4
AN11
KBI0
25
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
RB5/KBI1/PGM
RB5
KBI1
PGM
26
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
27
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
28
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
SPDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
PIC18F2458/2553/4458/4553
DS39887B-page 12 Preliminary © 2007 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
11
I/O
O
I
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/UOE
RC1
T1OSI
CCP2(2)
UOE
12
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
RC2/CCP1
RC2
CCP1
13
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
RC4/D-/VM
RC4
D-
VM
15
I
I/O
I
TTL
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
RC5
D+
VP
16
I
I/O
O
TTL
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
TX
CK
17
I/O
O
I/O
ST
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
SDO
18
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
RE3 See MCLR/VPP/RE3 pin.
VUSB 14
O
P
Internal USB transceiver power supply.
When the internal USB regulator is enabled, VUSB is the
regulator output.
When the internal USB regulator is disabled, VUSB is the
power input for the USB transceiver.
VSS 8, 19 P Ground reference for logic and I/O pins.
VDD 20 P Positive supply for logic and I/O pins.
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
SPDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 13
PIC18F2458/2553/4458/4553
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
VPP
RE3
11818
I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
CLKI
13 32 30
I
I
Analog
Analog
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 33 31
O
O
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
PIC18F2458/2553/4458/4553
DS39887B-page 14 Preliminary © 2007 Microchip Technology Inc.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
21919
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
32020
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/
CVREF
RA2
AN2
VREF-
CVREF
42121
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
52222
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT/
RCV
RA4
T0CKI
C1OUT
RCV
62323
I/O
I
O
I
ST
ST
TTL
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
72424
I/O
I
I
I
O
TTL
Analog
TTL
Analog
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 See the OSC2/CLKO/RA6 pin.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 15
PIC18F2458/2553/4458/4553
PORTB is a bidirectional I/O port. PORTB can be soft-
ware programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/
FLT0/SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
33 9 8
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI data in.
I2C™ data I/O.
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
34 10 9
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
35 11 10
I/O
I
I
O
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
36 12 11
I/O
I
I/O
O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
RB4/AN11/KBI0/CSSPP
RB4
AN11
KBI0
CSSPP
37 14 14
I/O
I
I
O
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.
RB5/KBI1/PGM
RB5
KBI1
PGM
38 15 15
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
39 16 16
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
40 17 17
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
PIC18F2458/2553/4458/4553
DS39887B-page 16 Preliminary © 2007 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
15 34 32
I/O
O
I
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/
UOE
RC1
T1OSI
CCP2(2)
UOE
16 35 35
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
RC2/CCP1/P1A
RC2
CCP1
P1A
17 36 36
I/O
I/O
O
ST
ST
TTL
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced CCP1 PWM output, channel A.
RC4/D-/VM
RC4
D-
VM
23 42 42
I
I/O
I
TTL
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
RC5
D+
VP
24 43 43
I
I/O
I
TTL
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
TX
CK
25 44 44
I/O
O
I/O
ST
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
SDO
26 1 1
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 17
PIC18F2458/2553/4458/4553
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). PORTD can be software
programmed for internal weak pull-ups on all inputs.
These pins have TTL input buffers when the SPP
module is enabled.
RD0/SPP0
RD0
SPP0
19 38 38
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD1/SPP1
RD1
SPP1
20 39 39
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD2/SPP2
RD2
SPP2
21 40 40
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD3/SPP3
RD3
SPP3
22 41 41
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD4/SPP4
RD4
SPP4
27 2 2
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD5/SPP5/P1B
RD5
SPP5
P1B
28 3 3
I/O
I/O
O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel B.
RD6/SPP6/P1C
RD6
SPP6
P1C
29 4 4
I/O
I/O
O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel C.
RD7/SPP7/P1D
RD7
SPP7
P1D
30 5 5
I/O
I/O
O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel D.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
PIC18F2458/2553/4458/4553
DS39887B-page 18 Preliminary © 2007 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/AN5/CK1SPP
RE0
AN5
CK1SPP
82525
I/O
I
O
ST
Analog
Digital I/O.
Analog input 5.
SPP clock 1 output.
RE1/AN6/CK2SPP
RE1
AN6
CK2SPP
92626
I/O
I
O
ST
Analog
Digital I/O.
Analog input 6.
SPP clock 2 output.
RE2/AN7/OESPP
RE2
AN7
OESPP
10 27 27
I/O
I
O
ST
Analog
Digital I/O.
Analog input 7.
SPP output enable output.
RE3 See MCLR/VPP/RE3 pin.
VSS 12,
31
6, 30,
31
6, 29 P Ground reference for logic and I/O pins.
VDD 11, 32 7, 8,
28, 29
7, 28 P Positive supply for logic and I/O pins.
VUSB 18 37 37
O
P
Internal USB transceiver power supply.
When the internal USB regulator is enabled, VUSB is
the regulator output.
When the internal USB regulator is disabled, VUSB
is the power input for the USB transceiver.
NC/ICCK/ICPGC(3)
ICCK
ICPGC
——12
I/O
I/O
ST
ST
No Connect or dedicated ICD/ICSP™ port clock.
In-Circuit Debugger clock.
ICSP programming clock.
NC/ICDT/ICPGD(3)
ICDT
ICPGD
——13
I/O
I/O
ST
ST
No Connect or dedicated ICD/ICSP port clock.
In-Circuit Debugger data.
ICSP programming data.
NC/ICRST/ICVPP(3)
ICRST
ICVPP
——33
I
P
No Connect or dedicated ICD/ICSP port Reset.
Master Clear (Reset) input.
Programming voltage input.
NC/ICPORTS(3)
ICPORTS
34 P No Connect or 28-pin device emulation.
Enable 28-pin device emulation when connected
to VSS.
NC 13 No Connect.
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39887B-page 19
PIC18F2458/2553/4458/4553
2.0 12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
10 inputs for the 28-pin devices and 13 for the 40-pin
and 44-pin devices. This module allows conversion of an
analog input signal to a corresponding 12-bit digital
number.
The module has five registers:
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
REGISTER 2-1: ADCON0: A/D CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)(1,2)
0110 = Channel 6 (AN6)(1,2)
0111 = Channel 7 (AN7)(1,2)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12
1101 = Unimplemented(2)
1110 = Unimplemented(2)
1111 = Unimplemented(2)
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
Note 1: These channels are not implemented on 28-pin devices.
2: Performing a conversion on unimplemented channels will return a floating input measurement.