Utility pSLC SD L500693 Rev. CV Utility PseudoSLC Secure Digital Engineering Specification Document Number: L500693 Revision: CV (c) 2020 | Delkin Devices Inc. 1 Utility pSLC SD L500693 Rev. CV Overview Capacity PseudoSLC: 4GB up to 64GB Bus Speed Mode 4GB~64GB: UHS-I Flash Interface Flash Type: MLC Power ConsumptionNote1 Power Up Current < 250uA Standby Current < 1000uA Read Current < 400mA Write Current < 400mA MTBF More than 3,000,000 hours Advanced Flash Management Static and Dynamic Wear Leveling Bad Block Management SMART Function Auto-Read Refresh Embedded Mode Storage Temperature Range -40C ~ 85C Performance Read: Up to 95 MB/s Operation Temperature Range -25C ~ 85C Write: Up to 90 MB/s CPRM (Content Protection for Recordable Media) RoHS compliant EMI compliant Notes: 1. Varies by capacity, please see Section "5.1 Power Consumption" for details. (c) 2020 | Delkin Devices Inc. 2 Utility pSLC SD L500693 Rev. CV Performance and Power Consumption Performance Capacity TestMetrixTest @500MB Power Consumption (Maximum) Read (mA) Write (mA) Idle (uA) 45 400 400 1000 95 80 400 400 1000 16GB pSLC 95 90 400 400 1000 32GB pSLC 95 90 400 400 1000 64GB pSLC 95 90 400 400 1000 Read (MB/s) Write (MB/s) 4GB pSLC 90 8GB pSLC NOTE: For more details on Power Consumption, please refer to Section 5.1. Power Consumption figures shown are maximum values and may vary with usage model, SDR configuration or host platform. (c) 2020 | Delkin Devices Inc. 3 Utility pSLC SD L500693 Rev. CV Table of Contents 1. Introduction ............................................................................................................. 6 1.1. General Description ........................................................................................... 6 1.2. 1.2.1. 1.2.2. 1.2.3. 1.2.4. 1.2.5. 1.2.6. 1.2.7. Flash Management ............................................................................................ 7 Error Correction Code (ECC) .................................................................. 7 Wear Leveling ......................................................................................... 7 Bad Block Management .......................................................................... 7 Smart Function ........................................................................................ 7 Auto-Read Refresh ................................................................................. 8 Embedded Mode ..................................................................................... 8 PseudoSLC (pSLC) ................................................................................. 8 2. Product Specification overview ............................................................................. 9 2.1. Performance .................................................................................................... 10 2.2. Part Numbers ................................................................................................... 10 3. Environmental Specifications .............................................................................. 11 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.5. Environmental Conditions ................................................................................ 11 Temperature and Humidity .................................................................... 11 Shock & Vibration .................................................................................. 11 Durability ............................................................................................... 11 Electrostatic Discharge (ESD) ............................................................... 11 EMI Compliance .................................................................................... 11 3.2. MTBF ............................................................................................................... 11 4. SD Card Comparison ............................................................................................ 12 5. Electrical Specifications ....................................................................................... 13 5.1. Power Consumption ......................................................................................... 13 5.2. DC Characteristic ............................................................................................. 13 5.2.1. 5.2.2. 5.2.3. Bus Operation Conditions for 3.3V Signaling ........................................ 13 Bus Signal Line Load ............................................................................ 15 Power Up Time ...................................................................................... 16 5.3. 5.3.1. 5.3.2. 5.3.3. 5.3.4. AC Characteristic ............................................................................................. 17 SD Interface Timing (Default) ................................................................ 17 SD Interface Timing (High-Speed Mode)............................................... 18 SD Interface Timing (SDR12, SDR25 and SDR50 Modes) ................... 20 SD Interface Timing (DDR50 Mode) ...................................................... 22 (c) 2020 | Delkin Devices Inc. 4 Utility pSLC SD 6. 6.1. 7. L500693 Rev. CV Interface ................................................................................................................. 24 Pad Assignment and Descriptions ................................................................... 24 Physical Dimensions ............................................................................................ 26 List of Tables Table 4-1 Comparing SD3.0 Standard, SD3.0 SDHC, SDXC ........................... 12 Table 5-1 Power Consumption by Capacity (Maximum)................................. 13 Table 5-2 Threshold Level for High Voltage Range......................................... 13 Table 5-3 Peak Voltage and Leakage Current .................................................. 14 Table 5-4 Threshold Level for 1.8V Signaling .................................................. 14 Table 5-5 Input Leakage Current for 1.8V Signaling ....................................... 14 Table 5-6 Clock Signal Timing .......................................................................... 20 Table 5-7 Output Timing of Fixed Data Window .............................................. 21 Table 5-8 Bus Timings - Parameters Values (DDR50 Mode) .......................... 23 Table 6-1 SD Memory Card Pad Assignment................................................... 24 (c) 2020 | Delkin Devices Inc. 5 Utility pSLC SD L500693 Rev. CV 1. INTRODUCTION 1.1. General Description Delkin's Utility Secure Digital (SD) card version 3.0 is fully compliant with the specification released by the SD Card Association. The Command List supports [Part 1 Physical Layer Specification Version 3.01 Final] definitions and Card Capacity of Non-secure Area, Secure Area Supports [Part 3 Security Specification Ver3.00 Final] Specifications. The Utility SD 3.0 card utilizes the standard 9-pin interface, designed to operate at a maximum operating frequency of 100MHz. It can alternate between SD mode and SPI mode communication protocols. SD also has the benefits of lower power consumption and high capacity, up to 64GB in pSLC (or pseudoSLC) mode, in a small package. PseudoSLC offers the benefits of performance and endurance approaching that of SLC, yet at a price point closer to MLC. Delkin's Utility Secure Digital 3.0 card is an extremely popular choice today based on its high performance, good reliability and wide compatibility. It is ideal for OEM applications in semiindustrial, medical, handheld, and other markets requiring a controlled, yet cost-effective solution. (c) 2020 | Delkin Devices Inc. 6 Utility pSLC SD L500693 Rev. CV 1.2. Flash Management 1.2.1. Error Correction Code (ECC) Flash memory cells will deteriorate with use, which might generate random bit errors in the stored data. Thus, Delkin's SD 3.0 controller applies the BCH ECC Algorithm, which can detect and correct errors that occur during the Read process, ensure data has been read correctly, as well as protect data from corruption. 1.2.2. Wear Leveling NAND Flash devices can only undergo a limited number of program/erase cycles, and in most cases, the flash media are not used evenly. If some areas are updated more frequently than others, the lifetime of the device would be reduced significantly. Thus, Wear Leveling techniques are applied to extend the lifespan of NAND Flash by evenly distributing write and erase cycles across the media. Delkin's SD 3.0 controller utilizes an advanced Wear Leveling algorithm, which can efficiently spread out the flash usage through the whole flash media area. Moreover, by implementing both dynamic and static Wear Leveling algorithms, the life expectancy of the NAND Flash is greatly improved. 1.2.3. Bad Block Management Bad blocks are blocks that include one or more invalid bits, and their reliability is not guaranteed. Blocks that are identified and marked as bad by the manufacturer are referred to as "Initial Bad Blocks". Bad blocks that are developed during the lifespan of the flash are named "Later Bad Blocks". Delkin's SD 3.0 controller implements an efficient bad block management algorithm to detect the factory-produced bad blocks and manages any bad blocks that develop with use. This practice further prevents data being stored into bad blocks and improves the data reliability. 1.2.4. Smart Function SMART, an acronym for Self-Monitoring, Analysis and Reporting Technology, is a special function that allows a memory device to automatically monitor its health. Delkin provides a dashboard to observe Utility SD and microSD cards. Note that this tool can only support Delkin Utility or Industrial SD and microSD cards which are SMART-enabled and contain specific controllers. This dashboard will display the controller version, flash type, firmware version, endurance life ratio, good block ratio, and so forth. In addition, a warning message will appear under the following 3 conditions: (1) When the life ratio remaining is less than 10%, (c) 2020 | Delkin Devices Inc. 7 Utility pSLC SD L500693 Rev. CV (2) When the quantity of abnormal power on cycles is more than 3,500, and (3) When there are less than 5 usable blocks for replacing bad blocks. 1.2.5. Auto-Read Refresh Auto-Read Refresh is especially applied on devices that mostly read data but rarely write data, GPS systems, for example. When blocks are continuously read, then the device cannot activate wear leveling since it is only applied while writing data. Thus, errors can accumulate and become uncorrectable. Therefore, to avoid the accumulation of errors that exceed the quantity correctable by the controller's ECC, which would result in bad blocks, Delkin's controller firmware will automatically refresh the bit errors when the error number in one block approaches the threshold, ex., 24 bits. 1.2.6. Embedded Mode Embedded mode is a function specially designed for Linux or customized OS use. Often under nonWindows OS, the default FAT system will not be used. In this case, the wear leveling mechanism of the SD cards will be affected, or even disabled in some cases. Embedded mode ensures that under any circumstances, the wear leveling mechanism will be activated, to keep the usage of blocks even throughout the card's life cycle. Embedded Mode is standard on the cards covered by this document. 1.2.7. PseudoSLC (pSLC) PseudoSLC (or pSLC) is considered an extended version of MLC, wherein standard MLC contains both fast and slow pages, pSLC only programs the fast pages. The concept of pSLC is demonstrated in the two tables below. The first and second bits of an MLC memory cell represent a fast and slow page respectively, as shown in the left table. Since only the fast pages are programmed in pSLC mode, the bits highlighted in red are used, as shown in the right table. As such, because only the fast pages are programmed, pSLC delivers better performance and endurance than standard MLC, yet is more cost effective than SLC. (c) 2020 | Delkin Devices Inc. 8 Utility pSLC SD L500693 Rev. CV 2. PRODUCT SPECIFICATION OVERVIEW Capacity 4GB up to 64GB pSLC Operation Temp. Range -25 ~ +85C Storage Temp. Range -40 ~ +85C Support SD system specification version 3.0 Card capacity of non-secure area and secure area support [Part 3 Security Specification Ver3.0 Final] Specifications Supports SD & SPI mode Designed for read-only and read/write cards Bus Speed Mode (use 4 parallel data lines) UHS-I mode SDR12: SDR up to 25MHz, 1.8V signaling SDR25: SDR up to 50MHz, 1.8V signaling SDR50: 1.8V signaling, frequency up to 100MHz, up to 50MB/sec DDR50: 1.8V signaling, frequency up to 50MHz, sampled on both clock edges, up to 50MB/sec Note: Timing in 1.8V signaling is different from that of 3.3V signaling. The command list supports [Part 1 Physical Layer Specification Ver3.01 Final] definitions Copyright Protection Mechanism Compliant with the highest security of SDMI standard Supports CPRM (Content Protection for Recordable Media) of SD Card Card removal during read operation will never harm the content Password Protection of cards (optional) Write Protect feature using mechanical switch Built-in write protection features (permanent and temporary) +4KV/-4KV ESD protection in contact pads Operation voltage range: 2.7 ~ 3.6V (c) 2020 | Delkin Devices Inc. 9 Utility pSLC SD L500693 Rev. CV 2.1. Performance Sequential Capacity Mode Read Write (MB/s) (MB/s) 4GB UHS-I 90 45 8GB UHS-I 95 80 16GB UHS-I 95 90 32GB UHS-I 95 90 64GB UHS-I 95 90 NOTES: 1. Benchmark performance measured with TestMetrix Test (@500MB). 2.2. Part Numbers Utility pSLC SD (c) 2020 | Delkin Devices Inc. Capacity Part Number 4GB SF04APG47-U3000-3 8GB SF08ANZ47-U3000-3 16GB TBD 32GB SF32ANZ73-U3000-3 64GB SF64ANZ73-U3000-3 10 Utility pSLC SD L500693 Rev. CV 3. ENVIRONMENTAL SPECIFICATIONS 3.1. Environmental Conditions 3.1.1. Temperature and Humidity Storage Temperature Range -40C ~ +85C Operation Temperature Range -25C ~ +85C Humidity 95% RH under 40C 3.1.2. Shock & Vibration Shock Specification 1500G, 0.5ms duration, 3 axes Vibration Specification 20Hz ~80Hz/1.52mm displacement, 80Hz~2000Hz / 20G Acceleration, 3 axes 3.1.3. Durability Mating Cycles 10,000 mating cycles 3.1.4. Electrostatic Discharge (ESD) Contact 4KV Air 8KV 3.1.5. EMI Compliance FCC: CISPR22 CE: EN55022 BSMI 13438 3.2. MTBF MTBF, an acronym for Mean Time Between Failures, is a measure of a device's reliability. Its value represents the average time between a repair and the next failure. The measure is typically in units of hours. The higher the MTBF value, the higher the reliability of the device. The predicted result of Delkin's Utility SD is more than 3,000,000 hours at temperatures up to 25C. (c) 2020 | Delkin Devices Inc. 11 Utility pSLC SD L500693 Rev. CV 4. SD CARD COMPARISON Table 4-1 Comparing SD3.0 Standard, SD3.0 SDHC, SDXC SD3.0 Standard (Backward compatible to 2.0 host) Byte (1 byte unit) SD3.0 SDHC (Backward compatible to 2.0 host) Block (512 byte unit) Block (512 byte unit) HCS/CCS bits of ACMD41 Supported Supported Supported CMD8 (SEND_IF_COND) Supported Supported Supported CMD16 (SET_BLOCKLEN) Supported Supported (Only CMD42) Supported (Only CMD42) Partial Read Supported Not Supported Not Supported Lock/Unlock Function Write Protect Groups Supply Voltage 2.0v - 2.7v (for initialization) Total Bus Capacitance for each signal line CSD Version (CSD_STRUCTURE Value) Mandatory Optional Mandatory Not Supported Mandatory Not Supported Not Supported Not Supported Not Supported 40pF 40pF 40pF 1.0 (0x0) 2.0 (0x1) 2.0 (0x1) Optional Mandatory (Class 2 / 4 / 6 / 10) Mandatory (Class 2 / 4 / 6 / 10) Addressing Mode Speed Class (c) 2020 | Delkin Devices Inc. SD3.0 SDXC 12 Utility pSLC SD L500693 Rev. CV 5. ELECTRICAL SPECIFICATIONS 5.1. Power Consumption The table below is the power consumption of Delkin Utility pSLC SD by capacity. Table 5-1 Power Consumption by Capacity (Maximum) Capacity Read (mA) Write (mA) Idle (uA) 4GB 400 400 1000 8GB 400 400 1000 16GB 400 400 1000 32GB 400 400 1000 64GB 400 400 1000 NOTE: 1. Data transfer mode is single channel. 2. Power Consumption shown is maximum and will vary by usage model, SDR configuration, or platform. 5.2. DC Characteristic 5.2.1. Bus Operation Conditions for 3.3V Signaling Table 5-2 Threshold Level for High Voltage Range Parameter Symbol Min. Max Unit Supply Voltage VDD 2.7 3.6 V Output High Voltage VOH 0.75*VDD Output Low Voltage VOL Input High Voltage VIH Input Low Voltage VIL Power Up Time (c) 2020 | Delkin Devices Inc. V 0.125*VDD V 0.625*VDD VDD+0.3 V VSS-0.3 0.25*VDD V 250 Ms Condition IOH=-2mA VDD Min IOL=2mA VDD Min From 0V to VDD min 13 Utility pSLC SD L500693 Rev. CV Table 5-3 Peak Voltage and Leakage Current Parameter Symbol Peak voltage on all lines Min Max. Unit -0.3 VDD+0.3 V 10 uA 10 uA Remarks All Inputs Input Leakage Current -10 All Outputs Output Leakage -10 Current Table 5-4 Threshold Level for 1.8V Signaling Parameter Symbol Min. Max Unit VDD 2.7 3.6 V VDDIO 1.7 1.95 V Output High Voltage VOH 1.4 - V IOH=-2mA Output Low Voltage VOL - 0.45 V IOL=2mA Input High Voltage VIH 1.27 2.00 V Input Low Voltage VIL Vss-0.3 0.58 V Supply Voltage Regulator Voltage Condition Generated by VDD Table 5-5 Input Leakage Current for 1.8V Signaling Parameter Input Leakage Current (c) 2020 | Delkin Devices Inc. Symbol Min Max. Unit -2 2 uA Remarks DAT3 pull-up is disconnected. 14 Utility pSLC SD L500693 Rev. CV 5.2.2. Bus Signal Line Load Figure 5-1 Bus Circuitry Diagram Bus Operation Conditions - Signal Line's Load Total Bus Capacitance = CHOST + CBUS + N Parameter Pull-up resistance Total bus capacitance for each signal line Card Capacitance for each signal pin symbol RCMD RDAT CCARD Mi n 10 CL Line (c) 2020 | Delkin Devices Inc. Remark 100 k to prevent bus floating 40 pF CHOST+CBUS shall not exceed 30 pF CCARD RDAT3 (pin1) Capacity Connected to Power Unit 1 card Maximum signal line inductance Pull-up resistance inside card Max CC 10 10 pF 16 nH 90 k 5 uF May be used for card detection To prevent inrush current 15 Utility pSLC SD L500693 Rev. CV 5.2.3. Power Up Time Host needs to keep power line level less than 0.5V and more than 1ms before power ramp up. Power On or Power Cycle Followings are requirements for Power on and Power cycle to assure a reliable SD Card hard reset. (1) Voltage level shall be below 0.5V. (2) Duration shall be at least 1ms. Power Supply Ramp Up The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage which is stable between VDD (min.) and VDD (max.) and host can supply SDCLK. Followings are recommendations of Power ramp up: (1) Voltage of power ramp up should be monotonic as much as possible. (2) The minimum ramp up time should be 0.1ms. (3) The maximum ramp up time should be 35ms for 2.7-3.6V power supply. Power Down and Power Cycle (1) When the host shuts down the power, the card VDD shall be lowered to less than 0.5Volt for a minimum period of 1ms. During power down, DAT, CMD, and CLK should be disconnected or driven to logical 0 by the host to avoid a situation that the operating current is drawn through the signal lines. (2) If the host needs to change the operating voltage, a power cycle is required. Power cycle means the power is turned off and supplied again. Power cycle is also needed for accessing cards that are already in Inactive State. To create a power cycle the host shall follow the power down description before power up the card (i.e. the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms). (c) 2020 | Delkin Devices Inc. 16 Utility pSLC SD L500693 Rev. CV 5.3. AC Characteristic 5.3.1. SD Interface Timing (Default) (c) 2020 | Delkin Devices Inc. 17 Utility pSLC SD L500693 Rev. CV Parameter Symbol Min Max Unit Clock CLK (All values are referred to min(VIH) and max(VIL) Clock frequency Data Transfer Mode fPP 0 25 MHz 400 kHz Clock frequency Identification Mode fOD 0(1)/100 Clock low time tWL 10 ns Clock high time tWH 10 ns Clock rise time tTLH 10 ns Clock fall time tTHL 10 ns Remark Ccard 10 pF (1 card) Ccard 10 pF (1 card) Ccard 10 pF (1 card) Ccard 10 pF (1 card) Ccard 10 pF (1 card) Ccard 10 pF (1 card) Inputs CMD, DAT (referenced to CLK) Input set-up time tISU 5 ns Input hold time tIH 5 ns Outputs CMD, DAT (referenced to CLK) Output Delay time during Data tODLY 0 14 Transfer Mode Output Delay time during tODLY 0 50 Identification Mode ns ns Ccard 10 pF (1 card) Ccard 10 pF (1 card) CL40 pF (1 card) CL40 pF (1 card) (1) 0Hz means to stop the clock. The given minimum frequency range is for cases where continuous clock is required. 5.3.2. SD Interface Timing (High-Speed Mode) (c) 2020 | Delkin Devices Inc. 18 Utility pSLC SD L500693 Rev. CV Parameter Symbol Min Max Unit Remark Clock CLK (All values are referred to min(VIH) and max(VIL) Clock frequency Data Transfer fPP Ccard 10 pF 0 50 MHz Mode (1 card) Ccard 10 pF Clock low time tWL 7 ns (1 card) Ccard 10 pF Clock high time tWH 7 ns (1 card) Ccard 10 pF Clock rise time tTLH 3 ns (1 card) Ccard 10 pF Clock fall time tTHL 3 ns (1 card) Inputs CMD, DAT (referenced to CLK) Ccard 10 pF Input set-up time tISU 6 ns (1 card) Ccard 10 pF Input hold time tIH 2 ns (1 card) Outputs CMD, DAT (referenced to CLK) Output Delay time during Data CL 40 pF tODLY 14 ns Transfer Mode (1 card) CL 15 pF Output Hold time TOH 2.5 ns (1 card) Total System capacitance of CL 15 pF CL 40 pF each line (1 card) (1) In order to satisfy severe timing, the host shall drive only one card. (c) 2020 | Delkin Devices Inc. 19 Utility pSLC SD L500693 Rev. CV 5.3.3. SD Interface Timing (SDR12, SDR25 and SDR50 Modes) Input Table 5-6 Clock Signal Timing Symbol Min Max Unit tCLK 4.80 - ns tCR, tCF - 0.2* tCLK ns 30 70 % Clock Duty Remark 208MHz (Max.), Between rising edge, VCT= 0.975V tCR, tCF < 2.00ns (max.) at 100MHz, CCARD=10pF SDR50 Input Timing Symbol tIs tIH Symbol tIs tIH Min 1.40 0.80 Min 3.00 0.80 (c) 2020 | Delkin Devices Inc. Max Max - Unit ns ns Unit ns ns SDR104 Mode CCARD =10pF, VCT= 0.975V CCARD =5pF, VCT= 0.975V SDR50 Mode CCARD =10pF, VCT= 0.975V CCARD =5pF, VCT= 0.975V 20 Utility pSLC SD L500693 Rev. CV Output Table 5-7 Output Timing of Fixed Data Window (SDR12, SDR25, SDR50 Modes) Symbol Min tODLY - 7.5 ns tODLY - 14 ns TOH 1.5 - ns Symbol tOP tOP tODW Min 0 -350 0.60 (c) 2020 | Delkin Devices Inc. Max Max 2 +1550 - Unit Remark tCLK>=10.0ns, CL=30pF, using driver Type B, for SDR50 tCLK>=20.0ns, CL=40pF, using driver Type B, for SDR25 and SDR12, Hold time at the tODLY (min.), CL=15pF Unit Remark Ul Card Output Phase ps Delay variable due to temperature change after tuning Ul tODW = 2.88ns at 208MHz 21 Utility pSLC SD L500693 Rev. CV 5.3.4. SD Interface Timing (DDR50 Mode) Symbol Min Max Unit Remark tCLK 20 - ns 50MHz (Max.), Between rising edge tCR, tCF - 0.2* tCLK ns tCR, tCF < 4.00ns (max.) at 50MHz, CCARD=10pF Clock Duty 45 55 % (c) 2020 | Delkin Devices Inc. 22 Utility pSLC SD L500693 Rev. CV Table 5-8 Bus Timings - Parameters Values (DDR50 Mode) Parameter Symbol Min Max Unit Input CMD (referenced to CLK rising edge) Input set-up time tISU 6 - ns Input hold time tIH 0.8 - ns Output CMD (referenced to CLK rising edge) Output Delay time during Data tODLY 13.7 ns Transfer Mode Output Hold time TOH 1.5 - ns Remark Ccard 10 pF (1 card) Ccard 10 pF (1 card) CL30 pF (1 card) CL15 pF (1 card) Inputs DAT (referenced to CLK rising and falling edges) Input set-up time tISU2x 3 - ns Input hold time tIH2x 0.8 - ns Outputs DAT (referenced to CLK rising and falling edges) Output Delay time during Data tODLY2x 7.0 ns Transfer Mode Output Hold time (c) 2020 | Delkin Devices Inc. TOH2x 1.5 - ns Ccard 10 pF (1 card) Ccard 10 pF (1 card) CL25 pF (1 card) CL15 pF (1 card) 23 Utility pSLC SD L500693 Rev. CV 6. INTERFACE 6.1. Pad Assignment and Descriptions Table 6-1 SD Memory Card Pad Assignment pin SD Mode SPI Mode Name Type 1 Description CD/DAT3 I/O/PP Card Detect/ 2 3 Data Line[bit3] 2 CMD PP 3 VSS1 4 Name Type Description CS I3 Chip Select (net true) Command/Response DI I Data In S Supply voltage ground VSS S Supply voltage ground VDD S Supply voltage VDD S Supply voltage 5 CLK I Clock SCLK I Clock 6 VSS2 S Supply voltage ground VSS2 S Supply voltage ground 7 DAT0 I/O/PP Data Line[bit0] DO O/PP Data Out 8 DAT1 I/O/PP Data Line[bit1] RSV 9 DAT2 I/O/PP Data Line[bit2] RSV 1 (1) S: power supply, I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers. (2) The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode as well while they are not used. It is defined so in order to keep compatibility to MultiMedia Cards. (3) At power up, this line has a 50KOhm pull up enabled in the card. This resistor serves two functions: Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled high to select SD mode. If the host wants to select SPI mode, it should drive the line low. For Card detection, the host detects that the line is pulled high. This pull-up should be disconnected by the user during regular data transfer with SET_CLR_CARD_DETECT (ACMD42) command. (c) 2020 | Delkin Devices Inc. 24 Utility pSLC SD L500693 Rev. CV Name Width CID 128bit Description Card identification number; card individual number for identification. Mandatory Relative card address; local system address of a card, dynamically RCA1 16bit suggested by the card and approved by the host during initialization. Mandatory DSR 16bit CSD 128bit SCR 64bit OCR 32bit SSR 512bit OCR 32bit Driver Stage Register; to configure the card's output drivers. Optional Card Specific Data; information about the card operation conditions. Mandatory SD Configuration Register; information about the SD Memory Card's Special Features capabilities Mandatory Operation conditions register. Mandatory. SD Status; information about the card proprietary features Mandatory Card Status; information about the card status Mandatory (1) RCA register is not used (or available) in SPI mode. (c) 2020 | Delkin Devices Inc. 25 Utility pSLC SD L500693 Rev. CV 7. PHYSICAL DIMENSIONS Dimension Value Length 32mm 0.1mm Width 24mm 0.1mm Thickness 2.1mm 0.1mm Refer to SD Association standards for further dimensional details. https://www.sdcard.org/ WARNING: This product may contain chemicals known to the State of California to cause cancer, birth defects, or other reproductive harm. For more information go to www.p65warnings.ca.gov. (c) 2020 | Delkin Devices Inc. 26