MAX19710ETN - Maxim Integrated Products, Inc.

General Description

The MAX19710 is an ultra-low-power, highly integrated

mixed-signal analog front-end (AFE) ideal for wideband

communication applications operating in full-duplex (FD)

mode. Optimized for high dynamic performance and

ultra-low power, the device integrates a dual 10-bit,

7.5Msps receive (Rx) ADC; dual 10-bit, 7.5Msps transmit

(Tx) DAC; three fast-settling 12-bit aux-DAC channels for

ancillary RF front-end control; and a 10-bit, 333ksps

housekeeping aux-ADC. The typical operating power in

FD mode is 30mW at a 7.5MHz clock frequency.

The Rx ADCs feature 54.8dB SINAD and 79.8dBc SFDR

at 3.3MHz input frequency with a 7.5MHz clock frequen-

cy. The analog I/Q input amplifiers are fully differential

and accept 1.024VP-P full-scale signals. Typical I/Q

channel matching is ±0.01° phase and ±0.01dB gain.

The Tx DACs feature 73.8dBc SFDR at fOUT = 620kHz

and fCLK = 7.5MHz. The analog I-Q full-scale output volt-

age range is ±400mV differential. The output DC com-

mon-mode voltage is from 0.89V to 1.36V. The I/Q

channel offset is adjustable to optimize radio lineup side-

band/carrier suppression. Typical I-Q channel matching

is ±0.01dB gain and ±0.15° phase.

Two independent 10-bit parallel, high-speed digital

buses used by the Rx ADC and Tx DAC allow full-

duplex operation for frequency-division duplex applica-

tions. The Rx ADC and Tx DAC can be disabled

independently to optimize power management. A 3-wire

serial interface controls power-management modes, the

aux-DAC channels, and the aux-ADC channels.

The MAX19710 operates on a single 2.7V to 3.3V analog

supply and 1.8V to 3.3V digital I/O supply. The

MAX19710 is specified for the extended (-40°C to

+85°C) temperature range and is available in a 56-pin,

thin QFN package. The

Selector Guide

at the end of the

data sheet lists other pin-compatible versions in this AFE

family. For time-division duplex (TDD) applications, refer

to the MAX19705–MAX19708 AFE family of products.

Applications

Features

♦Dual 10-Bit, 7.5Msps Rx ADC and Dual 10-Bit,

7.5Msps Tx DAC

♦Ultra-Low Power

30mW at fCLK = 7.5MHz, FD Mode

21.3mW at fCLK = 7.5MHz, Slow Rx Mode

21.9mW at fCLK = 7.5MHz, Slow Tx Mode

Low-Current Standby and Shutdown Modes

♦Programmable Tx DAC Common-Mode DC Level

and I/Q Offset Trim

♦Excellent Dynamic Performance

SNR = 54.9dB at fIN = 3.3MHz (Rx ADC)

SFDR = 73.8dBc at fOUT = 620kHz (Tx DAC)

♦Three 12-Bit, 1μs Aux-DACs

♦10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and

Data Averaging

♦Excellent Gain/Phase Match

±0.01° Phase, ±0.01dB Gain (Rx ADC) at

fIN = 1.8MHz

♦Multiplexed Parallel Digital I/O

♦Serial-Interface Control

♦Versatile Power-Control Circuits

Shutdown, Standby, Idle, Tx/Rx Disable

♦Miniature 56-Pin Thin QFN Package

(7mm x 7mm x 0.8mm)

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

________________________________________________________________

Maxim Integrated Products

19-0526; Rev 0; 5/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

PART* PIN-PACKAGE PKG CODE

MAX19710ETN 56 Thin QFN-EP** T5677-1

MAX19710ETN+ 56 Thin QFN-EP** T5677-1

All devices are specified over the -40°C to +85°C operating range.

EP = Exposed paddle.

Denotes lead-free package.

Functional Diagram and Selector Guide appear at end of

data sheet.

TOP VIEW

MAX19710

THIN QFN

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

OGND

OVDD

DA0

DA1

DA2

DA3

REFN

NOTE: THE PIN 1 INDICATOR IS “+” FOR LEAD-FREE DEVICES.

COM

REFIN

QDP

QDN

VDD

GND

IDP

IDN

VDD

DAC1

DAC2

DAC3

ADC1

1 2 3 4 5 6 7 8 9 1011121314

42 41 40 39 38 37 36 35 34 33 32 31 30 29

GND

AD0

AD1

VDD

QAP

QAN

VDD

GND

CLK

GND

IAN

IAP

VDD

REFP

DA6

DA5

DA4

DA7

DA8

DA9

DOUT

DIN

SCLK

VDD

GND

VDD

ADC2

EXPOSED PADDLE (GND)

CS/WAKE

Pin Configuration

Broadband Access

Radio

Private Mobile Radio

Portable Communication

Equipment

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V

GND to OGND.......................................................-0.3V to +0.3V

IAP, IAN, QAP, QAN, IDP, IDN, QDP,

QDN, DAC1, DAC2, DAC3 to GND .....................-0.3V to VDD

ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V)

REFP, REFN, REFIN, COM to GND ...........-0.3V to (VDD + 0.3V)

AD0–AD9, DA0–DA9, SCLK, DIN, CS/WAKE,

CLK, DOUT to OGND .........................-0.3V to (OVDD + 0.3V)

Continuous Power Dissipation (TA= +70°C)

56-Pin Thin QFN-EP (derate 27.8mW/°C above +70°C)2.22W

Thermal Resistance θJA ..................................................36°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

ELECTRICAL CHARACTERISTICS

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,

CREFP = CREFN = CCOM = 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMIN to TMAX, unless otherwise noted. Typical values are at

TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER REQUIREMENTS

Analog Supply Voltage VDD 2.7 3.0 3.3 V

Output Supply Voltage OVDD 1.8 VDD V

FD mode: fCLK = 7.5MHz, fOUT = 620kHz

on both DAC channels;

fIN = 1.875MHz on both ADC channels;

aux-DACs ON and at midscale, aux-ADC

10 12

SPI2-Tx mode: fCLK = 7.5MHz, fOUT =

620kHz on both DAC channels; Rx ADC

OFF; aux-DACs ON and at midscale, aux-

ADC ON

7.3 9

SPI1-Rx mode: fCLK = 7.5MHz, fIN =

1.875MHz on both ADC channels; Tx DAC

OFF (Tx DAC outputs at 0V); aux-DACs

ON and at midscale, aux-ADC ON

7.1 9

VDD Supply Current

SPI4-Tx mode: fCLK = 7.5MHz, fOUT =

620kHz on both DAC channels; Rx ADC

ON (output tri-stated); aux-DACs ON and

at midscale, aux-ADC ON

9.7 12

MAX19710

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,

CREFP = CREFN = CCOM = 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMIN to TMAX, unless otherwise noted. Typical values are at

TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SPI3-Rx mode: fCLK = 7.5MHz, fIN =

1.875MHz on both channels; Tx DAC ON

(Tx DAC outputs at midscale); aux-DACs

ON and at midscale, aux-ADC ON

9.5 12

Standby mode: CLK = 0 or OVDD;

aux-DACs ON and at midscale,

aux-ADC ON

2.7 3.5

Idle mode: fCLK = 7.5MHz; aux-DACs ON

and at midscale, aux-ADC ON 4.6 6

VDD Supply Current

Shutdown mode: CLK = 0 or OVDD, or

aux-ADC OFF 0.5 5 µA

FD mode: fCLK = 7.5MHz, fOUT = 620kHz

on both DAC channels; fIN = 1.875MHz on

both ADC channels; aux-DACs ON and at

midscale, aux-ADC ON

0.94

SPI1-Rx and SPI3-Rx modes: fCLK =

7.5MHz, fIN = 1.875MHz on both ADC

channels; DAC input bus tri-stated; aux-

DACs ON and at midscale, aux-ADC ON

0.90

SPI2-Tx and SPI4-Tx modes: fCLK =

7.5MHz, fOUT = 620kHz on both DAC

channels; ADC output bus tri-stated; aux-

DACs ON and at midscale, aux-ADC ON

Standby mode: CLK = 0 or OVDD; aux-

DACs ON and at midscale, aux-ADC ON 0.1

Idle mode: fCLK = 7.5MHz; aux-DACs ON

and at midscale, aux-ADC ON 12.8

OVDD Supply Current

Shutdown mode: CLK = 0 or OVDD, or

aux-ADC OFF 0.1

µA

Rx ADC DC ACCURACY

Resolution N 10 Bits

Integral Nonlinearity INL ±0.5 LSB

Differential Nonlinearity DNL N o m i ssi ng cod es over tem p er atur e ( N ote 2) -0.8 ±0.4 +1.0 LSB

Offset Error Residual DC offset error -5 ±0.2 +5 %FS

Gain Error Includes reference error -5 ±0.9 +5 %FS

DC Gain Matching -0.15 ±0.04 +0.15 dB

Offset Matching ±11 LSB

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

_______________________________________________________________________________________ 3

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,

CREFP = CREFN = CCOM = 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMIN to TMAX, unless otherwise noted. Typical values are at

TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Gain Temperature Coefficient ±30 ppm/°C

Offset (VDD ±5%) ±0.2

Power-Supply Rejection PSRR Gain (VDD ±5%) ±0.05 LSB

Rx ADC ANALOG INPUT

Input Differential Range VID Differential or single-ended inputs ±0.512 V

Input Common-Mode Voltage

Range VCM VDD / 2 V

RIN Switched capacitor load 720 kΩ

Input Impedance CIN 5pF

Rx ADC CONVERSION RATE

Maximum Clock Frequency fCLK (Note 3) 7.5 MHz

Channel IA 5

Data Latency Channel QA 5.5

Clock

Cycles

Rx ADC DYNAMIC CHARACTERISTICS (Note 4)

fIN = 1.875MHz 53.2 54.8

Signal-to-Noise Ratio SNR fIN = 3.3MHz 54.9 dB

fIN = 1.875MHz 53.1 54.7

Signal-to-Noise and Distortion SINAD fIN = 3.3MHz 54.8 dB

fIN = 1.875MHz 64.2 73.9

Spurious-Free Dynamic Range SFDR fIN = 3.3MHz 79.8 dBc

fIN = 1.875MHz -71.7 -62.8

Total Harmonic Distortion THD fIN = 3.3MHz -74.3 dBc

fIN = 1.875MHz -76.8

Third-Harmonic Distortion HD3 fIN = 3.3MHz -83.8 dBc

Intermodulation Distortion IMD fIN1 = 1.8MHz, AIN1 = -7dBFS;

fIN2 = 1MHz, AIN2 = -7dBFS -72 dBc

Third-Order Intermodulation

Distortion IM3 fIN1 = 1.8MHz, AIN1 = -7dBFS;

fIN2 = 1MHz, AIN2 = -7dBFS -83 dBc

Aperture Delay 3.5 ns

Aperture Jitter 2ps

RMS

Overdrive Recovery Time 1.5x full-scale input 2 ns

Rx ADC INTERCHANNEL CHARACTERISTICS

Crosstalk Rejection fIN X ,Y

= 1.8M H z, AIN X ,Y

= - 0.5d BFS , fIN Y ,X

1M H z, AIN Y ,X

= - 0.5d BFS ( N ote 5) -91 dB

Amplitude Matching fIN

= 1.8MHz, AIN

= -0.5dBFS (Note 6) ±0.01 dB

Phase Matching fIN

= 1.8MHz, AIN

= -0.5dBFS (Note 6) ±0.01 D eg r ees

MAX19710

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,

CREFP = CREFN = CCOM = 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMIN to TMAX, unless otherwise noted. Typical values are at

TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Tx DAC DC ACCURACY

Resolution N 10 Bits

Integral Nonlinearity INL ±0.3 LSB

Differential Nonlinearity DNL Guaranteed monotonic (Note 2) -0.75 ±0.2 +0.75 LSB

Residual DC Offset VOS -4 ±1.2 +4 mV

Full-Scale Gain Error -40 ±1.6 +40 mV

Tx DAC DYNAMIC PERFORMANCE

DAC Conversion Rate fCLK (Note 3) 7.5 MHz

In-Band Noise Density NDfOUT = 620kHz -120 dBFS/Hz

Third-Order Intermodulation

Distortion IM3 fOUT1 = 620kHz, fOUT2 = 640kHz -79 dBc

Glitch Impulse 10 pV•s

Spurious-Free Dynamic Range to

Nyquist SFDR fOUT = 620kHz 61 73.8 dBc

Total Harmonic Distortion to

Nyquist THD fOUT = 620kHz -72.2 -59.7 dBc

Signal-to-Noise Ratio to Nyquist SNR fOUT = 620kHz 55.1 dB

Tx DAC INTERCHANNEL CHARACTERISTICS

I-to-Q Output Isolation fOUTX,Y = 2MHz, fOUTY,X = 2.2MHz 92 dB

Gain Mismatch Between I and Q

Channels Measured at DC -0.4 ±0.01 +0.4 dB

Phase Mismatch Between I and Q

Channels fOUT = 620kHz ±0.15 D eg r ees

Differential Output Impedance 800 Ω

Tx DAC ANALOG OUTPUT

Full-Scale Output Voltage VFS ±400 mV

Bits CM1 = 0, CM0 = 0 (default) 1.29 1.36 1.42

Bits CM1 = 0, CM0 = 1 1.14 1.2 1.27

Bits CM1 = 1, CM0 = 0 0.96 1.05 1.15

Output Common-Mode Voltage VCOMD

Bits CM1 = 1, CM0 = 1 0.78 0.89 1.03

Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICS

Receive Transmit Isolation ADC fINI = fINQ = 1.8MHz, DAC fOUTI =

fOUTQ = 620kHz 92 dB

AUXILIARY ADCs (ADC1, ADC2)

Resolution N 10 Bits

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

_______________________________________________________________________________________ 5

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,

CREFP = CREFN = CCOM = 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMIN to TMAX, unless otherwise noted. Typical values are at

TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AD1 = 0 (default) 2.048

Full-Scale Reference VREF AD1 = 1 VDD

Analog Input Range 0 to

VREF V

Analog Input Impedance Measured at DC 500 kΩ

Input-Leakage Current Measured at unselected input from 0 to

VREF ±0.1 µA

Gain Error GE Includes reference error, AD1 = 0 -5 +5 %FS

Zero-Code Error ZE ±2 mV

Differential Nonlinearity DNL ±0.6 LSB

Integral Nonlinearity INL ±0.6 LSB

Supply Current 210 µA

AUXILIARY DACs (DAC1, DAC2, DAC3)

Resolution N 12 Bits

Integral Nonlinearity INL From code 100 to code 4000 ±1.25 LSB

Differential Nonlinearity DNL Guaranteed monotonic over code 100 to

code 4000 (Note 2) -1.0 ±0.65 +1.2 LSB

Output-Voltage Low VOL RL > 200kΩ0.2 V

Output-Voltage High VOH RL > 200kΩ2.57 V

DC Output Impedance DC output at midscale 4 Ω

Settling Time From code 1024 to code 3072, within ±10

LSB 1µs

Glitch Impulse From code 0 to code 4095 24 nV•s

Rx ADC–Tx DAC TIMING CHARACTERISTICS

CLK Rise to Channel-I Output Data

Valid tDOI Figure 3 (Note 2) 5.5 8.2 11.5 ns

CLK Fall to Channel-Q Output

Data Valid tDOQ Figure 3 (Note 2) 6.5 9.3 13.0 ns

I-DAC DATA to CLK Fall Setup

Time tDSI Figure 5 (Note 2) 10 ns

Q-DAC DATA to CLK Rise Setup

Time tDSQ Figure 5 (Note 2) 10 ns

CLK Fall to I-DAC Data Hold Time tDHI Figure 5 (Note 2) 0 ns

CLK Rise to Q-DAC Data Hold

Time tDHQ Figure 5 (Note 2) 0 ns

CLK Duty Cycle 50 %

CLK Duty-Cycle Variation ±15 %

Digital Output Rise/Fall Time 20% to 80% 2.4 ns

MAX19710

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,

CREFP = CREFN = CCOM = 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMIN to TMAX, unless otherwise noted. Typical values are at

TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 6 and 8, Note 2)

Falling Edge of CS/WAKE to Rising

Edge of First SCLK Time tCSS 10 ns

DIN to SCLK Setup Time tDS 10 ns

DIN to SCLK Hold Time tDH 0ns

SCLK Pulse-Width High tCH 25 ns

SCLK Pulse-Width Low tCL 25 ns

SCLK Period tCP 50 ns

SCLK to CS/WAKE Setup Time tCS 10 ns

CS/WAKE High Pulse Width tCSW 80 ns

CS/WAKE High to DOUT

Active High tCSD Bit AD0 set 200 ns

CS/WAKE High to DOUT Low

(Aux-ADC Conversion Time) tCONV Bit AD0 set, no averaging, fCLK = 7.5MHz,

CLK divider = 2 4.3 µs

DOUT Low to CS/WAKE

Setup Time tDCS Bit AD0, AD10 set 200 ns

SCLK Low to DOUT Data Out tCD Bit AD0, AD10 set 14.5 ns

CS/WAKE High to DOUT High

Impedance tCHZ Bit AD0, AD10 set 200 ns

MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)

From shutdown to Rx mode, ADC settles

to within 1dB SINAD 500

From shutdown to Tx mode, DAC settles to

within 10 LSB error 26.2

From aux-ADC enable to aux-ADC start

conversion 10

From shutdown to aux-DAC output valid 28

Shutdown Wake-Up Time

(With CLK) tWAKE

From shutdown to FD mode, ADC settles

to within 1dB SINAD, DAC settles to within

10 LSB error

500

µs

Fr om i d l e to Rx m od e, AD C settl es to w i thi n

1d B S IN AD 7.3

From idle to Tx mode, DAC settles to 10

LSB error 5.2

Idle Wake-Up Time

(With CLK) tWAKE

ST0

From idle to FD mode, ADC settles to

within 1dB SINAD, DAC settles to within 10

LSB error

7.3

µs

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

_______________________________________________________________________________________ 7

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

8 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,

CREFP = CREFN = CCOM = 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMIN to TMAX, unless otherwise noted. Typical values are at

TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

From standby to Rx mode, ADC settles to

within 1dB SINAD 7.5

From standby to Tx mode, DAC settles to

10 LSB error 22.2

Standby Wake-Up Time

(With CLK) tWAKE

ST1

From standby to FD mode, ADC settles to

within 1dB SINAD, DAC settles to within 10

LSB error

22.2

µs

Enable Time from Tx to Rx,

Fast Mode tENABLE

RX ADC settles to within 1dB SINAD 0.1 µs

E nab l e Ti m e fr om Rx to Tx,

Fast M od etENABLE

TX DAC settles to within 10 LSB error 0.1 µs

Enable Time from Tx to Rx,

Slow Mode tENABLE

RX ADC settles to within 1dB SINAD 7.3 µs

E nab l e Ti m e fr om Rx to Tx,

S l ow M od etENABLE

TX DAC settles to within 10 LSB error 5.2 µs

INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally)

Positive Reference VREFP - VCOM 0.256 V

Negative Reference VREFN - VCOM -0.256 V

Common-Mode Output Voltage VCOM VDD / 2

- 0.15 VDD / 2 VDD / 2

+ 0.15 V

Maximum REFP/REFN/COM

Source Current ISOURCE 2mA

Maximum REFP/REFN/COM

Sink Current ISINK 2mA

Differential Reference Output VREF VREFP - VREFN +0.490 +0.512 +0.534 V

Differential Reference Temperature

Coefficient REFTC ±30 ppm/°C

BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally)

Reference Input Voltage VREFIN 1.024 V

Differential Reference Output VDIFF VREFP - VREFN 0.512 V

Common-Mode Output Voltage VCOM VDD / 2 V

Maximum REFP/REFN/COM

Source Current ISOURCE 2mA

Maximum REFP/REFN/COM

Sink Current ISINK 2mA

REFIN Input Current -0.7 µA

REFIN Input Resistance 500 kΩ

MAX19710

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,

CREFP = CREFN = CCOM = 0.33µF, CL< 5pF on all aux-DAC outputs, TA= TMIN to TMAX, unless otherwise noted. Typical values are at

TA= +25°C.) (Note 1)

Note 1: Specifications from TA= +25°C to +85°C guaranteed by production tests. Specifications at TA< +25°C guaranteed by

design and characterization.

Note 2: Guaranteed by design and characterization.

Note 3: The minimum clock frequency (fCLK) for the MAX19710 is 1.5MHz (typ). The minimum aux-ADC sample rate clock frequency

(ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 1.5MHz / 128 =

11.7kHz. The aux-ADC conversion time does not include the time to clock the serial data out of DOUT. The maximum con-

version time (for no averaging, NAVG = 1) will be tCONV (max) = (12 x 1 x 128) / 1.5MHz = 1024µs.

Note 4: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude

of the digital outputs. SINAD and THD are calculated using HD2 through HD6.

Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-

ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second

channel FFT test tones.

Note 6: Amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output

signals using a sine-wave fit.

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

_______________________________________________________________________________________ 9

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (CLK, SCLK, DIN, CS/WAKE, DA9–DA0)

Input High Threshold VINH 0.7 x OVDD V

Input Low Threshold VINL 0.3 x OVDD V

CLK, SCLK, DIN, CS/WAKE = OGND or

OVDD -1 +1

DA9–DA0 = OVDD -1 +1

Input Leakage DIIN

DA9–DA0 = OGND -5 +5

µA

Input Capacitance DCIN 5pF

DIGITAL OUTPUTS (AD9–AD0, DOUT)

Output-Voltage Low VOL ISINK = 200µA 0.2 x OVDD V

Output-Voltage High VOH ISOURCE = 200µA 0.8 x OVDD V

Tri-State Leakage Current ILEAK -1 +1 µA

Tri-State Output Capacitance COUT 5pF

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

10 ______________________________________________________________________________________

Typical Operating Characteristics

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC

input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC

output, CREFP = CREFN = CCOM = 0.33µF, TA= +25°C, unless otherwise noted.)

Rx ADC CHANNEL-IA FFT PLOT

MAX19710 toc01

FREQUENCY (MHz)

AMPLITUDE (dBFS)

3.02.01.0

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

03.52.51.50.5

45362

fIN = 1.8019362MHz

AIN = -0.524dBFS

SINAD = 54.897dB

SNR = 54.927dB

THD = -76.609dBc

SFDR = 83.379dBc

FUNDAMENTAL

Rx ADC CHANNEL-QA FFT PLOT

MAX19710 toc02

FREQUENCY (MHz)

AMPLITUDE (dBFS)

3.02.01.0

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

03.52.51.50.5

fIN = 1.8019362MHz

AIN = -0.488dBFS

SINAD = 54.773dB

SNR = 54.83dB

THD = -73.651dBc

SFDR = 77.541dBc

FUNDAMENTAL

Rx ADC CHANNEL-IA

TWO-TONE FFT PLOT

MAX19710 toc03

FREQUENCY (MHz)

AMPLITUDE (dBFS)

3.02.01.0

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

03.52.51.50.5

fIN1

2fIN1 - fIN2 2fIN2 - fIN1

fIN2

fIN1 = 1.7471383MHz

fIN2 = 1.8421213MHz

AIN1 = AIN2 = -7dBFS

IMD = -64dBc

Rx ADC CHANNEL-QA

TWO-TONE FFT PLOT

MAX19710 toc04

FREQUENCY (MHz)

AMPLITUDE (dBFS)

3.02.01.0

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

03.52.51.50.5

2fIN1 - fIN2 2fIN2 - fIN1

fIN1 = 1.7471383MHz

fIN2 = 1.8421213MHz

AIN1 = AIN2 = -7dBFS

IMD = -64dBc

fIN2

fIN1

Rx ADC SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

MAX19710 toc05

0 102030405060708090100

Rx ADC SIGNAL-TO-NOISE AND DISTORTION

RATIO vs. ANALOG INPUT FREQUENCY

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

MAX19710 toc06

0 102030405060708090100

Rx ADC TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

ANALOG INPUT FREQUENCY (MHz)

-THD (dBc)

MAX19710 toc07

0 102030405060708090100

Rx ADC SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

ANALOG INPUT FREQUENCY (MHz)

SFDR (dBc)

MAX19710 toc08

0 102030405060708090100

Rx ADC SIGNAL-T0-NOISE RATIO

vs. ANALOG INPUT AMPLITUDE

ANALOG INPUT AMPLITUDE (dBFS)

SNR (dB)

MAX19710 toc09

-30 -25 -20 -15 -10 -5 0

fIN = 1.875MHz

MAX19710

Typical Operating Characteristics (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC

input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC

output, CREFP = CREFN = CCOM = 0.33µF, TA= +25°C, unless otherwise noted.)

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________

Rx ADC SIGNAL-TO-NOISE AND DISTORTION

RATIO vs. ANALOG INPUT AMPLITUDE

ANALOG INPUT AMPLITUDE (dBFS)

SINAD (dB)

MAX19710 toc10

-30 -25 -20 -15 -10 -5 0

fIN = 1.875MHz

Rx ADC TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT AMPLITUDE

ANALOG INPUT AMPLITUDE (dBFS)

-THD (dBc)

MAX19710 toc11

-30 -25 -20 -15 -10 -5 0

80 fIN = 1.875MHz

Rx ADC SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT AMPLITUDE

ANALOG INPUT AMPLITUDE (dBFS)

SFDR (dBc)

MAX19710 toc12

-30 -25 -20 -15 -10 -5 0

fIN = 1.875MHz

Rx ADC SPURIOUS-FREE DYNAMIC RANGE

vs. SAMPLING FREQUENCY

SAMPLING FREQUENCY (MHz)

SFDR (dBc)

MAX19710 toc16

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5

fIN = 1.875MHz

Rx ADC SIGNAL-TO-NOISE RATIO

vs. CLOCK DUTY CYCLE

CLOCK DUTY CYCLE (%)

SNR (dB)

MAX19710 toc17

35 40 45 50 55 60 65

fIN = 1.875MHz

Rx ADC SIGNAL-TO-NOISE AND DISTORTION

RATIO vs. CLOCK DUTY CYCLE

CLOCK DUTY CYCLE (%)

SINAD (dB)

MAX19710 toc18

35 40 45 50 55 60 65

fIN = 1.875MHz

Rx ADC SIGNAL-TO-NOISE RATIO

vs. SAMPLING FREQUENCY

SAMPLING FREQUENCY (MHz)

SNR (dB)

MAX19710 toc13

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5

52.0

52.5

53.0

53.5

54.0

54.5

55.0

55.5

56.0

56.5

57.0

fIN = 1.875MHz

Rx ADC SIGNAL-TO-NOISE AND DISTORTION

RATIO vs. SAMPLING FREQUENCY

SAMPLING FREQUENCY (MHz)

SINAD (dB)

MAX19710 toc14

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5

52.0

52.5

53.0

53.5

54.0

54.5

55.0

55.5

56.0

56.5

57.0

fIN = 1.875MHz

Rx ADC TOTAL HARMONIC DISTORTION

vs. SAMPLING FREQUENCY

SAMPLING FREQUENCY (MHz)

-THD (dBc)

MAX19710 toc15

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5

fIN = 1.875MHz

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

12 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC

input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC

output, CREFP = CREFN = CCOM = 0.33µF, TA= +25°C, unless otherwise noted.)

Rx ADC TOTAL HARMONIC DISTORTION

vs. CLOCK DUTY CYCLE

CLOCK DUTY CYCLE (%)

-THD (dBc)

MAX19710 toc19

35 40 45 50 55 60 65

90 fIN = 1.875MHz

Rx ADC SPURIOUS-FREE DYNAMIC RANGE

vs. CLOCK DUTY CYCLE

CLOCK DUTY CYCLE (%)

SFDR (dBc)

MAX19710 toc20

35 40 45 50 55 60 65

fIN = 1.875MHz

Rx ADC OFFSET ERROR vs. TEMPERATURE

TEMPERATURE (°C)

OFFSET ERROR (%FS)

MAX19710 toc21

-40 -15 10 35 60 85

-1.00

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

Tx DAC SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT AMPLITUDE

OUTPUT AMPLITUDE (dBFS)

SFDR (dBc)

MAX19710 toc25

-30 -25 -20 -15 -10 -5 0

fOUT = 2MHz

Tx DAC CHANNEL-ID SPECTRAL PLOT

FREQUENCY (MHz)

AMPLITUDE (dBFS)

MAX19710 toc26

0 0.76 1.52 2.28 3.04 3.80

-90

-80

-70

-60

-50

-40

-30

-20

-10

fOUT = 2.2MHz

Tx DAC CHANNEL-QD SPECTRAL PLOT

FREQUENCY (MHz)

AMPLITUDE (dBFS)

MAX19710 toc27

0 0.76 1.52 2.28 3.04 3.80

-90

-80

-70

-60

-50

-40

-30

-20

-10

fOUT = 2.2MHz

Rx ADC GAIN ERROR vs. TEMPERATURE

TEMPERATURE (°C)

GAIN ERROR (%FS)

MAX19710 toc22

-40 -15 10 35 60 85

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

Tx DAC SPURIOUS-FREE DYNAMIC RANGE

vs. SAMPLING FREQUENCY

SAMPLING FREQUENCY (MHz)

SFDR (dBc)

MAX19710 toc23

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5

fOUT = fCLK / 10

Tx DAC SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

MAX19710 toc24

0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8

MAX19710

Typical Operating Characteristics (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC

input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC

output, CREFP = CREFN = CCOM = 0.33µF, TA= +25°C, unless otherwise noted.)

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________

Tx DAC CHANNEL-ID TWO-TONE

SPECTRAL PLOT

FREQUENCY (MHz)

AMPLITUDE (dBFS)

MAX19710 toc28

0 0.76 1.52 2.28 3.04 3.80

-90

-80

-70

-60

-50

-40

-30

-20

-10

fOUT1 = 600kHz,

fOUT2 = 800kHz

Tx DAC CHANNEL-QD TWO-TONE

SPECTRAL PLOT

FREQUENCY (MHz)

AMPLITUDE (dBFS)

MAX19710 toc29

0 0.76 1.52 2.28 3.04 3.80

-90

-80

-70

-60

-50

-40

-30

-20

-10

fOUT1 = 600kHz,

fOUT2 = 800kHz

SUPPLY CURRENT

vs. SAMPLING FREQUENCY

SAMPLING FREQUENCY (MHz)

IVDD (mA)

MAX1910 toc30

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

FD MODE

fIN = 1.875MHz

fOUT = 620kHz

Tx DAC DIFFERENTIAL NONLINEARITY

DIGITAL INPUT CODE

DNL (LSB)

MAX19710 toc34

0 128 256 384 512 640 768 896 1024

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

REFERENCE OUTPUT VOLTAGE

vs. TEMPERATURE

TEMPERATURE (°C)

VREFP - VREFN (V)

MAX19710 toc35

-40 -15 10 35 60 85

0.500

0.505

0.510

0.515

0.520

VREFP - VREFN

AUX-DAC INTEGRAL NONLINEARITY

DIGITAL INPUT CODE

INL (LSB)

MAX19710 toc36

0 512 1024 1536 2048 2560 3072 3584 4096

-2.0

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

Rx ADC INTEGRAL NONLINEARITY

DIGITAL OUTPUT CODE

INL (LSB)

MAX19710 toc31

0 128 256 384 512 640 768 896 1024

-1.00

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

Rx ADC DIFFERENTIAL NONLINEARITY

DIGITAL OUTPUT CODE

DNL (LSB)

MAX19710 toc32

0 128 256 384 512 640 768 896 1024

-1.00

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

Tx DAC INTEGRAL NONLINEARITY

DIGITAL INPUT CODE

INL (LSB)

MAX19710 toc33

0 128 256 384 512 640 768 896 1024

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

14 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC

input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC

output, CREFP = CREFN = CCOM = 0.33µF, TA= +25°C, unless otherwise noted.)

AUX-DAC DIFFERENTIAL NONLINEARITY

MAX19710 toc37

DIGITAL INPUT CODE

DNL (LSB)

30722560204815361024512

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-0.6

-0.8

-1.0

0 40963584

AUX-ADC INTEGRAL NONLINEARITY

DIGITAL OUTPUT CODE

INL (LSB)

MAX19710 toc38

0 128 256 384 512 640 768 896 1024

-2.0

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

AUX-ADC DIFFERENTIAL NONLINEARITY

DIGITAL OUTPUT CODE

DNL (LSB)

MAX19710 toc39

0 128 256 384 512 640 768 896 1024

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

AUX-DAC OUTPUT VOLTAGE

vs. OUTPUT SOURCE CURRENT

MAX19710 toc40

OUTPUT SOURCE CURRENT (mA)

OUTPUT VOLTAGE (V)

1010.10.01

0.5

1.0

1.5

2.0

2.5

3.0

0.001 100

AUX-DAC OUTPUT VOLTAGE

vs. OUTPUT SINK CURRENT

OUTPUT SINK CURRENT (mA)

OUTPUT VOLTAGE (V)

MAX19710 toc41

0.5

1.0

1.5

2.0

2.5

3.0

0.001 0.01 0.1 1 10 100

AUX-DAC SETTLING TIME

MAX19710 toc42

AUX-DAC

OUTPUT

CS/WAKE

1V/div

500mV/div

400ns/div

STEP FROM CODE 1024 TO CODE 3072

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 15

Pin Description

Detailed Description

The MAX19710 integrates a dual, 10-bit Rx ADC and a

dual, 10-bit Tx DAC while providing ultra-low power

and high dynamic performance at 7.5Msps conversion

rate. The Rx ADC analog input amplifiers are fully differ-

ential and accept 1.024VP-P full-scale signals. The Tx

DAC analog outputs are fully differential with ±400mV

full-scale output, selectable common-mode DC level,

and adjustable channel ID–QD offset trim.

PIN NAME FUNCTION

1 REFP Positive Reference Voltage Input Terminal. Bypass with a 0.33µF capacitor to GND as close to REFP

as possible.

2, 8, 11, 39,

41, 47, 51 VDD Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with

a 0.1µF capacitor.

3 IAP Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP.

4 IAN Channel-IA Negative Analog Input. For single-ended operation, connect IAN to COM.

5, 7, 12, 40, 50

GND Analog Ground. Connect all GND pins to ground plane.

6 CLK Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs.

9 QAN Channel-QA Negative Analog Input. For single-ended operation, connect QAN to COM.

10 QAP Channel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP.

13–22

AD0–AD9

Receive ADC Digital Outputs. AD9 is the most significant bit (MSB) and AD0 is the least significant

bit (LSB).

23 OGND Output-Driver Ground

24 OVDD Output-Driver Power Supply. Supply range from +1.8V to VDD. Bypass OVDD to OGND with a

combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.

25–34

DA0–DA9

Transmit DAC Digital Inputs. DA9 is the most significant bit (MSB) and DA0 is the least significant bit

(LSB). DA0–DA9 are internally pulled up to OVDD.

35 DOUT Aux-ADC Digital Output

36 DIN 3-Wire Serial-Interface Data Input. Data is latched on the rising edge of SCLK.

37 SCLK 3-Wire Serial-Interface Clock Input

CS/WAKE

3-Wire Serial-Interface Chip-Select/WAKE Input. When the MAX19710 is in shutdown, CS/WAKE

controls the wake-up function. See the Wake-Up Function section.

42 ADC2 Selectable Auxiliary ADC Analog Input 2

43 ADC1 Selectable Auxiliary ADC Analog Input 1

44 DAC3 Auxiliary DAC3 Analog Output (VOUT = 0 at Power-Up)

45 DAC2 Auxiliary DAC2 Analog Output (VOUT = 0 at Power-Up)

46 DAC1 Auxiliary DAC1 Analog Output (AFC DAC, VOUT = 1.1V at Power-Up)

48 IDN Tx Path Channel-ID Differential Negative Output

49 IDP Tx Path Channel-ID Differential Positive Output

52 QDN Tx Path Channel-QD Differential Negative Output

53 QDP Tx Path Channel-QD Differential Positive Output

54 REFIN Reference Input. Connect to VDD for internal reference.

55 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.

56 REFN Negative Reference Voltage Input Terminal. Rx ADC conversion range is ±(VREFP - VREFN). Bypass

REFN to GND with a 0.33µF capacitor.

— EP Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

16 ______________________________________________________________________________________16 ______________________________________________________________________________________

Figure 1. Rx ADC Internal T/H Circuits

The MAX19710 integrates three 12-bit auxiliary DACs

(aux-DACs) and a 10-bit, 333ksps auxiliary ADC (aux-

ADC) with 4:1 input multiplexer. The aux-DAC channels

feature 1µs settling time for fast AGC, VGA, and AFC

level setting. The aux-ADC features data averaging to

reduce processor overhead and a selectable clock-

divider to program the conversion rate.

The MAX19710 includes a 3-wire serial interface to con-

trol operating modes and power management. The seri-

al interface is SPI™ and MICROWIRE™ compatible.

The MAX19710 serial interface selects shutdown, idle,

standby, FD, transmit (Tx), and receive (Rx) modes, as

well as controls aux-DAC and aux-ADC channels.

The MAX19710 features two independent, high-speed,

10-bit buses for the Rx ADC and Tx DAC, which allow

full-duplex (FD) operation for frequency-division duplex

applications. Each bus can be disabled to optimize

power management through the 3-wire interface. The

MAX19710 operates from a single 2.7V to 3.3V analog

supply and a 1.8V to 3.3V digital supply.

Dual 10-Bit Rx ADC

The ADC uses a seven-stage, fully differential, pipelined

architecture that allows for high-speed conversion while

minimizing power consumption. Samples taken at the

inputs move progressively through the pipeline stages

every half clock cycle. Including the delay through the

output latch, the total clock-cycle latency is 5 clock

cycles for channel IA and 5.5 clock cycles for channel

QA. The ADC full-scale analog input range is ±VREF

with a VDD / 2 (±0.8V) common-mode input range. VREF

is the difference between VREFP and VREFN. See the

Reference Configurations

section for details.

Input Track-and-Hold (T/H) Circuits

Figure 1 displays a simplified diagram of the Rx ADC

input track-and-hold (T/H) circuitry. Both ADC inputs

(IAP, QAP, IAN, and QAN) can be driven either differen-

S3b

S3a

COM

S5b

S5a

QAP

QAN

OUT

C2a

C2b

S4c

S4a

S4b C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

HOLD HOLD CLK

INTERNAL

NONOVERLAPPING

CLOCK SIGNALS

TRACK TRACK

S2a

S2b

S3b

S3a

COM

S5b

S5a

IAP

IAN

OUT

C2a

C2b

S4c

S4a

S4b C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

S2a

S2b

MAX19710

MICROWIRE is a trademark of National Semiconductor Corp.

SPI is a trademark of Motorola, Inc.

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 17

tially or single-ended. Match the impedance of IAP and

IAN, as well as QAP and QAN, and set the input signal

common-mode voltage within the VDD / 2 (±0.8V) Rx

ADC range for optimum performance.

Rx ADC System Timing Requirements

Figure 3 shows the relationship between the clock, ana-

log inputs, and the resulting output data. Channels IA

and QA are sampled on the rising edge of the clock sig-

nal (CLK) and the resulting data is multiplexed at the

AD0–AD9 outputs. Channel IA data is updated on the ris-

ing edge and channel QA data is updated on the falling

edge of CLK. Including the delay through the output

latch, the total clock-cycle latency is 5 clock cycles for

channel IA and 5.5 clock cycles for channel QA.

Digital Output Data (AD0–AD9)

AD0–AD9 are the Rx ADC digital logic outputs of the

MAX19710. The logic level is set by OVDD from 1.8V to

VDD. The digital output coding is offset binary (Table 1).

Keep the capacitive load on the digital outputs AD0–AD9

as low as possible (< 15pF) to avoid large digital currents

feeding back into the analog portion of the MAX19710

and degrading its dynamic performance. Buffers on the

digital outputs isolate the outputs from heavy capacitive

loads. Adding 100Ωresistors in series with the digital out-

puts close to the MAX19710 will help improve ADC per-

formance. Refer to the MAX19710EVKIT schematic for an

example of the digital outputs driving a digital buffer

through 100Ωseries resistors.

During SHDN, IDLE, STBY, SPI2, and SPI4 states, digital

outputs AD0–AD9 are tri-stated.

Dual 10-Bit Tx DACs

The dual 10-bit digital-to-analog converters (Tx DACs)

operate with clock speeds up to 7.5MHz. The Tx DAC

digital inputs, DA0–DA9, are multiplexed on a single

10-bit transmit bus. The voltage reference determines

the Tx DAC full-scale voltage at IDP, IDN and QDP,

QDN analog outputs. See the

Reference Configurations

section for setting the reference voltage.

Figure 2. Rx ADC Transfer Function

INPUT VOLTAGE (LSB)

-1

-510 -509

1024

2 x VREF

1 LSB = VREF = VREFP - VREFN

VREF VREF

VREF

0+ 1

-511 +510 +512

+511

-512 +509

(COM)

OFFSET BINARY OUTPUT CODE (LSB)

00 0000 0000

00 0000 0001

00 0000 0010

00 0000 0011

11 1111 1111

11 1111 1110

11 1111 1101

01 1111 1111

10 0000 0000

10 0000 0001

Table 1. Rx ADC Output Codes vs. Input Voltage

DIFFERENTIAL INPUT

VOLTAGE DIFFERENTIAL INPUT

(

LSB

)

OFFSET BINARY

(

AD0–AD9

)

OUTPUT DECIMAL CODE

VREF x 512/512 511 (+Full Scale - 1 LSB) 11 1111 1111 1023

VREF x 511/512 510 (+Full Scale - 2 LSB) 11 1111 1110 1022

VREF x 1/512 +1 10 0000 0001 513

VREF x 0/512 0 (Bipolar Zero) 10 0000 0000 512

-VREF x 1/512 -1 01 1111 1111 511

-VREF x 511/512 -511 (-Full Scale + 1 LSB) 00 0000 0001 1

-VREF x 512/512 -512 (-Full Scale) 00 0000 0000 0

______________________________________________________________________________________ 17

18 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

18 ______________________________________________________________________________________

Figure 3. Rx ADC System Timing Diagram

tDOQ

tCL tCH

tCLK

tDOI

5 CLOCK-CYCLE LATENCY (IA)

5.5 CLOCK-CYCLE LATENCY (QA)

D0–D9 D0Q D1I D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q

CLK

Table 2. Tx DAC Output Voltage vs. Input Codes

(Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN, VFS = 400 for 800mVP-P

Full Scale)

The Tx DAC outputs (IDN, IDP, QDN, QDP) are biased at

an adjustable common-mode DC level and designed to

drive a differential input stage with ≥70kΩinput imped-

ance. This simplifies the analog interface between RF

quadrature upconverters and the MAX19710. Many RF

upconverters require a 0.89V to 1.36V common-mode

bias. The MAX19710 common-mode DC bias eliminates

discrete level-setting resistors and code-generated level

shifting while preserving the full dynamic range of each

Tx DAC. The Tx DAC differential analog outputs can-

not be used in single-ended mode because of the

internally generated common-mode DC level. Table 2

shows the Tx DAC output voltage vs. input codes. Table

10 shows the selection of DC common-mode levels.

See Figure 4 for an illustration of the Tx DAC analog

output levels.

The Tx DAC also features independent DC offset trim on

each ID–QD channel. This feature is configured through

the SPI interface. The DC offset correction is used to opti-

mize sideband and carrier suppression in the Tx signal

path (see Table 9).

DIFFERENTIAL OUTPUT VOLTAGE

(

)

OFFSET BINARY (DA0–DA9) INPUT DECIMAL CODE

11 1111 1111 1023

11 1111 1110 1022

10 0000 0001 513

10 0000 0000 512

01 1111 1111 511

00 0000 0001 1

00 0000 0000 0

FS REFDAC

1024

1023

()

FS REFDAC

1024

1023

()

FS REFDAC

1024

1023

()

FS REFDAC

1024

1023

()

FS REFDAC

1024

1023

()

FS REFDAC

1023

()

FS REFDAC

1024

1023

()

______________________________________________________________________________________ 19

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 19

Figure 5. Tx DAC System Timing Diagram

tDSQ

tDSI

Q: N - 2 I: N - 1

D0–D9

CLK

Q: N - 1 I: N Q: N I: N + 1

N - 2 N - 1 N

tDHQ

tDHI

Figure 4. Tx DAC Common-Mode DC Level at IDN, IDP or QDN, QDP Differential Outputs

0°

FULL SCALE = 1.56V

VCOMD = 1.36V

ZERO SCALE = 1.16V

COMMON-MODE LEVEL

EXAMPLE:

Tx RFIC INPUT REQUIREMENTS

• DC COMMON-MODE BIAS = 0.9V (MIN), 1.3V (TYP)

• BASEBAND INPUT = ±400mV DC-COUPLED

90°

MAX19710

SELECT CM1 = 0, CM0 = 0

VCOMD = 1.36V

VFS = ±400mV

Tx DAC

CH-ID

Tx DAC

CH-QD

20 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

20 ______________________________________________________________________________________

Tx DAC Timing

Figure 5 shows the relationship among the clock, input

data, and analog outputs. Channel ID data is latched

on the falling edge of the clock signal, and channel

QD data is latched on the rising edge of the clock sig-

nal, at which point both ID and QD outputs are simul-

taneously updated.

3-Wire Serial Interface and

Operation Modes

The 3-wire serial interface controls the MAX19710 oper-

ation modes as well as the three 12-bit aux-DACs and

the 10-bit aux-ADC. Upon power-up, program the

MAX19710 to operate in the desired mode. Use the 3-

wire serial interface to program the device for shutdown,

idle, standby, FD, Rx, Tx, aux-DAC controls, or aux-ADC

conversion. A 16-bit data register sets the mode control

as shown in Table 3. The 16-bit word is composed of

four control bits (A3–A0) and 12 data bits (D11–D0).

Data is shifted in MSB first (D11) and LSB last (A0) for-

mat. Table 4 shows the MAX19710 power-management

modes. Table 5 shows the SPI-controlled Tx, Rx, and FD

modes. The serial interface remains active in all modes.

SPI Register Description

Program the control bits, A3–A0, in the register as shown

in Table 3 to select the operating mode. Modify A3–A0

bits to select from ENABLE-16, Aux-DAC1, Aux-DAC2,

Aux-DAC3, IOFFSET, QOFFSET, COMSEL, Aux-ADC,

ENABLE-8, and WAKEUP-SEL modes. ENABLE-16 is

the default operating mode (see Table 6). This mode

allows for shutdown, idle, and standby states as well as

switching between FAST, SLOW, Rx and Tx modes.

Tables 4 and 5 show the required SPI settings for

each mode.

In ENABLE-16 mode, the aux-DACs have independent

control bits E4, E5, and E6, and bit E9 enables the aux-

ADC. Table 7 shows the auxiliary DAC enable codes.

Table 8 shows the auxiliary ADC enable code. Bits E11

and E10 are reserved. Program bits E11 and E10 to

logic-low. Bits E3, E7, and E8 are not used.

Modes aux-DAC1, aux-DAC2, and aux-DAC3 select the

aux-DAC channels named DAC1, DAC2, and DAC3 and

hold the data inputs for each DAC. Bits _D11–_D0 are

the data inputs for each aux-DAC and can be pro-

grammed through SPI. The MAX19710 also includes

two 6-bit registers that can be programmed to adjust the

offsets for the Tx DAC ID and QD channels indepen-

dently (see Table 9). Use the COMSEL mode to select

the output common-mode voltage with bits CM1 and

CM0 (see Table 10). Use the aux-ADC mode to start the

auxiliary ADC conversion (see the

10-Bit, 333ksps

Auxiliary ADC

section for details). Use ENABLE-8 mode

for faster enable and switching between shutdown, idle,

and standby states as well as switching between FAST,

SLOW, Rx and Tx modes and the FD mode.

The WAKEUP-SEL register selects the operating mode

that the MAX19710 is to enter immediately after coming

out of shutdown (Table 11). See the

Wake-Up Function

section for more information.

Shutdown mode offers the most dramatic power sav-

ings by shutting down all the analog sections (including

the reference) of the MAX19710. In shutdown mode,

the Rx ADC digital outputs are in tri-state mode, the Tx

DAC digital inputs are internally pulled to OVDD, and

the Tx DAC outputs are at 0V. When the Rx ADC out-

puts transition from tri-state to active mode, the last

converted word is placed on the digital output bus. The

Tx DAC previously stored data is lost when coming out

of shutdown mode. The wake-up time from shutdown

mode is dominated by the time required to charge the

capacitors at REFP, REFN, and COM. In internal refer-

ence mode and buffered external reference mode, the

wake-up time is typically 500µs to enter Rx mode,

26.2µs to enter Tx mode, and 500µs to enter

FD mode.

In all operating modes the Tx DAC inputs DA0–DA9 are

internally pulled to OVDD. To reduce the supply current of

the MAX19710 in shutdown mode do not pull DA0–DA9

low. This consideration is especially important in shut-

down mode to achieve the lowest quiescent current.

In idle mode, the reference and clock distribution cir-

cuits are powered, but all other functions are off. The

Rx ADC outputs AD0–AD9 are forced to tri-state. The

Tx DAC DA0–DA9 inputs are internally pulled to OVDD,

while the Tx DAC outputs are at 0V. The wake-up time

is 7.3µs to enter Rx mode, 5.2µs to enter Tx mode, and

7.3µs to enter FD mode. When the Rx ADC outputs

transition from tri-state to active, the last converted

word is placed on the digital output bus.

In standby mode, the reference is powered but all other

device functions are off. The wake-up time from stand-

by mode is 7.5µs to enter Rx mode, 22.2µs to enter Tx

mode, and 22.2µs to enter FD mode. When the Rx ADC

outputs transition from tri-state to active, the last con-

verted word is placed on the digital output bus.

FAST and SLOW Rx and Tx Modes

The MAX19710 features FAST and SLOW modes for

switching between Rx and Tx operation. In FAST Tx

mode, the Rx ADC core is powered on but the ADC digi-

tal outputs AD0–AD9 are tri-stated. The Tx DAC digital

bus is active and the DAC core is fully operational.

______________________________________________________________________________________ 21

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 21

Table 4. Power-Management Modes

ADDRESS DATA BITS

A3 A2 A1 A0 E9* E2 E1 E0

MODE FUNCTION (POWER

MANAGEMENT) DESCRIPTION COMMENT

1 0 0 0 SHDN SHUTDOWN

Rx ADC = OFF

Tx DAC = OFF

(TX DAC outputs at 0V)

Aux-DAC = OFF

Aux-ADC = OFF

CLK = OFF

REF = OFF

Device is in

complete shutdown.

X** 0 0 1 IDLE IDLE

Rx ADC = OFF

Tx DAC = OFF

(TX DAC outputs at 0V)

Aux-DAC = Last State

CLK = ON

REF = ON

Fast turn-on time.

Moderate idle

power.

0000

(16-Bit Mode)

1000

(8-Bit Mode)

X** 0 1 0 STBY STANDBY

Rx ADC = OFF

Tx DAC = OFF

(TX DAC outputs at 0V)

Aux-DAC = Last State

CLK = OFF

REF = ON

Slow turn-on time.

Low standby power.

X = Don’t care.

Bit E9 is not available in 8-bit mode.

In IDLE and STBY modes, the aux-ADC can be turned on or off.

Table 3. MAX19710 Mode Control

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0

NAME (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (LSB)

ENABLE-16 E11 = 0

Reserved

E10 = 0

Reserved E9 — — E6 E5 E4 — E2 E1 E0 0 0 0 0

Aux-DAC1 1D11 1D10 1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0 0 0 0 1

Aux-DAC2 2D11 2D10 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0 0 0 1 0

Aux-DAC3 3D11 3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0 0 0 1 1

IOFFSET — — — — — — IO5 IO4 IO3 IO2 IO1 IO0 0 1 0 0

QOFFSET — — — — — — QO5 QO4 QO3 QO2 QO1 QO0 0 1 0 1

COMSEL — — — — — — — — — — CM1 CM0 0 1 1 0

Aux-ADC AD11 = 0

Reserved AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 1 1 1

ENABLE-8 — — — — — — — — — E2 E1 E0 1 0 0 0

WAKEUP-SEL — — — — — — — — — W2 W1 W0 1 0 0 1

— = Not used.

22 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

22 ______________________________________________________________________________________

Table 5. MAX19710 Tx, Rx, and FD Control Using SPI Commands

In FAST Rx mode, the Tx DAC core is powered on. The

Tx DAC outputs are set to midscale. In this mode, the Tx

DAC input bus is disconnected from the DAC core and

DA0–DA9 are internally pulled to OVDD. The Rx ADC

digital bus is active and the ADC core is fully opera-

tional.

In FAST mode, the switching time from Tx to Rx, or Rx to

Tx is minimized because the converters are on and do

not have to recover from a power-down state. In FAST

mode, the switching time from Rx to Tx and Tx to Rx is

0.1µs. Power consumption is higher in FAST mode

because both Tx and Rx cores are always on.

In SLOW Tx mode, the Rx ADC core is powered off and

the ADC digital outputs AD0–AD9 are tri-stated. The Tx

DAC digital bus is active and the DAC core is fully oper-

ational. In SLOW Rx mode, the Tx DAC core is powered

off. The Tx DAC outputs are set to 0. In SLOW Rx mode,

the Tx DAC input bus is disconnected from the DAC

core and DA0–DA9 are internally pulled to OVDD. The

Rx ADC digital bus is active and the ADC core is fully

operational. The switching times for SLOW modes are

5.2µs for Rx to Tx and 7.3µs for Tx to Rx.

ADDRESS DATA BITS

A3 A2 A1 A0 E2 E1 E0 MODE FUNCTION

(Tx-Rx SWITCHING SPEED) DESCRIPTION COMMENT

0 1 1 SPI1-Rx SLOW

Rx Mode:

Rx ADC = ON

Rx Bus = Enabled

Tx DAC = OFF

(Tx DAC outputs at 0V)

Tx Bus = OFF (all inputs

are pulled high)

Slow transition to Tx

mode from this

mode.

Low power.

1 0 0 SPI2-Tx SLOW

Tx Mode:

Rx ADC = OFF

Rx Bus = Tri-state

Tx DAC = ON

Tx Bus = ON

Slow transition to Rx

mode from this

mode.

Low power.

1 0 1 SPI3-Rx FAST

Rx Mode:

Rx ADC = ON

Rx Bus = Enabled

Tx DAC = ON

(Tx DAC outputs at

midscale)

Tx Bus = OFF (all inputs

are pulled high)

Fast transition to Tx

mode from this

mode. Moderate

power.

1 1 0 SPI4-Tx FAST

Tx Mode:

Rx ADC = ON

Rx Bus = Tri-state

Tx DAC = ON

Tx Bus = ON

Fast transition to Rx

mode from this

mode. Moderate

power.

0000

(16-Bit Mode)

and

1000

(8-Bit Mode)

1 1 1 FD FAST

FD Mode:

Rx ADC = ON

Rx Bus = ON

Tx DAC = ON

Tx Bus = ON

Default Mode

Fast transition to any

mode. Moderate

power.

______________________________________________________________________________________ 23

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 23

Power consumption in SLOW Tx mode is 21.9mW, and

21.3mW in SLOW Rx mode. Power consumption in FAST

Tx mode is 29.1mW, and 28.5mW in FAST Rx mode.

FD Mode

The MAX19710 features an FD mode, which is ideal for

applications supporting frequency-division duplex. In

FD mode, both Rx ADC and Tx DAC, as well as their

Table 6. MAX19710 Default (Power-On) Register Settings

D11D10D9 D8D7D6D5D4D3D2D1D0

NAME 16

(MSB) 15 14 13 12 11 10 9 8 7 6 5

0 000 111

ENABLE-16 00

Aux- AD C

= ON

—— Aux- D AC1 to

Aux- D AC3 = ON

—FD mode

011 010001100

Aux-DAC1 DAC1 output set to 1.1V

00 0 0 0 0 0 0 0 0 0 0

Aux-DAC2 DAC2 output set to 0V

00 0 0 0 0 0 0 0 0 0 0

Aux-DAC3 DAC3 output set to 0V

000000

IOFFSET —— — — — — No offset on channel ID

000000

QOFFSET —— — — — — No offset on channel QD

COMSEL ——— ———————

VCOMD = 1.36V

00 000000000

Aux-ADC 0Aux-ADC = ON, Conversion = IDLE, Aux-ADC REF = 2.048V, MUX = ADC1,

Averaging = 1, Clock Divider = 1, DOUT = Disabled

111

ENABLE-8 ——— —————— FD mode

111

WA KEU P- SEL ——— ——————

Wake-up state = FD mode

Table 7. Aux-DAC Enable Table

(ENABLE-16 Mode)

E6 E5 E4 Aux-DAC3 Aux-DAC2 Aux-DAC1

000ONONON

0 0 1 ON ON OFF

0 1 0 ON OFF ON

0 1 1 ON OFF OFF

1 0 0 OFF ON ON

1 0 1 OFF ON OFF

1 1 0 OFF OFF ON

1 1 1 OFF OFF OFF

0 0 0 Default mode

Table 8. Aux-ADC Enable Table

(ENABLE-16 Mode)

E9 SELECTION

0 (Default) Aux-ADC is Powered ON

1 Aux-ADC is Powered OFF

24 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

24 ______________________________________________________________________________________

respective digital buses, are active and the device can

receive and transmit simultaneously. Switching from FD

mode to other Rx or Tx modes is fast (0.1µs) since

the on-board converters are already powered.

Consequently, power consumption in this mode is the

maximum of all operating modes. In FD mode the

MAX19710 consumes 30mW.

Wake-Up Function

The MAX19710 uses the SPI interface to control the

operating modes of the device including the shutdown

and wake-up functions. Once the device has been

placed in shutdown through the appropriate SPI com-

mand, the first pulse on CS/WAKE performs a wake-up

function. At the first rising edge of CS/WAKE, the

MAX19710 is forced to a preset operating mode deter-

mined by the WAKEUP-SEL register. This mode is

termed the wake-up state. If the WAKEUP-SEL register

has not been programmed, the wake-up state for the

MAX19710 is FD mode by default (Tables 6, 11). The

WAKEUP-SEL register cannot be programmed with W2

Table 9. Offset Control Bits for ID and QD Channels (IOFFSET or QOFFSET Mode)

BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE

IO5/QO5 IO4/QO4 IO3/QO3 IO2/QO2 IO1/QO1 IO0/QO0

OFFSET 1 LSB =

(VFSP-P / 1023)

1 1 1 1 1 1 -31 LSB

1 1 1 1 1 0 -30 LSB

1 1 1 1 0 1 -29 LSB

•

100010-2 LSB

100001-1 LSB

1000000mV

0 0 0 0 0 0 0mV (Default)

0000011 LSB

0000102 LSB

•

01110129 LSB

01111030 LSB

01111131 LSB

Note: 1 LSB = (800mVP-P / 1023) = 0.782mV.

Table 10. Common-Mode Select

(COMSEL Mode)

CM1 CM0 Tx PATH OUTPUT COMMON MODE (V)

0 0 1.36 (Default)

0 1 1.20

1 0 1.05

1 1 0.89

Table 11. WAKEUP-SEL Register

W2 W1 W0 POWER MODE AFTER WAKE-UP

(WAKE-UP STATE)

000

Invalid Value. This value is ignored

when inadvertently written to the

WAKEUP-SEL register.

0 0 1 IDLE

0 1 0 STBY

0 1 1 SPI1-SLOW Rx

1 0 0 SPI2-SLOW Tx

1 0 1 SPI3-FAST Rx

1 1 0 SPI4-FAST Tx

111 FD (Default)

______________________________________________________________________________________ 25

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 25

Figure 6. Serial-Interface Timing Diagram

tCSW

tCS

LSB

tCL

tCP

tCH

tDH

tDS

MSB

tCSS

SCLK

DIN

CS/WAKE

QSPI is a trademark of Motorola, Inc.

Figure 7. Mode-Recovery Timing Diagram

CS/WAKE

SCLK

DIN 16-BIT SERIAL DATA INPUT

AD0–AD9

ID/QD

DAC ANALOG OUTPUT

SETTLES TO 10 LSB ERROR

ADC DIGITAL OUTPUT SINAD

SETTLES TO WITHIN 1dB

WAKE,SD,ST_

TO Rx MODE OR t

ENABLE

WAKE,SD,ST_

TO Tx MODE OR t

ENABLE

= 0, W1 = 0, and W0 = 0. If this value is inadvertently

written to the device, it is ignored and the register con-

tinues to store its previous value. Upon wake-up, the

MAX19710 enters the power mode determined by the

WAKEUP-SEL register, however, all other settings (Tx

DAC offset, Tx DAC common-mode voltage, aux-DAC

settings, aux-ADC state) are restored to their values

prior to shutdown.

The only SPI line that is monitored by the MAX19710

during shutdown is CS/WAKE. Any information transmit-

ted to the MAX19710 concurrent with the CS/WAKE

wake-up pulse is ignored.

SPI Timing

The serial digital interface is a standard 3-wire connection

CS/WAKE, SCLK, DIN) compatible with SPI/QSPI™/

MICROWIRE/DSP interfaces. Set CS/WAKE low to enable

the serial data loading at DIN or output at DOUT. Following

a CS/WAKE high-to-low transition, data is shifted synchro-

nously, most significant bit first, on the rising edge of the

serial clock (SCLK). After 16 bits are loaded into the serial

input register, data is transferred to the latch when

CS/WAKE transitions high. CS/WAKE must transition high

for a minimum of 80ns before the next write sequence.

SCLK can idle either high or low between transitions.

Figure 6 shows the detailed timing diagram of the 3-wire

serial interface.

Mode-Recovery Timing

Figure 7 shows the mode-recovery timing diagram.

tWAKE is the wake-up time when exiting shutdown, idle,

or standby mode and entering Rx, Tx, or FD mode.

tENABLE is the recovery time when switching between

either Rx or Tx mode. tWAKE or tENABLE is the time for

the Rx ADC to settle within 1dB of specified SINAD per-

formance and Tx DAC settling to 10 LSB error. tWAKE

and tENABLE times are measured after the 16-bit serial

command is latched into the MAX19710 by a CS/WAKE

transition high. In FAST mode, the recovery time is 0.1µs

to switch between Tx or Rx modes.

26 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

26 ______________________________________________________________________________________

System Clock Input (CLK)

Both the Rx ADC and Tx DAC share the CLK input. The

CLK input accepts a CMOS-compatible signal level set

by OVDD from 1.8V to VDD. Since the interstage con-

version of the device depends on the repeatability of

the rising and falling edges of the external clock, use a

clock with low jitter and fast rise and fall times (< 2ns).

Specifically, sampling occurs on the rising edge of the

clock signal, requiring this edge to provide the lowest

possible jitter. Any significant clock jitter limits the SNR

performance of the on-chip Rx ADC as follows:

where fIN represents the analog input frequency and

tAJ is the time of the clock jitter.

Clock jitter is especially critical for undersampling

applications. Consider the clock input as an analog

input and route away from any analog input or other

digital signal lines. The MAX19710 clock input operates

with an OVDD / 2 voltage threshold and accepts a 50%

±10% duty cycle.

When the clock signal is stopped at CLK input (CLK =

0V or OVDD), all internal registers hold their last value

and the MAX19710 saves the last power-management

mode or Tx/Rx/FD command. All converter circuits (Rx

ADC, Tx DAC, aux-ADC, and aux-DACs) hold their last

value. When the clock signal is restarted at CLK, allow

7.5µs (clock wake-up time) for the internal clock circuit-

ry to settle before updating the Tx DAC, reading a valid

Rx ADC conversion result, or starting an aux-ADC con-

version. This ensures the converters (Rx ADC, Tx DAC,

aux-ADC) meet all dynamic performance specifica-

tions. The aux-DAC channels are not dependent on

CLK, so they may be updated when CLK is idle.

12-Bit, Auxiliary Control DACs

The MAX19710 includes three 12-bit aux-DACs (DAC1,

DAC2, DAC3) with 1µs settling time for controlling vari-

able-gain amplifier (VGA), automatic gain-control

(AGC), and automatic frequency-control (AFC) func-

tions. The aux-DAC output range is 0.2V to 2.57V as

defined by VOH - VOL. During power-up, the VGA and

AGC outputs (DAC2 and DAC3) are at zero. The AFC

DAC (DAC1) is at 1.1V during power-up. The aux-DACs

can be independently controlled through the SPI bus,

except during SHDN mode where the aux-DACs are

turned off completely and the output voltage is set to

zero. In STBY and IDLE modes the aux-DACs maintain

the last value. On wake-up from SHDN, the aux-DACs

resume the last values.

Loading on the aux-DAC outputs should be carefully

observed to achieve the specified settling time and sta-

bility. The capacitive load must be kept to a maximum

of 5pF including package and trace capacitance. The

resistive load must be greater than 200kΩ. If capacitive

loading exceeds 5pF, then add a 10kΩresistor in

series with the output. Adding the series resistor helps

drive larger load capacitance (< 15pF) at the expense

of slower settling time.

10-Bit, 333ksps Auxiliary ADC

The MAX19710 integrates a 333ksps, 10-bit aux-ADC

with an input 4:1 multiplexer. In the aux-ADC mode reg-

ister, setting bit AD0 begins a conversion with the auxil-

iary ADC. Bit AD0 automatically clears when the

conversion is complete. Setting or clearing AD0 during

a conversion has no effect (see Table 12). Bit AD1

determines the internal reference of the auxiliary ADC

(see Table 13). Bits AD2 and AD3 determine the auxil-

iary ADC input source (see Table 14). Bits AD4, AD5,

and AD6 select the number of averages taken when a

single start-convert command is given. The conversion

time increases as the number of averages increases

(see Table 15). The conversion clock can be divided

down from the system clock by properly setting bits

AD7, AD8, and AD9 (see Table 16). The aux-ADC out-

put data can be written out of DOUT by setting bit

AD10 high (see Table 17).

The aux-ADC features a 4:1 input multiplexer to allow

measurements on four input sources. The input sources

are selected by AD3 and AD2 (see Table 14). Two of

the multiplexer inputs (ADC1 and ADC2) can be con-

nected to external sources such as an RF power detec-

tor like the MAX2208 or temperature sensor like the

MAX6613. The other two multiplexer inputs are internal

connections to VDD and OVDD that monitor the power-

supply voltages. The internal VDD and OVDD connec-

tions are made through integrated dividers that yield

VDD / 2 and OVDD / 2 measurement results. The aux-

ADC voltage reference can be selected between an

internal 2.048V bandgap reference or VDD (see Table

13). The VDD reference selection is provided to allow

measurement of an external voltage source with a full-

scale range extending beyond the 2.048V level. The

input source voltage range cannot extend above VDD.

The conversion requires 12 clock edges (1 for input

sampling, 1 for each of the 10 bits, and 1 at the end for

loading into the serial output register) to complete one

conversion cycle (when no averaging is being done).

Each conversion of an average (when averaging is set

greater than 1) requires 12 clock edges. The conver-

sion clock is generated from the system clock input

(CLK). An SPI-programmable divider divides the system

logSNR ft

=× ×× ×

⎛

⎝

⎜

⎞

⎠

⎟

20 1

2πIN AJ

______________________________________________________________________________________ 27

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 27

clock by the appropriate divisor (set with bits AD7,

AD8, and AD9; see Table 16) and provides the conver-

sion clock to the auxiliary ADC. The auxiliary ADC has a

maximum conversion rate of 333ksps. The maximum

conversion clock frequency is 4MHz (333ksps x 12

clocks). Choose the proper divider value to keep the

conversion clock frequency under 4MHz, based upon

the system CLK frequency supplied to the MAX19710

(see Table 16). The total conversion time (tCONV) of the

auxiliary ADC can be calculated as tCONV = (12 x

NAVG x NDIV) / fCLK; where NAVG is the number of

averages (see Table 15), NDIV is the CLK divisor (see

Table 16), and fCLK is the system CLK frequency.

Reading DOUT from the Aux-ADC

DOUT is normally in a high-impedance condition. Upon

setting the auxiliary ADC start conversion bit (bit AD0),

DOUT becomes active and goes high, indicating that

the aux-ADC is busy. When the conversion cycle is

complete (including averaging), the data is placed into

an output register and DOUT goes low, indicating that

the output data is ready to be driven onto DOUT. When

bit AD10 is set (AD10 = 1), the aux-ADC enters a data

output mode where data is available at DOUT on the

next low assertion of CS/WAKE. The auxiliary ADC data

is shifted out of DOUT (MSB first) with the data transi-

tioning on the falling edge of the serial clock (SCLK).

Since a DOUT read requires 16 bits, DOUT holds the

value of the last conversion data bit for the last 6 bits (6

least significant bits) following the aux-ADC conversion

data. DOUT enters a high-impedance state when

CS/WAKE is deasserted high. When bit AD10 is cleared

(AD10 = 0), the aux-ADC data is not available on DOUT

(see Table 17).

After the aux-ADC completes a conversion, the data

result is loaded to an output register waiting to be shift-

ed out. No further conversions are possible until data is

shifted out. This means that if the first conversion com-

mand sets AD10 = 0, AD0 = 1, then it cannot be fol-

lowed by conversion commands setting AD10 = 0, AD0

= 1 or AD10 = 1, AD0 = 1. If this sequence of com-

mands is inadvertently used then DOUT is disabled. To

resume normal operation set AD0 = 0.

AD1 SELECTION

0 Internal 2.048V Reference (Default)

1 Internal VDD Reference

Table 13. Auxiliary ADC Reference

Table 14. Auxiliary ADC Input Source

AD3 AD2 Aux-ADC INPUT SOURCE

0 0 ADC1 (Default)

0 1 ADC2

10 V

DD / 2

11 OV

DD / 2

Table 12. Auxiliary ADC Convert

AD0 SELECTION

0 Aux-ADC Idle (Default)

1 Aux-ADC Start-Convert

Table 15. Auxiliary ADC Averaging

Table 16. Auxiliary ADC Clock (CLK)

Divider

AD6 AD5 AD4 Aux-ADC AVERAGING

0 0 0 1 Conversion (No Averaging) (Default)

0 0 1 Average of 2 Conversions

0 1 0 Average of 4 Conversions

0 1 1 Average of 8 Conversions

1 0 0 Average of 16 Conversions

1 0 1 Average of 32 Conversions

1 1 X Average of 32 Conversions

AD9 AD8 AD7 Aux-ADC CONVERSION CLOCK

0 0 0 CLK Divided by 1 (Default)

0 0 1 CLK Divided by 2

0 1 0 CLK Divided by 4

0 1 1 CLK Divided by 8

1 0 0 CLK Divided by 16

1 0 1 CLK Divided by 32

1 1 0 CLK Divided by 64

1 1 1 CLK Divided by 128

X = Don’t care.

Table 17. Auxiliary ADC Data Output

Mode

AD10 SELECTION

0 Aux-ADC Data is Not Available on DOUT (Default)

1Aux-ADC Enters Data Output Mode Where

Data is Available on DOUT

28 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

28 ______________________________________________________________________________________

The fastest method to perform sequential conversions

with the aux-ADC is by sending consecutive com-

mands setting AD10 = 1, AD0 = 1. With this sequence

the CS/WAKE falling edge shifts data from the previous

conversion on to DOUT and the rising edge of

CS/WAKE loads the next conversion command at DIN.

Allow enough time for each conversion to complete

before sending the next conversion command. See

Figure 8 for single and continuous conversion examples.

Figure 8. Aux-ADC Conversions Timing

CS/WAKE

2. CONTINUOUS AUX-ADC CONVERSIONS

SCLK

0001 111 1100111 1100111

16 1 10 11 12 13 14 15 16 1 10 11 12 13 14 15 161

DIN

DOUT D1 D0 D0 HELDD9D1 D0 D0 HELDD9

FIRST 10-BIT AUX-ADC

CONVERSION RESULT IS

SHIFTED OUT ON DOUT ON

THE FALLING EDGE OF SCLK

MSB FIRST

SECOND 10-BIT AUX-ADC

CONVERSION RESULT IS

SHIFTED OUT ON DOUT ON

THE FALLING EDGE OF SCLK

MSB FIRST

AD10 = 1, AD0 = 1,

PERFORM CONVERSION,

DOUT ENABLED

AD10 = 1, AD0 = 1,

PERFORM CONVERSION,

DOUT ENABLED

AD10 = 1, AD0 = 1,

PERFORM CONVERSION,

DOUT ENABLED

DOUT TRANSITIONS FROM

HIGH IMPEDANCE TO LOGIC-

HIGH INDICATING START OF

FIRST CONVERSION DOUT TRANSITIONS HIGH

INDICATING START OF

SECOND CONVERSION

DOUT TRANSITIONS HIGH

INDICATING START OF

THIRD CONVERSION

DOUT TRANSITIONS LOW

INDICATING END OF FIRST

CONVERSION, DATA IS AVAILABLE

AND CAN BE SHIFTED OUT IF DOUT

IS ENABLED, AD0 CLEARED

DOUT TRANSITIONS LOW

INDICATING END OF SECOND

CONVERSION, DATA IS AVAILABLE

AND CAN BE SHIFTED OUT IF DOUT

IS ENABLED, AD0 CLEARED

DOUT TRANSITIONS LOW

INDICATING END OF THIRD

CONVERSION, DATA IS AVAILABLE

AND CAN BE SHIFTED OUT IF DOUT

IS ENABLED, AD0 CLEARED

AUX-ADC REGISTER

ADDRESS

CSD

CHZ

CS/WAKE

SCLK

1. SINGLE AUX-ADC CONVERSION WITH CONVERSION DATA READOUT AT A LATER TIME

00 1 1 0 1 00 1 DIN SET HIGH DURING SINGLE READ

1111

16 1 16 1 16 1 1610

D1 D0 D0 HELDD9

DIN

DOUT

AD10 = 0, AD0 = 1,

PERFORM CONVERSION,

DOUT DISABLED

DOUT TRANSITIONS FROM

HIGH IMPEDANCE TO LOGIC-

HIGH INDICATING START OF

CONVERSION

DOUT TRANSITIONS LOW

INDICATING END OF CONVERSION,

DATA IS AVAILABLE AND CAN BE

SHIFTED OUT IF DOUT IS ENABLED,

AD0 CLEARED

IF AUX-ADC CONVERSION

DOES NOT NEED TO BE

READ IMMEDIATELY, THE SPI

INTERFACE IS FREE AND

CAN BE USED FOR OTHER

FUNCTIONS, SUCH AS

HOUSEKEEPING AUX-DAC

ADJUSTMENT, ETC.

AUX-ADC REGISTER

ADDRESS

CONVERSION RESULT DATA

BIT D0 IS HELD FOR THE SIX

LEAST SIGNIFICANT BITS

DOUT TRANSITIONS TO

HIGH IMPEDANCE

10-BIT AUX-ADC

CONVERSION RESULT IS

SHIFTED OUT ON DOUT ON

THE FALLING EDGE OF SCLK

MSB FIRST

AUX-ADC REGISTER

ADDRESS

AD10 = 1, AD0 = 0,

AUX-ADC IDLE

(NO CONVERSION),

DOUT ENABLED AND

CONVERSION DATA IS

SHIFTED OUT ON NEXT

CS/WAKE FALLING EDGE

FIRST FALLING EDGE OF

CS/WAKE AFTER DOUT IS

ENABLED STARTS SHIFTING THE

AUX-ADC CONVERSION DATA ON

THE FALLING EDGE OF SCLK

tDCS

tCONV

______________________________________________________________________________________ 29

MAX19710

DIN can be written independent of DOUT state. A 16-bit

instruction at DIN updates the device configuration. To

prevent modifying internal registers while reading data

from DOUT, hold DIN at a high state (only applies if

sequential aux-ADC conversions are not executed).

This effectively writes all ones into address 1111. Since

address 1111 does not exist, no internal registers

are affected.

Reference Configurations

The MAX19710 features an internal precision 1.024V-

bandgap reference that is stable over the entire power-

supply and temperature ranges. The REFIN input

provides two modes of reference operation. The volt-

age at REFIN (VREFIN) sets the reference operation

mode (Table 18).

In internal reference mode, connect REFIN to VDD.

VREF is an internally generated 0.512V ±4% reference

level. COM, REFP, and REFN are low-impedance out-

puts with VCOM = VDD / 2, VREFP = VDD / 2 + VREF / 2,

and VREFN = VDD / 2 - VREF / 2. Bypass REFP, REFN,

and COM each with a 0.33µF capacitor. Bypass REFIN

to GND with a 0.1µF capacitor.

In buffered external reference mode, apply 1.024V

±10% at REFIN. In this mode, COM, REFP, and REFN

are low-impedance outputs with VCOM = VDD / 2,

VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 -

VREFIN / 4. Bypass REFP, REFN, and COM each with a

0.33µF capacitor. Bypass REFIN to GND with a 0.1µF

capacitor. In this mode, the Tx path full-scale output is

proportional to the external reference. For example, if

the VREFIN is increased by 10% (max), the Tx path full-

scale output is also increased by 10% or ±440mV.

Applications Information

Using Balun Transformer AC-Coupling

An RF transformer (Figure 9) provides an excellent

solution to convert a single-ended signal source to a

fully differential signal for optimum ADC performance.

Connecting the center tap of the transformer to COM

provides a VDD / 2 DC level shift to the input. A 1:1

transformer can be used, or a step-up transformer can

be selected to reduce the drive requirements. In gener-

al, the MAX19710 provides better SFDR and THD with

fully differential input signals than single-ended signals,

especially for high input frequencies. In differential

mode, even-order harmonics are lower as both inputs

(IAP, IAN, QAP, QAN) are balanced, and each of the

Figure 9. Balun Transformer-Coupled Single-Ended-to-

Differential Input Drive for Rx ADC

COM

IAP

IAN

25Ω

0.1μF

0.33μF

25Ω

0.1μF

VIN

MAX19710

22pF

QAP

QAN

25Ω

0.1μF

0.33μF

25Ω

0.1μF

VIN

22pF

Table 18. Reference Modes

VREFIN REFERENCE MODE

> 0.8V x VDD Internal Reference Mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each

with a 0.33µF capacitor.

1.024V ±10%

Buffered External Reference Mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is

internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass

REFIN to GND with a 0.1µF capacitor.

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 29

30 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

30 ______________________________________________________________________________________

Rx ADC inputs only requires half the signal swing com-

pared to single-ended mode. Figure 10 shows an RF

transformer converting the MAX19710 Tx DAC differen-

tial analog outputs to single-ended.

Using Op-Amp Coupling

Drive the MAX19710 Rx ADC with op amps when a

balun transformer is not available. Figures 11 and 12

show the Rx ADC being driven by op amps for AC-cou-

pled single-ended and DC-coupled differential applica-

tions. Amplifiers such as the MAX4454 and MAX4354

provide high speed, high bandwidth, low noise, and

low distortion to maintain the input signal integrity. The

op-amp circuit shown in Figure 12 can also be used to

interface with the Tx DAC differential analog outputs to

provide gain or buffering. The Tx DAC differential ana-

log outputs cannot be used in single-ended mode

because of the internally generated common-mode

level. Also, the Tx DAC analog outputs are designed to

drive a differential input stage with input impedance ≥

70kΩ. If single-ended outputs are desired, use an

amplifier to provide differential-to-single-ended conver-

sion and select an amplifier with proper input common-

mode voltage range.

FDD Application

Figure 13 illustrates a typical FDD application circuit. The

MAX19710 interfaces directly with a ZIF radio front-end to

provide a complete “RF-to-Bits” solution for FDD applica-

tions such as private mobile radio (PMR), broadband

access radio, and proprietary radio systems. The

MAX19710 provides several system benefits to digital

baseband developers:

• Fast Time-to-Market

• High-Performance, Low-Power Analog Functions

• Low-Risk, Proven Analog Front-End Solution

• No Mixed-Signal Test Times

• No NRE Charges

• No IP Royalty Charges

• Enables Digital Baseband and Scale with 65nm to

90nm CMOS

Grounding, Bypassing, and

Board Layout

The MAX19710 requires high-speed board layout design

techniques. Refer to the MAX19710 EV kit data sheet for a

board layout reference. Place all bypass capacitors as

close to the device as possible, preferably on the same

side of the board as the device, using surface-mount

devices for minimum inductance. Bypass VDD to GND

with a 0.1µF ceramic capacitor in parallel with a 2.2µF

Figure 11. Single-Ended Drive for Rx ADC

MAX19710

0.1μF

1kΩ

100Ω

CIN

22pF

CIN

22pF

QAP

QAN

COM

IAP

IAN

0.1μFRISO

50Ω

RISO

50Ω

REFP

REFN

VIN

0.1μF

1kΩ

100Ω

CIN

22pF

CIN

22pF

0.1μFRISO

50Ω

RISO

50Ω

REFP

REFN

VIN

Figure 10. Balun Transformer-Coupled Differential-to-Single-

Ended Output Drive for Tx DAC

MAX19710

IDP

IDN

VOUT

QDP

QDN

VOUT

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 31

capacitor. Bypass OVDD to OGND with a 0.1µF ceramic

capacitor in parallel with a 2.2µF capacitor. Bypass REFP,

REFN, and COM each to GND with a 0.33µF ceramic

capacitor. Bypass REFIN to GND with a 0.1µF capacitor.

Multilayer boards with separated ground and power

planes yield the highest level of signal integrity. Use a

split ground plane arranged to match the physical loca-

tion of the analog ground (GND) and the digital output-

driver ground (OGND) on the device package. Connect

the MAX19710 exposed backside paddle to the GND

plane. Join the two ground planes at a single point so

the noisy digital ground currents do not interfere with

the analog ground plane. The ideal location for this

connection can be determined experimentally at a

point along the gap between the two ground planes.

Make this connection with a low-value, surface-mount

resistor (1Ωto 5Ω), a ferrite bead, or a direct short.

Alternatively, all ground pins could share the same

ground plane, if the ground plane is sufficiently isolated

from any noisy digital system’s ground plane (e.g.,

downstream output buffer or DSP ground plane).

Route high-speed digital signal traces away from sensi-

tive analog traces. Make sure to isolate the analog

input lines to each respective converter to minimize

channel-to-channel crosstalk. Keep all signal lines short

and free of 90° turns.

Dynamic Parameter Definitions

ADC and DAC Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an

actual transfer function from a straight line. This straight

line can be either a best-straight-line fit or a line drawn

between the end points of the transfer function, once

offset and gain errors have been nullified. The static lin-

earity parameters for the device are measured using

the best-straight-line fit (DAC Figure 14a).

Figure 12. Rx ADC DC-Coupled Differential Drive

MAX19710

IAP

COM

IAN

RISO

22Ω

RISO

22Ω

R11

600Ω

R10

600Ω

CIN

5pF

CIN

5pF

______________________________________________________________________________________ 31

32 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

32 ______________________________________________________________________________________

Figure 13. Typical FDD Application Circuit

CLK

SERIAL

INTERFACE

AND SYSTEM

CONTROL

IAP

IAN

QAP

QAN

IDP

IDN

QDP

QDN

REFP

COM

REFN

DOUT

REFIN

DIN

SCLK

CS/WAKE

SYSTEM

CLOCK

PROGRAMMABLE

OFFSET/CM

1.024V

REFERENCE

BUFFER

10-BIT

ADC

10-BIT

ADC

10-BIT

DAC

10-BIT

DAC

12-BIT

AUX-DAC

12-BIT

AUX-DAC

12-BIT

AUX-DAC

GND

/ 2

DAC1

DAC2

DAC3

ADC1

10-BIT

AUX-ADC

ADC2

OGND

= 2.7V TO 3.3V OV

= 1.8V TO V

DATA MUX

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DA8

DA9

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

MAX19710

DIGITAL

BASEBAND

ASIC

TCXO

TEMPERATURE MEASUREMENT

FDD ZIF

TRANSCEIVER

AGC

BATTERY VOLTAGE MONITOR

______________________________________________________________________________________ 33

MAX19710

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an

actual step width and the ideal value of 1 LSB. A DNL

error specification of less than 1 LSB guarantees no

missing codes (ADC) and a monotonic transfer function

(ADC and DAC) (DAC Figure 14b).

ADC Offset Error

Ideally, the midscale transition occurs at 0.5 LSB above

midscale. The offset error is the amount of deviation

between the measured transition point and the ideal

transition point.

DAC Offset Error

Offset error (Figure 14a) is the difference between the

ideal and actual offset point. The offset point is the out-

put value when the digital input is midscale. This error

affects all codes by the same amount and usually can

be compensated by trimming.

ADC Gain Error

Ideally, the ADC full-scale transition occurs at 1.5 LSB

below full scale. The gain error is the amount of devia-

tion between the measured transition point and the

ideal transition point with the offset error removed.

ADC Dynamic Parameter Definitions

Aperture Jitter

Figure 15 shows the aperture jitter (tAJ), which is the

sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the

rising edge of the sampling clock and the instant when

an actual sample is taken (Figure 15).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital

samples, the theoretical maximum SNR is the ratio of

the full-scale analog input (RMS value) to the RMS

quantization error (residual error) and results directly

from the ADC’s resolution (N bits):

SNR(max) = 6.02 x N + 1.76

(in dB)

In reality, there are other noise sources besides quanti-

zation noise: thermal noise, reference noise, clock jitter,

etc. SNR is computed by taking the ratio of the RMS

signal to the RMS noise. RMS noise includes all spec-

tral components to the Nyquist frequency excluding the

fundamental, the first five harmonics, and the DC offset.

Signal-to-Noise and Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig-

nal to the RMS noise. RMS noise includes all spectral

HOLD

ANALOG

INPUT

SAMPLED

DATA (T/H)

T/H

tAD

tAJ

TRACK TRACK

CLK

Figure 15. T/H Aperture Timing

000 010001 011 100 101 110

AT STEP

011 (0.5 LSB)

AT STEP

001 (0.25 LSB)

111

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE

Figure 14a. Integral Nonlinearity

000 010001 011 100 101

DIFFERENTIAL LINEARITY

ERROR (-0.25 LSB)

DIFFERENTIAL

LINEARITY ERROR (+0.25 LSB)

1 LSB

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE

Figure 14b. Differential Nonlinearity

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 33

34 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

34 ______________________________________________________________________________________

components to the Nyquist frequency excluding the

fundamental and the DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at a

specific input frequency and sampling rate. An ideal

ADC’s error consists of quantization noise only. ENOB for

a full-scale sinusoidal input waveform is computed from:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first five

harmonics of the input signal to the fundamental itself.

This is expressed as:

where V1 is the fundamental amplitude and V2–V6are

the amplitudes of the 2nd- through 6th-order harmonics.

Third Harmonic Distortion (HD3)

HD3 is defined as the ratio of the RMS value of the third

harmonic component to the fundamental input signal.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next-largest spurious

component, excluding DC offset.

Intermodulation Distortion (IMD)

IMD is the total power of the intermodulation products

relative to the total input power when two tones, fIN1

and fIN2, are present at the inputs. The intermodulation

products are (fIN1 ±f

IN2), (2 ✕fIN1), (2 ✕fIN2), (2 ✕fIN1

±f

IN2), (2 ✕fIN2 ±f

IN1). The individual input tone levels

are at -7dBFS.

3rd-Order Intermodulation (IM3)

IM3 is the power of the worst 3rd-order intermodulation

product relative to the input power of either input tone

when two tones, fIN1 and fIN2, are present at the inputs.

The 3rd-order intermodulation products are (2 x fIN1 ±

fIN2), (2 ✕fIN2 ±f

IN1). The individual input tone levels

are at-7dBFS.

Power-Supply Rejection

Power-supply rejection is defined as the shift in offset

and gain error when the power supply is changed ±5%.

Small-Signal Bandwidth

A small -20dBFS analog input signal is applied to an

ADC in such a way that the signal’s slew rate does not

limit the ADC’s performance. The input frequency is

then swept up to the point where the amplitude of the

digitized conversion result has decreased by 3dB. Note

that the T/H performance is usually the limiting factor

for the small-signal input bandwidth.

Full-Power Bandwidth

A large -0.5dBFS analog input signal is applied to an

ADC, and the input frequency is swept up to the point

where the amplitude of the digitized conversion result

has decreased by 3dB. This point is defined as the full-

power bandwidth frequency.

DAC Dynamic Parameter Definitions

Total Harmonic Distortion

THD is the ratio of the RMS sum of the output harmonics

up to the Nyquist frequency divided by the fundamental:

where V1is the fundamental amplitude and V2through

Vn are the amplitudes of the 2nd through nth harmonic

up to the Nyquist frequency.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next-largest distortion

component up to the Nyquist frequency excluding DC.

THD (V + V + ... + V )

⎡

⎣

⎢

⎤

⎦

⎥

20 x log

THD (V +V +V +V +V )

=⎡

⎣

⎢

⎤

⎦

⎥

20 x log

Selector Guide

PART SAMPLING RATE (Msps) INTEGRATED CDMA Tx FILTERS

MAX19710 7.5 No

MAX19711 11 Yes

MAX19712 22 No

MAX19713 45 No

______________________________________________________________________________________ 35

MAX19710

CLK

SERIAL

INTERFACE

AND SYSTEM

CONTROL

IAP

IAN

QAP

QAN

IDP

IDN

QDP

QDN

REFP

REFN

COM

DOUT

REFIN

DIN

SCLK

CS/WAKE

SYSTEM

CLOCK

PROGRAMMABLE

OFFSET/GAIN/CM

1.024V

REFERENCE

BUFFER

10-BIT

ADC

10-BIT

ADC

10-BIT

DAC

10-BIT

DAC

12-BIT

AUX-DAC

12-BIT

AUX-DAC

12-BIT

AUX-DAC

GND

/ 2

DAC1

DAC2

DAC3

ADC1 10-BIT

AUX-ADC

ADC2

OGND

= 2.7V TO 3.3V OV

= 1.8V TO V

DATA MUX

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DA8

DA9

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

MAX19710

Functional Diagram

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________ 35

36 ______________________________________________________________________________________

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

36 ______________________________________________________________________________________

32, 44, 48L QFN.EPS

A1 A

E/2

D/2

DETAIL A

D2/2

E2/2

(NE-1) X e

(ND-1) X e

DETAIL B

PACKAGE OUTLINE

21-0144

32, 44, 48, 56L THIN QFN, 7x7x0.8mm

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

MAX19710

10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

PACKAGE OUTLINE

21-0144

32, 44, 48, 56L THIN QFN, 7x7x0.8mm

Jackson