CY2542C002 - CYPRESS SEMICONDUCTOR

CY7C1380DV33

CY7C1382DV33

18-Mbit (512 K × 36/1 M × 18)

Pipelined SRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-74445 Rev. *D December 29, 2015

18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM

Features

■Supports bus operation up to 200 MHz

■Available speed grades is 200 MHz

■Registered inputs and outputs for pipelined operation

■3.3 V core power supply

■2.5 V or 3.3 V I/O power supply

■Fast clock-to-output times

❐3 ns (for 200 MHz device)

■Provides high performance 3-1-1-1 access rate

■User selectable burst counter supporting IntelPentium®

interleaved or linear burst sequences

■Separate processor and controller address strobes

■Synchronous self-timed write

■Asynchronous output enable

■Single cycle chip deselect

■CY7C1380DV33 is available in JEDEC-standard Pb-free

100-pin TQFP and 165-ball FBGA package and

CY7C1382DV33 is available in 165-ball FBGA package

■IEEE 1149.1 JTAG-Compatible Boundary Scan

■ZZ sleep mode option

Functional Description

The CY7C1380DV33/CY7C1382DV33 SRAM integrates

524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive edge triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining chip enable (CE1), depth-expansion

chip enables (CE2 and CE3 [1]), burst control inputs (ADSC,

ADSP

, and ADV), write enables (BWX, and BWE), and global

write (GW). Asynchronous inputs include the output enable (OE)

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP) or address strobe

controller (ADSC) are active. Subsequent burst addresses can

be internally generated as they are controlled by the advance pin

(ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle.This part supports byte write

operations (see Pin Definitions on page 6 and Truth Table on

page 10 for further details). Write cycles can be one to two or four

bytes wide as controlled by the byte write control inputs. GW

when active LOW causes all bytes to be written.

The CY7C1380DV33/CY7C1382DV33 operates from a +3.3 V

core power supply while all outputs operate with a +2.5 or +3.3 V

power supply. All inputs and outputs are JEDEC-standard and

JESD8-5-compatible.

For a complete list of related documentation, click here.

Selection Guide

Description 200 MHz 167 MHz Unit

Maximum Access Time 3.0 3.4 ns

Maximum Operating Current 300 275 mA

Maximum CMOS Standby Current 70 70 mA

Note

1. CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only.

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 2 of 33

Logic Block Diagram – CY7C1380DV33

Logic Block Diagram – CY7C1382DV33

ADDRESS

ADV

CLK BURST

COUNTER

AND

LOGIC

CLR

ADSP

ADSC

MODE

BWE

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

OUTPUT

BUFFERS

PIPELINED

ENABLE

INPUT

REGISTERS

A0, A1, A

MEMORY

ARRAY

DQs

DQP

SLEEP

CONTROL

[1:0]

A ,

DQP

BYTE

WRITE REGISTER

B ,

DQP

BYTE

WRITE REGISTER

C ,

DQP

BYTE

WRITE REGISTER

D ,

DQP

BYTE

WRITE REGISTER

A ,

DQP

BYTE

WRITE DRIVER

B ,

DQP

BYTE

WRITE DRIVER

C ,

DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

A0, A1, A ADDRESS

ADV

CLK

BURST

COUNTER AND

LOGIC

ADSC

BW B

DQP

WRITE REGISTER

DQP

WRITE REGISTER

ENABLE

SENSE

MEMORY

ARRAY

CE2

CE3

BWE

PIPELINED

ENABLE

DQs

DQP

OUTPUT

INPUT

DQP

WRITE DRIVER

OUTPUT

BUFFERS

DQP

WRITE DRIVER

ZZ SLEEP

CONTROL

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 3 of 33

Contents

Pin Configurations ...........................................................4

Pin Definitions ..................................................................6

Functional Overview ........................................................8

Single Read Accesses ................................................8

Single Write Accesses Initiated by ADSP ................... 8

Single Write Accesses Initiated by ADSC ...................8

Burst Sequences .........................................................8

Sleep Mode .................................................................9

Interleaved Burst Address Table .................................9

Linear Burst Address Table .........................................9

ZZ Mode Electrical Characteristics .............................. 9

Truth Table ......................................................................10

Truth Table for Read/Write ............................................ 11

IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12

Disabling the JTAG Feature ...................................... 12

Test Access Port (TAP) ............................................. 12

PERFORMING A TAP RESET .................................. 12

TAP REGISTERS ...................................................... 12

TAP Instruction Set ................................................... 12

TAP Controller State Diagram ....................................... 14

TAP Controller Block Diagram ...................................... 15

TAP Timing ...................................................................... 15

TAP AC Switching Characteristics ............................... 16

3.3 V TAP AC Test Conditions ....................................... 17

3.3 V TAP AC Output Load Equivalent .........................17

2.5 V TAP AC Test Conditions ....................................... 17

2.5 V TAP AC Output Load Equivalent .........................17

TAP DC Electrical Characteristics and

Operating Conditions ..................................................... 17

Identification Register Definitions ................................ 18

Scan Register Sizes ....................................................... 18

Identification Codes ....................................................... 18

Boundary Scan Order .................................................... 19

Maximum Ratings ........................................................... 20

Operating Range ............................................................. 20

Electrical Characteristics ............................................... 20

Capacitance .................................................................... 21

Thermal Resistance ........................................................ 21

AC Test Loads and Waveforms ..................................... 22

Switching Characteristics .............................................. 23

Switching Waveforms .................................................... 24

Ordering Information ...................................................... 28

Ordering Code Definitions ......................................... 28

Package Diagrams .......................................................... 29

Acronyms ........................................................................ 31

Document Conventions ................................................. 31

Units of Measure ....................................................... 31

Document History Page ................................................. 32

Sales, Solutions, and Legal Information ...................... 33

Worldwide Sales and Design Support ....................... 33

Products .................................................................... 33

PSoC® Solutions ...................................................... 33

Cypress Developer Community ................................. 33

Technical Support ..................................................... 33

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 4 of 33

Pin Configurations

Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable)

CY7C1380DV33 (512 K × 36)

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 5 of 33

Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable)

CY7C1380DV33 (512 K × 36)

CY7C1382DV33 (1 M × 18)

Pin Configurations (continued)

234 5671

TDO

NC/288M

NC/144M

DQPC

DQC

DQPD

DQD

CE1BWB CE3

BWCBWE

ACE2

DQC

DQD

MODE

DQC

DQD

NC/36M

NC/72M

VDDQ

BWDBWACLK GW

VSS VSS VSS VSS

VDDQ VSS

VDD VSS

VSS

VDDQ

VDD VSS

VDD VSS VSS

VDDQ VDD

VSS

VDD

VSS

VDD VSS VSS

VSS

VDD

VDD VSS

VDD VSS VSS

TCK

VSS

TDI

DQCVSS

DQC

VSS

DQD

VDDQ

VSS

TMS

891011

ADV A

ADSC NC

OE ADSP ANC/576M

VSS VDDQ NC/1G DQPB

VDDQ

VDD DQB

DQB

DQA

VDD VDDQ

VDD VDDQ DQB

VDD

DQA

VDD VDDQ DQA

VDDQ

VDD

VDD VDDQ

VDD VDDQ DQA

VDDQ

VSS

DQB

DQA

DQPA

DQA

VDDQ

VSS

234 5671

TDO

NC/288M

NC/144M

DQPB

DQB

ACE1NC CE3

BWBBWE

ACE2

DQB

MODE

DQB

NC/36M

NC/72M

VDDQ

NC BWACLK GW

VSS VSS VSS VSS

VDDQ VSS

VDD VSS

VSS

VDDQ

VDD VSS

VDD VSS VSS

VDDQ VDD

VSS

VDD

VSS

VDD VSS VSS

VSS

VDD

VDD VSS

VDD VSS VSS

TCKA0

VSS

TDI

DQBVSS

NC VSS

DQB

VSS

DQB

VDDQ

VSS

TMS

891011

ADV A

ADSC A

OE ADSP ANC/576M

VSS VDDQ NC/1G DQPA

VDDQ

VDD NC

DQA

VDD VDDQ

VDD VDDQ DQA

VDD

NCVDD VDDQ DQA

VDDQ

VDD

VDD VDDQ

VDD VDDQ NC

VDDQ

VSS

DQA

VDDQ

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 6 of 33

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK

if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [3]are sampled active. A1:A0 are fed to the

two-bit counter.

BWA, BWB,

BWC, BWD

Input-

Synchronous

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled

on the rising edge of CLK.

GW Input-

Synchronous

Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write

is conducted (all bytes are written, regardless of the values on BWX and BWE).

BWE Input-

Synchronous

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted

LOW to conduct a byte write.

CLK Input-

Clock

Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV is asserted LOW, during a burst operation.

CE1Input-

Synchronous

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2

and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a

new external address is loaded.

CE2 [2] Input-

Synchronous

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1

and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.

CE3 [2] Input-

Synchronous

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1

and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.

OE Input-

Asynchronou

Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,

the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data

pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

ADV Input-

Synchronous

Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP Input-

Synchronous

Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is

ignored when CE1 is deasserted HIGH.

ADSC Input-

Synchronous

Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

ZZ Input-

Asynchronou

ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition with data

integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal

pull down.

DQs,

DQPX

I/O-

Synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

addresses presented during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX

are placed in a tri-state condition.

VDD Power Supply Power supply inputs to the core of the device

VSS Ground Ground for the core of the device.

VSSQ I/O Ground Ground for the I/O circuitry.

Note

2. CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in 1-chip enable.

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 7 of 33

VDDQ I/O Power

Supply

Power supply for the I/O circuitry.

MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating

selects interleaved burst sequence. This is a strap pin and must remain static during device operation.

Mode pin has an internal pull up.

TDO JTAG serial

output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is

not being utilized, this pin must be disconnected. This pin is not available on 100-pin TQFP packages.

TDI JTAG serial

input

Synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being

utilized, this pin can be disconnected or connected to VDD. This pin is not available on 100-pin TQFP

packages.

TMS JTAG serial

input

Synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being

utilized, this pin can be disconnected or connected to VDD. This pin is not available on 100-pin TQFP

packages.

TCK JTAG-

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected

to VSS. This pin is not available on 100-pin TQFP packages.

NC – No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally

connected to the die.

Pin Definitions (continued)

Name I/O Description

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 8 of 33

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

access delay from the clock rise (tCO) is 3 ns (200 MHz device).

CY7C1380DV33/CY7C1382DV33 supports secondary cache in

systems using a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486 processors.

The linear burst sequence suits processors that use a linear

burst sequence. The burst order is user selectable, and is

determined by sampling the MODE input. Accesses can be

initiated with either the processor address strobe (ADSP) or the

controller address strobe (ADSC). Address advancement

through the burst sequence is controlled by the ADV input. A

two-bit on-chip wraparound burst counter captures the first

address in a burst sequence and automatically increments the

address for the rest of the burst access.

Byte write operations are qualified with the byte write enable

(BWE) and byte write select (BWX) inputs. A global write enable

(GW) overrides all byte write inputs and writes data to all four

bytes. All writes are simplified with on-chip synchronous

self-timed write circuitry.

Three synchronous chip selects (CE1, CE2, CE3) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE1 is

HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

(2) CE1, CE2, CE3 are all asserted active, and (3) the write

signals (GW, BWE) are all deserted HIGH. ADSP is ignored if

CE1 is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the address

corresponding data is enabled to propagate to the input of the

output registers. At the rising edge of the next clock, the data is

enabled to propagate through the output register and onto the

data bus within 3 ns (200 MHz device) if OE is active LOW. The

only exception occurs when the SRAM is emerging from a

deselected state to a selected state; its outputs are always

tri-stated during the first cycle of the access. After the first cycle

of the access, the outputs are controlled by the OE signal.

Consecutive single read cycles are supported. Once the SRAM

is deselected at clock rise by the chip select and either ADSP or

ADSC signals, its output tri-states immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both the following conditions are

satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE1,

CE2, and CE3 are all asserted active. The address presented to

A is loaded into the address register and the address

advancement logic while being delivered to the memory array.

The write signals (GW, BWE, and BWX) and ADV inputs are

ignored during this first cycle.

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the

corresponding address location in the memory array. If GW is

HIGH, then the write operation is controlled by BWE and BWX

signals.

CY7C1380DV33/CY7C1382DV33 provides byte write capability

that is described in the write cycle descriptions table. Asserting

the byte write enable input (BWE) with the selected byte write

(BWX) input, selectively writes to only the desired bytes. Bytes

not selected during a byte write operation remain unaltered. A

synchronous self-timed write mechanism has been provided to

simplify the write operations.

CY7C1380DV33/CY7C1382DV33 is a common I/O device, the

output enable (OE) must be deserted HIGH before presenting

data to the DQs inputs. Doing so tri-states the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever a

write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following conditions

are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted

HIGH, (3) CE1, CE2, and CE3 are all asserted active, and (4) the

appropriate combination of the write inputs (GW, BWE, and

BWX) are asserted active to conduct a write to the desired

byte(s). ADSC-triggered Write accesses require a single clock

cycle to complete. The address presented to A is loaded into the

address register and the address advancement logic while being

delivered to the memory array. The ADV input is ignored during

this cycle. If a global write is conducted, the data presented to

the DQs is written into the corresponding address location in the

memory core. If a byte write is conducted, only the selected bytes

are written. Bytes not selected during a byte write operation

remain unaltered. A synchronous self-timed write mechanism

has been provided to simplify the write operations.

CY7C1380DV33/CY7C1382DV33 is a common I/O device, the

output enable (OE) must be deserted HIGH before presenting

data to the DQs inputs. Doing so tri-states the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever a

write cycle is detected, regardless of the state of OE.

Burst Sequences

CY7C1380DV33/CY7C1382DV33 provides a two-bit

wraparound counter, fed by A1:A0, that implements an

interleaved or a linear burst sequence. The interleaved burst

sequence is designed specifically to support Intel Pentium

applications. The linear burst sequence is designed to support

processors that follow a linear burst sequence. The burst

sequence is user selectable through the MODE input.

Asserting ADV LOW at clock rise automatically increments the

burst counter to the next address in the burst sequence. Both

read and write burst operations are supported.

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 9 of 33

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation sleep mode. Two clock cycles

are required to enter into or exit from this sleep mode. While in

this mode, data integrity is guaranteed. Accesses pending when

entering the sleep mode are not considered valid nor is the

completion of the operation guaranteed. The device must be

deselected prior to entering the sleep mode. CE1, CE2, CE3,

ADSP, and ADSC must remain inactive for the duration of tZZREC

after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 80 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns

tZZI ZZ Active to sleep current This parameter is sampled – 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 10 of 33

Truth Table

The Truth Table for this data sheet follows. [3, 4, 5, 6, 7]

Operation Address Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power Down None H X X L X L X X X L–H Tri-state

Deselect Cycle, Power Down None L L X L L X X X X L–H Tri-state

Deselect Cycle, Power Down None L X H L L X X X X L–H Tri-state

Deselect Cycle, Power Down None L L X L H L X X X L–H Tri-state

Deselect Cycle, Power Down None L X H L H L X X X L–H Tri-state

Sleep Mode, Power Down None X X X H X X X X X X Tri-state

READ Cycle, Begin Burst External L H L L L X X X L L–H Q

READ Cycle, Begin Burst External L H L L L X X X H L–H Tri-state

WRITE Cycle, Begin Burst External L H L L H L X L X L–H D

READ Cycle, Begin Burst External L H L L H L X H L L–H Q

READ Cycle, Begin Burst External L H L L H L X H H L–H Tri-state

READ Cycle, Continue Burst Next X X X L H H L H L L–H Q

READ Cycle, Continue Burst Next X X X L H H L H H L–H Tri-state

READ Cycle, Continue Burst Next H X X L X H L H L L–H Q

READ Cycle, Continue Burst Next H X X L X H L H H L–H Tri-state

WRITE Cycle, Continue Burst Next X X X L H H L L X L–H D

WRITE Cycle, Continue Burst Next H X X L X H L L X L–H D

READ Cycle, Suspend Burst Current X X X L H H H H L L–H Q

READ Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-state

READ Cycle, Suspend Burst Current H X X L X H H H L L–H Q

READ Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-state

WRITE Cycle, Suspend Burst Current X X X L H H H L X L–H D

WRITE Cycle, Suspend Burst Current H X X L X H H L X L–H D

Notes

3. X = Don't Care, H = Logic HIGH, L = Logic LOW.

4. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after

the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care

for the remainder of the write cycle.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 11 of 33

Truth Table for Read/Write

The Truth Table for Read/Write for CY7C1380DV33 follows. [8, 9]

Function (CY7C1380DV33) GW BWE BWDBWCBWBBWA

Read H H X X X X

Read HLHHHH

Write Byte A – (DQA and DQPA)HLHHHL

Write Byte B – (DQB and DQPB)HLHHLH

Write Bytes B, A H L H H L L

Write Byte C – (DQC and DQPC)HLHLHH

Write Bytes C, A H L H L H L

Write Bytes C, B H L H L L H

Write Bytes C, B, A H L H L L L

Write Byte D – (DQD and DQPD)HLLHHH

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

Write Bytes D, C, B H L L L L H

Write All Bytes H L L L L L

Write All Bytes L X X X X X

Truth Table for Read/Write

The Truth Table for Read/Write for CY7C1382DV33 follows. [8, 9]

Function (CY7C1382DV33) GW BWE BWBBWA

Read H H X X

Read H L H H

Write Byte A – (DQA and DQPA)HLHL

Write Byte B – (DQB and DQPB)HLLH

Write Bytes B, A H L L L

Write All Bytes H L L L

Write All Bytes L X X X

Notes

8. X = Don't Care, H = Logic HIGH, L = Logic LOW.

9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 12 of 33

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1380DV33/CY7C1382DV33 incorporates a serial

boundary scan test access port (TAP).This part is fully compliant

with 1149.1. The TAP operates using JEDEC-standard 3.3 V or

2.5 V I/O logic levels.

CY7C1380DV33/CY7C1382DV33 contains a TAP controller,

instruction register, boundary scan register, bypass register, and

ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may

alternately be connected to VDD through a pull up resistor. TDO

must be left unconnected. Upon power up, the device comes up

in a reset state which does not interfere with the operation of the

device.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. This pin may be left

unconnected if the TAP is not used. The ball is pulled up

internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers

and can be connected to the input of any of the registers. The

is loaded into the TAP instruction register. For information about

loading the instruction register, see the TAP Controller State

Diagram on page 14. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) of any register.

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current state

of the TAP state machine (see Identification Codes on page 18).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising

edges of TCK. This Reset does not affect the operation of the

SRAM and may be performed while the SRAM is operating.

At power up, the TAP is reset internally to ensure that TDO

comes up in a high Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and

enable data to be scanned in and out of the SRAM test circuitry.

Only one register can be selected at a time through the

instruction register. Data is serially loaded into the TDI ball on the

rising edge of TCK. Data is output on the TDO ball on the falling

edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

and TDO balls as shown in the TAP Controller Block Diagram on

page 15. Upon power up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as described

in the previous section.

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary ‘01’ pattern to enable fault

isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This enables data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW (VSS)

when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the

RAM input and output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and TDO

balls when the controller is moved to the Shift-DR state. The

EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can

be used to capture the contents of the input and output ring.

The boundary scan order tables show the order in which the bits

are connected. Each bit corresponds to one of the bumps on the

SRAM package. The MSB of the register is connected to TDI,

and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in the Identification Register Definitions on

page 18.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit

instruction register. All combinations are listed in Identification

Codes on page 18. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions

are described in detail in this section.

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO balls. To execute

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the instruction once it is shifted in, the TAP controller must be

moved into the Update-IR state.

EXTEST

The EXTEST instruction enables the preloaded data to be driven

out through the system output pins. This instruction also selects

the boundary scan register to be connected for serial access

between the TDI and TDO in the Shift-DR controller state.

IDCODE

The IDCODE instruction causes a vendor-specific 32-bit code to

be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and enables

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register

upon power up or whenever the TAP controller is given a test

logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to

be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. The SAMPLE Z command places

all SRAM outputs into a high Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the input and output pins is captured

in the boundary scan register.

The TAP controller clock can only operate at a frequency up to

20 MHz, while the SRAM clock operates more than an order of

magnitude faster. As there is a large difference in the clock

frequencies, it is possible that during the Capture-DR state, an

input or output undergoes a transition. The TAP may then try to

capture a signal while in transition (metastable state). This does

not harm the device, but there is no guarantee as to the value

that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture setup plus hold

times (tCS and tCH). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the CK and CK# captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

PRELOAD enables an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells prior

to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required; that is, while data captured is

shifted out, the preloaded data is shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO balls. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able

to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at Bit #89

(for 165-ball FBGA package). When this scan cell, called the

“extest output bus tri-state,” is latched into the preload register

during the Update-DR state in the TAP controller, it directly

controls the state of the output (Q-bus) pins, when the EXTEST

is entered as the current instruction. When HIGH, it enables the

output buffers to drive the output bus. When LOW, this bit places

the output bus into a high Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that cell,

during the Shift-DR state. During Update-DR, the value loaded

into that shift-register cell latches into the preload register. When

the EXTEST instruction is entered, this bit directly controls the

output Q-bus pins. Note that this bit is preset HIGH to enable the

output when the device is powered up, and also when the TAP

controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

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TAP Controller State Diagram

The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1 1

0 0

1 1

0 0

1 0

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TAP Controller Block Diagram

Bypass Register

Instruction Register

012

Identiﬁcation Register

012293031 ...

Boundary Scan Register

012..x ...

Selection

Circuitry

Selection

Circuitry

TCK

TMS TAP CONTROLLER

TDI TDO

TAP Timing

Figure 3. TAP Timing

tTL

Test Clock

(TCK)

Test Mode Select

(TMS)

tTH

Test Data-Out

(TDO)

tCYC

Test Data-In

(TDI)

tTMSH

tTMSS

tTDIH

tTDIS

tTDOX

tTDOV

DON’T CARE UNDEFINED

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TAP AC Switching Characteristics

Over the Operating Range

Parameter [10, 11] Description Min Max Unit

Clock

tTCYC TCK Clock Cycle Time 50 –ns

tTF TCK Clock Frequency –20 MHz

tTH TCK Clock HIGH time 20 –ns

tTL TCK Clock LOW time 20 –ns

Output Times

tTDOV TCK Clock LOW to TDO Valid –10 ns

tTDOX TCK Clock LOW to TDO Invalid 0 – ns

Setup Times

tTMSS TMS Setup to TCK Clock Rise 5 – ns

tTDIS TDI Setup to TCK Clock Rise 5 – ns

tCS Capture Setup to TCK Rise 5 – ns

Hold Times

tTMSH TMS Hold after TCK Clock Rise 5 – ns

tTDIH TDI Hold after Clock Rise 5 – ns

tCH Capture Hold after Clock Rise 5 – ns

Notes

10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

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3.3 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 3.3 V

Input rise and fall times ...................................................1 ns

Input timing reference levels ......................................... 1.5 V

Output reference levels ................................................ 1.5 V

Test load termination supply voltage ............................ 1.5 V

3.3 V TAP AC Output Load Equivalent

2.5 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 2.5 V

Input rise and fall time ....................................................1 ns

Input timing reference levels ....................................... 1.25 V

Output reference levels .............................................. 1.25 V

Test load termination supply voltage .......................... 1.25 V

2.5 V TAP AC Output Load Equivalent

TDO

1.5V

20pF

Z = 50 Ω

50Ω

TDO

1.25V

20pF

Z = 50 Ω

50Ω

TAP DC Electrical Characteristics and Operating Conditions

(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)

Parameter [12] Description Test Conditions Min Max Unit

VOH1 Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3 V 2.4 – V

IOH = –1.0 mA, VDDQ = 2.5 V 2.0 – V

VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3 V 2.9 – V

VDDQ = 2.5 V 2.1 – V

VOL1 Output LOW Voltage IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V

VDDQ = 2.5 V – 0.4 V

VOL2 Output LOW Voltage IOL = 100 µA VDDQ = 3.3 V – 0.2 V

VDDQ = 2.5 V – 0.2 V

VIH Input HIGH Voltage VDDQ = 3.3 V 2.0 VDD + 0.3 V

VDDQ = 2.5 V 1.7 VDD + 0.3 V

VIL Input LOW Voltage VDDQ = 3.3 V –0.3 0.8 V

VDDQ = 2.5 V –0.3 0.7 V

IXInput Load Current GND < VIN < VDDQ –5 5 µA

Note

12. All voltages referenced to VSS (GND).

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Identification Register Definitions

Instruction Field CY7C1380DV33

(512 K × 36)

CY7C1382DV33

(1 M × 18) Description

Revision Number (31:29) 000 000 Describes the version number.

Device Depth (28:24) [13] 01011 01011 Reserved for internal use.

Device Width (23:18) 165-ball FBGA 000000 000000 Defines the memory type and

architecture.

Cypress Device ID (17:12) 100101 010101 Defines the width and density.

Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM

vendor.

ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID

Scan Register Sizes

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan Order (165-ball FBGA package) 89 89

Identification Codes

Instruction Code Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces

all SRAM outputs to high Z state.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operations.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces

all SRAM output drivers to a high Z state.

RESERVED 011 Do Not Use. This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does

not affect SRAM operation.

RESERVED 101 Do Not Use. This instruction is reserved for future use.

RESERVED 110 Do Not Use. This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Note

13. Bit #24 is 1 in the register definitions for both 2.5 V and 3.3 V versions of this device.

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Boundary Scan Order

165-ball BGA [14, 15]

Bit # Ball ID Bit # Ball ID Bit # Ball ID

1N6 31D10 61G1

2N7 32C11 62D2

3 N10 33 A11 63 E2

4P11 34B11 64F2

5 P8 35 A10 65 G2

6 R8 36 B10 66 H1

7R9 37A9 67H3

8P9 38B9 68J1

9 P10 39 C10 69 K1

10 R10 40 A8 70 L1

11 R11 41 B8 71 M1

12 H11 42 A7 72 J2

13N11 43B7 73K2

14 M11 44 B6 74 L2

15 L11 45 A6 75 M2

16 K11 46 B5 76 N1

17 J11 47 A5 77 N2

18M10 48A4 78P1

19 L10 49 B4 79 R1

20 K10 50 B3 80 R2

21J10 51A3 81P3

22 H9 52 A2 82 R3

23H10 53B2 83P2

24G11 54C2 84R4

25F11 55B1 85P4

26 E11 56 A1 86 N5

27 D11 57 C1 87 P6

28G10 58D1 88R6

29 F10 59 E1 89 Internal

30 E10 60 F1

Note

14. Balls which are NC (No Connect) are pre-set LOW.

15. Bit# 89 is pre-set HIGH.

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Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the

device. For user guidelines, not tested.

Storage Temperature ............................... –65 °C to +150 °C

Ambient Temperature with

Power Applied ......................................... –55 °C to +125 °C

Supply Voltage on

VDD Relative to GND ...................................–0.3 V to +4.6 V

Supply Voltage on

VDDQ Relative to GND .................................. –0.3 V to +VDD

DC Voltage Applied to Outputs

in tri-state ..........................................–0.5 V to VDDQ + 0.5 V

DC Input Voltage ................................ –0.5 V to VDD + 0.5 V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage

(per MIL-STD-883, Method 3015) .......................... > 2001 V

Latch-up Current .................................................... > 200 mA

Operating Range

Range Ambient

Temperature VDD VDDQ

Industrial –40 °C to +85 °C 3.3 V– 5% /

+ 10%

2.5 V – 5% to

VDD

Electrical Characteristics

Over the Operating Range

Parameter [16, 17] Description Test Conditions Min Max Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage for 3.3 V I/O 3.135 VDD V

for 2.5 V I/O 2.375 2.625 V

VOH Output HIGH Voltage for 3.3 V I/O, IOH = –4.0 mA 2.4 – V

for 2.5 V I/O, IOH = –1.0 mA 2.0 – V

VOL Output LOW Voltage for 3.3 V I/O, IOL = 8.0 mA – 0.4 V

for 2.5 V I/O, IOL = 1.0 mA – 0.4 V

VIH Input HIGH Voltage [17] for 3.3 V I/O 2.0 VDD + 0.3 V

for 2.5 V I/O 1.7 VDD + 0.3 V

VIL Input LOW Voltage [17] for 3.3 V I/O –0.3 0.8 V

for 2.5 V I/O –0.3 0.7 V

IXInput Leakage Current except ZZ

and MODE

GND  VI  VDDQ –5 5 A

Input Current of MODE Input = VSS –30 – A

Input = VDD –5A

Input Current of ZZ Input = VSS –5 – A

Input = VDD –30A

IOZ Output Leakage Current GND  VI  VDDQ, Output Disabled –5 5 A

IDD VDD Operating Supply Current VDD = Max, IOUT = 0 mA,

f = fMAX = 1/tCYC

5.0-ns cycle,

200 MHz

–300mA

6.0-ns cycle,

167 MHz

–275mA

ISB1 Automatic CE power-down

Current – TTL Inputs

VDD = Max, Device Deselected,

VIN  VIH or VIN  VIL,

f = fMAX = 1/tCYC

5.0-ns cycle,

200 MHz

–150mA

6.0-ns cycle,

167 MHz

–140mA

Notes

16. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).

17. TPower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

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ISB2 Automatic CE power-down

Current – CMOS Inputs

VDD = Max, Device Deselected,

VIN  0.3 V or

VIN > VDDQ – 0.3 V,

f = 0

All speeds – 70 mA

ISB3 Automatic CE power-down

Current – CMOS Inputs

VDD = Max, Device Deselected,

VIN  0.3 V or

VIN > VDDQ – 0.3 V,

f = fMAX = 1/tCYC

5.0-ns cycle,

200 MHz

–130mA

6.0-ns cycle,

167 MHz

–125mA

ISB4 Automatic CE power-down

Current – TTL Inputs

VDD = Max, Device Deselected,

VIN  VIH or VIN  VIL, f = 0

All speeds – 80 mA

Electrical Characteristics (continued)

Over the Operating Range

Parameter [16, 17] Description Test Conditions Min Max Unit

Capacitance

Parameter [18] Description Test Conditions 100-pin TQFP

Package

165-ball FBGA

Package Unit

CIN Input Capacitance TA = 25 °C, f = 1 MHz,

VDD = 3.3 V, VDDQ = 2.5 V

59pF

CCLK Clock Input Capacitance 5 9 pF

CIO Input/Output Capacitance 5 9 pF

Thermal Resistance

Parameter [18] Description Test Conditions 100-pin TQFP

Package

165-ball FBGA

Package Unit

JA Thermal resistance

(junction to ambient)

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, in accordance with

EIA/JESD51.

28.66 20.7 °C/W

JC Thermal resistance

(junction to case)

4.08 4.0 °C/W

Note

18. Tested initially and after any design or process change that may affect these parameters.

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AC Test Loads and Waveforms

Figure 4. AC Test Loads and Waveforms

OUTPUT

R = 317 

R = 351 

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50 

Z0= 50 

= 1.5 V

3.3 V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

1 ns 1 ns

(c)

OUTPUT

R = 1667 

R = 1538 

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50 

Z0= 50 

VT= 1.25 V

2.5 V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

1 ns 1 ns

(c)

3.3 V I/O Test Load

2.5 V I/O Test Load

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Switching Characteristics

Over the Operating Range

Parameter [19, 20] Description 200 MHz 167 MHz Unit

Min Max Min Max

tPOWER VDD(typical) to the first access [21] 1–1–ms

Clock

tCYC Clock Cycle Time 5 – 6 – ns

tCH Clock HIGH 2.0 – 2.2 – ns

tCL Clock LOW 2.0 – 2.2 – ns

Output Times

tCO Data Output Valid After CLK Rise – 3.0 – 3.4 ns

tDOH Data Output Hold After CLK Rise 1.3 – 1.3 – ns

tCLZ Clock to Low Z [22, 23, 24] 1.3–1.3–ns

tCHZ Clock to High Z [22, 23, 24] – 3.0 – 3.4 ns

tOEV OE LOW to Output Valid – 3.0 – 3.4 ns

tOELZ OE LOW to Output Low Z [22, 23, 24] 0–0–ns

tOEHZ OE HIGH to Output High Z [22, 23, 24] – 3.0 – 3.4 ns

Setup Times

tAS Address Setup Before CLK Rise 1.4 – 1.5 – ns

tADS ADSC, ADSP Setup Before CLK Rise 1.4 – 1.5 – ns

tADVS ADV Setup Before CLK Rise 1.4 – 1.5 – ns

tWES GW, BWE, BWX Setup Before CLK Rise 1.4 – 1.5 – ns

tDS Data Input Setup Before CLK Rise 1.4 – 1.5 – ns

tCES Chip Enable SetUp Before CLK Rise 1.4 – 1.5 – ns

Hold Times

tAH Address Hold After CLK Rise 0.4 – 0.5 – ns

tADH ADSP, ADSC Hold After CLK Rise 0.4 – 0.5 – ns

tADVH ADV Hold After CLK Rise 0.4 – 0.5 – ns

tWEH GW, BWE, BWX Hold After CLK Rise 0.4 – 0.5 – ns

tDH Data Input Hold After CLK Rise 0.4 – 0.5 – ns

tCEH Chip Enable Hold After CLK Rise 0.4 – 0.5 – ns

Notes

19. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.

20. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted.

21. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can

be initiated.

22. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 22. Transition is measured ±200 mV from steady-state voltage.

23. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

high Z prior to low Z under the same system conditions.

24. This parameter is sampled and not 100% tested.

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Switching Waveforms

Figure 5. Read Cycle Timing [25]

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,

BWx

Data Out (Q) High-Z

tCLZ

tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

ADV

suspends

burst.

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1) Q(A2) Q(A2 + 1)Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

DON’T CARE UNDEFINED

Note

25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

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Figure 6. Write Cycle Timing [26, 27]

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

Data Out (Q)

High-Z

ADV

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Data In (D)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

ADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are

ignored for ﬁrst cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

Notes

26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

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Document Number: 001-74445 Rev. *D Page 26 of 33

Figure 7. Read/Write Cycle Timing [28, 29, 30]

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

Data Out (Q) High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

Notes

28. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

29. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

30. GW is HIGH.

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Document Number: 001-74445 Rev. *D Page 27 of 33

Figure 8. ZZ Mode Timing [31, 32]

Switching Waveforms (continued)

tZZ

SUPPLY

CLK

tZZREC

ALL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

Notes

31. Device must be deselected when entering ZZ mode. See Truth Table on page 10 for all possible signal conditions to deselect the device.

32. DQs are in high Z when exiting ZZ sleep mode.

CY7C1380DV33

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Document Number: 001-74445 Rev. *D Page 28 of 33

Ordering Information

The below table lists the key package features and ordering codes. The table contains only the parts that are currently available. If

you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at

www.cypress.com and refer to the product summary page at http://www.cypress.com/products.

Ordering Code Definitions

Speed

(MHz) Ordering Code

Package

Diagram Part and Package Type Operating

Range

200 CY7C1380DV33-200AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Industrial

CY7C1382DV33-200BZI 51-85180 165-ball FBGA (13 × 15 × 1.4 mm)

Temperature Range:

I = Industrial

Pb-free

Package Type: XX = A or BZ

A = 100-pin TQFP; BZ = 165-ball FBGA

Frequency Range: XXX = 200 MHz

V33 = 3.3 V

Die Revision:

D  90 nm

Part Identifier: 138X = 1380 or 1382

1380 = SCD, 512 K × 36 (18 Mb)

1382 = SCD, 1 Mb × 18 (18 Mb)

Technology Code: C = CMOS

Marketing Code: 7 = SRAM

Company ID: CY = Cypress

CCY 138X D - XXX I

XX7X

V33

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 29 of 33

Package Diagrams

Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85050

51-85050 *E

CY7C1380DV33

CY7C1382DV33

Document Number: 001-74445 Rev. *D Page 30 of 33

Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180

Package Diagrams (continued)

51-85180 *G

CY7C1380DV33

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Document Number: 001-74445 Rev. *D Page 31 of 33

Acronyms Document Conventions

Units of Measure

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

EIA Electronic Industries Alliance

FBGA Fine-Pitch Ball Grid Array

I/O Input/Output

JEDEC Joint Electron Devices Engineering Council

JTAG Joint Test Action Group

LSB Least Significant Bit

MSB Most Significant Bit

OE Output Enable

SRAM Static Random Access Memory

TCK Test Clock

TDI Test Data-In

TDO Test Data-Out

TMS Test Mode Select

TQFP Thin Quad Flat Pack

TTL Transistor-Transistor Logic

Symbol Unit of Measure

°C degree Celsius

MHz megahertz

µA microampere

mA milliampere

mm millimeter

ms millisecond

ns nanosecond

ohm

% percent

pF picofarad

Vvolt

Wwatt

CY7C1380DV33

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Document Number: 001-74445 Rev. *D Page 32 of 33

Document History Page

Document Title: CY7C1380DV33/CY7C1382DV33, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM

Document Number: 001-74445

Rev. ECN No. Submission

Date

Orig. of

Change Description of Change

** 3420399 12/21/2011 NJY New data sheet

*A 3514252 02/02/2012 NJY Changed status from Preliminary to Final.

Updated Functional Description (Updated Note 1).

Updated Selection Guide (Included 167 MHz information).

Updated Pin Configurations (Included 100-pin TQFP information).

Updated Pin Definitions (Updated Note 2 and included 100-pin TQFP

information).

Updated Operating Range (Removed Commercial Temperature information).

Updated Electrical Characteristics (Included 167 MHz information).

Updated Capacitance (Included 100-pin TQFP information).

Updated Thermal Resistance (Included 100-pin TQFP information).

Updated Switching Characteristics (Included 167 MHz information).

Updated Ordering Information.

Updated Package Diagrams.

*B 4194894 11/18/2013 PRIT Updated Package Diagrams:

spec 51-85180 – Changed revision from *E to *F.

Updated to new template.

Completing Sunset Review.

*C 4575228 11/20/2014 PRIT Updated Functional Description:

Added “For a complete list of related documentation, click here.” at the end.

Updated Ordering Information:

Updated part numbers.

Updated Package Diagrams:

spec 51-85050 – Changed revision from *D to *E.

*D 5067400 12/29/2015 PRIT Updated Package Diagrams:

spec 51-85180 – Changed revision from *F to *G.

Updated to new template.

Completing Sunset Review.

Document Number: 001-74445 Rev. *D Revised December 29, 2015 Page 33 of 33

All products and company names mentioned in this document may be the trademarks of their respective holders.

CY7C1380DV33

CY7C1382DV33

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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