AN397 - STMicroelectronics

March 1999 1/5

AN397

APPLICATION NOTE

Timing Speci fications for Memory Products

STMicroelectronics has, for m any ye ars, committed itself to t he JEDEC nam ing convent ion for the timing

parameters of its memory products. Historically, timing parameter names had te nded towards describ ing

the function that was being performed durin g the time interval, for examp le:

–t

AH to represent the Address Hold time

–t

DH to represent the Data Hold time

–t

ACC to represent the Access time

However, the se nam es are ambi guous. The y do not spec ify which signals a re used t o indicate t he start

and end events, and they do not specify which transitions are involved. For example, tACC does not spec-

ify, whethe r t his is th e tim e f rom addre sses becom ing valid, or fro m the Chi p E nabl e be co ming enabled,

or from the Chip Enable ceasi ng to be disabled.

Under the JEDEC system, timing parameter names are composed from the names of the signals involved,

and their co rresponding logic transition s. They take the general form, t1234, where 1 and 3 specify two

signal nam es, an d 2 an d 4 specify the log ic transitions. E ach timi ng period consists of a s tart event , as

specified by a g iven logic transition-2 on sig nal-1, and an end eve nt, as spec ified by a given logic transi-

tion -4 on signal-3 .

To help in keeping the nam es of the timi ng periods consist ent between designers , there are convent ions

on how th e signal names, 1 and 3, shoul d be c hosen, and on how th e trans ition na mes, 2 and 4, should

be specified. The core of the signal naming system is as follows:

– Q to represent a Data Output

– D to represent a Data Input

– A to represe nt an Address Line

– E to represe nt a Chip Enable Input

– G to represent a, Output Enable Input

– W to represent a Write Enable Input

These are shown in use for the example m emory device in Figure 1.

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Figure 1. Signal Names on an Exampl e Memo ry Device

The naming convention for the transitio ns is as follows:

– H indicates the earliest moment at w hich the si gnal can be consi dered to b e driven in the high logic

state (for example, as a res ul t of a low-to-high transition).

– L indicates the earliest moment at which the signal can be considered to be driven in the low logic state

(for example, as a result of a hig h-to-low transition).

– V indicat es the earlies t moment at which the signal can be considered to be driven in a valid logic stat e,

either high or low (for example, as a result of coming out of a high-to-low, or low-to-high transition,

passing through the invalid state in between).

– X indicates the earliest moment at which the signal can be con sidered to be driven in the invalid logic

state (between VIL and V IH in Figure 2), neither high nor low (for example, as a result of going into a

high-to-low, or l ow-to-high transition, passing through the i nvalid state in between).

– Z indicates earliest mom ent at which the signal can be conside re d t o be undriven, and left floating in

its high i mpedance state.

Figure 2. Logic State Transitions on Example Input and Output Waveforms

AI00708B

A0-A14

DQ0-DQ7

VPP

VCC

VSS

AI00830B

VOH

VOL

Transition (x)

VIH

VIL

VOH

VOL

Valid

VIH

VIL Valid

VOH

VOL

High

Low

VIH

VIL

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AN397 - APPLICATION NOTE

EXAMPLES

The parameter tAVQV specifies a time interv al: starting from the i ns tant wh en the address lines are below

VIL (for signals at, or g oing to a logic Low level)

above VIH (for those at, or going to a High logic level);

and ending at the instant when the data output signals are all below VIL or abov e VIH.

The parameter tEHQZ specifies a time interval: starting from the instant when the Chip Enab le input goes

above VIH; and endi ng at the instant when the data output is no longer driven.

The paramet er tAXQX specifies a time interval: starting from t he instant when any single address li ne goes

outside its stable, valid le vel; and ending at the instant when any data outpu t line transition passes these

levels, and is consequently no longer valid.

Some further examples are shown in the first column of Table 1. The second column indicates the old style

of name for the same parameter. As can be seen in some of the names, the inversion bar is always omit ted

from signals that use negati ve logic. For example, E from Figure 1 appears as E in tELQX in Table 1.

Table 1. Timing Characteristics Example

No te s: 1. Th ese are taken from the FLA S H Memory data sheets.

MEASUREMENT CONDIT IONS

There are a few other parameters that need to be includ ed in the data sheets, to make t he specification

complete. Firstly, the limits on the output levels, as used in Figure 2, need specifying:

VOH ≥ 0.8 VCC

VOL ≤ 0.2 VCC

Next, the th resholds reco gnized by the input buffers, again as used in Figure 2, need specifying:

VIH ≥ 0.7 VCC

VIL ≤ 0.3 VCC

Finally, the reference voltages for the timing measurements need specifying. L et us call them V RH and

VRL, here, but note that, because these are not physical parameters of the hardware, they ar e not gener-

ally given explicit nam es in the data sheet. However, they do appear in the “AC Measurement Conditions”

table, and in the accompanying “AC Testing Input Output Waveforms” diagram. Generally, they set at

VIH(min) and VIL(max), respectively. That is, the measurement equipment is set to recognize the logic

thresholds at the same voltages as are rec ognized by the input buffers of the chip.

VRH = 0.7 VCC

VRL = 0.3 VCC

Symbol Alt. Parameter

tAVAV tRC Read Cycle Time

tAVQV tACC Address Valid to Output Valid

tELQX tLZ Chip Enable Low to Output Transition

tELQV tCE Chip Enable Low to Output Valid

tGLQX tOLZ Output Enable Low to Output Transition

tGLQV tOE Output Enable Low to Output Valid

tEHQZ Chip Enable High to Output Hi-Z

tGHQZ tDF Output Enable High to Output Hi-Z

tAXQX tOH Address Transition to Output Transition

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Notice, though , that thi s is by de finition, and is not itself a measu re d param ete r (he nce the “e qual” sign,

rather than the “less than or equals” or “greater than or equals” sign for the boun ded value.

Although, in theory, no timings depend on the rise and fall times of signals, some products may have char-

acteristics which vary with the slew rate of the input. For an ST EPROM device, the data sheet might state

“Input rise and fall times are 20 ns (max)”.

As a further point of definition, the data s heets might state t hat “a si gnal is de fined as Hi-Z (high im ped-

ance) when it is not driving or being driven”.

TIMING DIAGRAMS

The JEDEC convention leads to clearer, les s ambiguous timing specifications. Also, it allows a substant ial

simplification to be made to timing di agrams, and hence to an increas e in the ir clarity. Since the voltage

reference levels (VRH and VRL) are spec ified explicitly in t he data sheet, as described in the section above,

these levels do not need to be spelled out precisely each time on the timing diagram. Ins tead, it is sufficient

to depict, di agrammatically, the timing events starting and ending at the m idpoints of logic transit ions, and

to let the name of the parameter indicate which of the referenc e levels are involved.

For example, the data sheet might specify the meas urem ent condi tions, with V CC=5 V, as follows:

– Input Voltage levels are VOL=1 V and VOH=4 V

– Input and Output timing reference levels are 1.5 V an d 3.5 V

– Output Hi-Z is the point where the signal is no longer driving

The parameters in the timing diagram (Figure 3) would then be interpreted as follows:

–t

AVAV is measured f rom the point where all address line s are either above 3. 5 V or below 1.5 V, to the

point of similar conditions at the end of the cycle.

–t

ELQV is m easured f rom E being below 1. 5 V, to the point when all data lines are either above 3. 5 V or

below 1.5 V.

–t

EHQZ is measu red from E being abov e 3. 5 V, to th e point when the d ata outputs are no longe r d riving

the signal lines.

Note that, in Figu re 3, t he t ELQV t im ing, for ex am pl e, is shown diagram ma tically not from a “low” poin t on

the E falling edge, but from t he cent er , and is shown not to a “high/low” point on the Data Output but again

to the center.

Figure 3. Timing Diagram (an Examp le)

AI00709

tEHQZ

DATA OUT

A0-A14

DQ0-DQ7

tAVAV

tELQV

VALID

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AN397 - APPLICATION NOTE

If you have any questions or suggestions concerning the matters raised in this document, please send

them to the following electronic mail address:

ask.memory@st.com

(for general enquiries)

Please remember to include your name, compa ny , location, telephone num ber and fax number.

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