MAX 7000A Programmable Logic Device Family Features... High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array Matrix (MAX) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (TAG) interface with advanced pin-locking capability Prelit inary Built-in boundary-scan test (BST) circuitry compliant with infarmation TREE Std. 1149.1-1990 @ Enhanced ISP features Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices) Pull-up resistor on I/O pins during in-system programming @ Pin-compatible with the popular 5.0-V MAX 70008 devices High-density PLDs ranging from 600 to 10,000 usable gates 4.5-ns pin-to-pin logic delays with counter frequencies of up to 192.3 MHz 2 For information on in-system programmable 5.0-V MAX 7000 or 2.5-V = ae MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Advance Information Brief in this data book. Table 1. MAX 7000A Device Features Feature EPM7032AE EPM7064AE EPM7128AE EPM7256AE EPM7512AE EPNI7128A4 EPM7256A Usable gates 600 1,250 2,500 5,000 10,000 Macrocells 32 64 128 256 512 Lagic array blacks 2 4 8 16 32 Maximum user VO 36 68 100 164 212 pins tpp (ns) 4.5 4.5 5.0 6.0 7.5 tgy (ns) 3.0 3.0 3.2 3.7 49 tesu (ns) 2.5 2.5 2.5 25 3.0 teo1 (ns) 2.8 2.8 3.0 3.3 45 font (MHz) 192.3 192.3 181.8 156.3 119.0 Altera Corporation 595 A-DS-M7000.A-02MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information ...and More Features 596 fee ee a: MultiVolt 1/0 interface enabling device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TOFP), plastic quad flat pack (POFP), ball-grid array (BGA), space- saving FineLine BGA, and plastic J-lead chip carrier (PLCC) packages Supports hot-socketing in MAX 7000AE devices Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance Peripheral component interconnect (PCI) compatible Bus friendly architecture including programmable slew-rate control Open-drain output option Programmable macrocell registers with individual clear, preset, clock, and clock enable centrels Programmable power-up states for macrocell registers in MAX 700OAE devices Programmable power-saving mode for 50% or greater power reduction in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell Programmable security bit for protection of proprietary designs 6 to 10 pin- or logic-driven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from 1/O pin to macrocell registers Programmable output slew-rate control Programmable ground pins Software design support and automatic place-and-route provided by Alteras MAX+PLUS I development system for Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations, and the Quartus development system for Windows-based PCs and Sun SPARCstation and HP 9000 Series 700 workstations Additional design entry and simulation support provided by EDIF 200 and 3 0 O netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with Alteras Master Programming Unit (MPU), BitBlaster serial download cable, and ByteBlasterMV parallel port download cable, as well as programming hardware from third-party manufacturers and any Jam File (jam), Jam Byte-Code File (.jbc), or Serial Vector Format File- (svf) capable in-circuit tester Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet G ene ral MAX 7O00A (including MAX 7000AE) devices are high-density, high- 45 performance devices based on Alteras second-generation MAX D escri pti on architecture. Fabricated with advanced CMOS technology, the EEPROM- based MAX 7O00A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 192.3 MHz. MAX 7000A devices in the -5, -6, -7, and -10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2,2. See Table 2. Table 2. MAX 7000A Speed Grades _Notes (1), (2) Device Speed Grade -4 5 -6 7 EPM7032AE EPM7064AE EPM7128A we / EPM7128AE EPM7256A 7 EPM7256AE EPM7512AE a8, SIRIATS J AOATAYR Notes: (1) Contact Altera Applications for up-to-date information on available device speed grades. (2) Timing parameters for these speed grades are preliminary. Altera Corporation 597MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information The MAX 7000A architecture supports 100% TTL emulation and high- density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH, and pLsI devices. MAX 7O00A devices are available in a wide range of packages, including PLCC, BGA, FineLine BGA, PQFP, and TQFP packages. See Table 3. Table 3. MAX 7080A Maximum User 1/0 Pins Notes (1), (2) Device 44-Pin | 44-Pin | 84-Pin | 100-Pin | 100-Pin | 144-Pin | 208-Pin | 256-Pin | 256-Pin PLCC | TOFP | PLCC | TOFP |FineLine} TOFP | POFP BGA |FineLine BGA BGA EPM7032AE | 36 36 EPM7064AE | 36 36 68 68 68 (3) EPM7128A 68 84 84 100 100 EPM7128AE 68 84 84 100 100 EPM7256A 84 120 164 164 EPM7256AE 84 84 120 164 164 EPM7512AE 120 176 212 212 Notes: (1) Contact Altera tor up-to-date information on available device package options. (2) When the IEEE Std. 1149.1 (TAG) interface is used for in-system programming or boundary-scan testing, four 1/O pins become JTAG pins. (3) All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See SameFrame Pin-Outs on page 608 for more details. 598 MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7O00A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. MAX 7O00A devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high- speed parallel expander product terms to provide up to 32 product terms per macrocell. Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet oo Be Functional Description Altera Corporation MAX 7000A devices provide programmable speed /power optimization. Speed-critical portions of a design can run at high speed/ full power, while the remaining portions run at reduced speed /low power. This speed/ power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000A devices can be set for 2.5 V or 3.3 V and all input pins are 2.5-V,3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used in mixed-voltage systems. MAX 7000A devices are supported by the Quartus and MAX+PLUS I] development systems, which are integrated packages that offer schematic, textincluding VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The Quartus and MAX+PLUS II software provides EDIF 20 0and3 00, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry- standard PC- and UNIX-worksiation-based EDA tools. The MAX+PLUS I software runs on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/ 6000 workstations. The Quartus software runs on Windows-based PCs, as well as Sun SPARCstation and HP 9000 Series 700 workstations. For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System Data Sheet. The MAX 7000A architecture includes the following elements: Logic array blocks (LABs) Macrocells Expander product terms (shareable and parallel) Programmable interconnect array I/O control blocks HERR R B The MAX 7000A architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 7000A devices. 599MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Figure 1. MAX 7000A Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE 4 INPUT/GCLRn 6 or 10 Output Enables (7? Bor 10 Enables (1) : vo |sto16 FIEY Macrocells Macrocells . 3101610 8 | Control 1to16 17to 32 # 3101610 Block * . WO 3to16 PE: Macrocells : Macrocells lo . 3101610 : Control 33 to 48 49 t0 G4 Control] # 310 1610 Block Block Note: (1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables. EPM7512AE devices have 10 output enables. Logic Array Blocks The MAX 7000A device architecture is based on the linking of high-performance LABs. LABs consist of 16-macrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, 1/O pins, and macrocells. Each LAB is fed by the following signals: % 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions Direct input paths from 1/0 pins to the registers that are used for fast setup times 600 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Macrocells The MAX 7000A macrocell can be individually configured for either sequential or combinatorial logic operation. The macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. Figure 2 shows the MAX 7000A macrocell. Figure 2. MAX 7008A Macrecell Global Global LAB Local Array Clear Clocks From Parallel Logic 24 VO pin Expance s Fastinput Programmable {from ather Select Aegister macrocells) Register nm Bypass {oH a I } To VO I y i Control TH . oo Block Cth Product- : clot > . Term Naole EN {oH Select Select ai) CLAN Matrix ) WoC eee Clear Select yn 4 <q T ee T: Shared Logic To PIA Expanders 36 Signals 16 Expander from PIA Product Terms Altera Corporation Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocells register preset, clock, and clock enable control functions. Two kinds of expander product terms (expanders) are available to supplement macrocell logic resources: @ Shareable expanders, which are inverted product terms that are fed back into the logic array # Parallel expanders, which are product terms borrowed from adjacent macrocells 601MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information The MAX+PLUS H development system automatically optimizes product-term allocation according to the logic requirements of the design. For registered functions, each macrocell flipflop can be individually programmed to implement D, T, |K, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the MAX+PLUS II software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: Global clock signal. This mode achieves the fastest clock-to-output performance. Global clock signal enabled by an active-high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. Array clock implemented with a preduct term. In this mede, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX 7000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear from the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register ina MAX 7000AE device may be set to either a high or low state. This power-up state is specified at design entry. All MAX 7000A 1/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be clocked to an input D flipflop with an extremely fast (as low as 2.5 ns) input setup time. 602 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Altera Corporation Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, more complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources. However, the MAX 7000A architecture also offers both shareable and parallel expander product terms (expanders) that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (fspxp) is incurred when shareable expanders are used. Figure 3 shows how shareable expanders can feed multiple macrocells. Figure 3. MAX 7000A Shareable Expanders Shareable expanders can be shared by any or all macrocelts in an LAP. Macrocell Product-Term Logic Produci-Term Sefect Matrix iMacrocefl Product-Term Logic eee eee 36 Signals 16 Shared from PIA Expanders 603MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information 604 Parallel Expanders Parallel expanders are unused product terms that can be allocated toa neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with 5 product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. The MAX+PLUS I Compiler can allocate up to 3 sets of up to 5 parallel expanders automatically to the macrocells that require additional product terms. Each set of 5 parallel expanders incurs a small, incremental timing delay (tpxp). For example, if a macrocell requires 14 product terms, the Compiler uses the 5 dedicated product terms within the macrocell and allocates 2 sets of parallel expanders; the first set includes 5 product terms and the second set includes 4 product terms, increasing the total delay by 2x tpexp. Two groups of 8 macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form 2 chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower-numbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrecell can only borrow them. Figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell. Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Figure 4. MAX 7000A Parallel Expanders Unused product terms in a macrocell can be allocated fo a neighboring macrocell. From Previous Macrocell Macrocell Product- Term Logic Preset Macrocell Product- Term Logic To Next Macrocell 36 Signals 16 Shared from PIA = Expanders Programmable Interconnect Array Logic is routed between LABs on the PIA. This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 7000A dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure 5 shows how the PIA signals are routed into the LAB, An EEPROM cell controls one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB. Altera Corporation 605MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information 606 Figure 5. MAX 7080A PIA Routing To LAB PIA Signals While the routing delays of channel-based routing schemes in masked or field-programmable gate arrays (FPGAs) are cumulative, variable, and path-dependent, the MAX 7000A PIA has a predictable delay. The PIA makes a design's timing performance easy to predict. 1/0 Control Blocks The I/O control block allows each 1/0 pin to be individually configured for input, output, or bidirectional operation. All1/O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or Ver. Figure 6 shows the I/O control block for MAX 7000A devices. The 1/ control block has 6 or 10 global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins, ora subset of the I/O macrocells. Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Figure 6. 1/0 Control Block of MAX 7000A Devices PIA Note: oToTT] 6 or 10 Global Output Enable Signals (1) _ OE Select Multiplexer voc To Other I/O Pins From LI I @ GND Macrocell Fast Input to Macrocell ~@ Open-Drain Output Slew-Rate Control Register To PIA ~& (1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enable signals. EPM7512AE devices have 10 output enable signals. Altera Corporation When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the 1/O pin can be used as a dedicated input. When the tri-state buffer control is connected to Voc, the output is enabled. The MAX 7000A architecture provides dual 1/O feedback, in which macrocell and pin feedbacks are independent. When an 1/O pin is configured as an input, the associated macrocell can be used for buried logic. 607MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information SameFrame Pin-Quts 608 MAX 7000A devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA packages such that the lower-ball- count packages form a subset of the higher-ball-count packages. SameFrame pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. A given printed circuit board (PCB) layout can support multiple device density / package combinations. For example, a single board layout can support a range of devices from an EPM7128A device in a 256-pin FineLine BGA package to an EPM7512AE device in a 256-pin FineLine BGA package. The Quartus and MAX+PLUS II software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The Quartus and MAX+PLUS II software generates pin-outs describing how to lay out a board to take advantage of this migration (see Figure 7). Figure 7. SameFrame Pin-Out Example Printed Circuit Board Designed for 256-PinFineLine BGA Package Po} ED aaa) FineLine i etal BGA 8 BGA 100-Pin FineLine BGA Package 256-Pin FineLine BGA Package (Reduced I/O Count or (Increased I/O Count or Logic Requirements) Logic Requirements) Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet In-System Programma- bility (ISP) 585 ae Altera Corporation MAX 7000A devices can be programmed in-system via an industry- standard 4-pin IEEE Std. 1149.1-1990 (TAG) interface. ISP offers quick, efficient iterations during design development and debugging cycles. The MAX 7000A architecture internally generates the high programming voltages required to program EEPROM cells, allowing in-system programming with only a single 3.3-V power supply. During in-system programming, the I/O pins are tri-stated and weakly pulled-up to eliminate board conflicts. The pull-up value is nominally 50 kQ. MAX 7OQ00AE devices have an enhanced ISP algorithm for faster programming. These devices also offer an ISP_Done bit that provides safe operation when in-system programming is interrupted. This ISP_Done bit, which is the last bit programmed, prevents all 1/O pins from driving until the bit is programmed. This feature is available in EPM7032AE, EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices only. ISP simplifies the manufacturing flow by allowing devices to be mounted ona printed circuit board (PCB) with standard pick-and-place equipment before they are programmed. MAX 7000A devices can be programmed by downloading the information via in-circuit testers, embedded processors, the Altera BitBlaster serial download cable, and the ByteBlasterMV parallel port download cable. Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling. MAX 7000A devices can be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers cannot support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm contain an F suffix in the ordering code and are marked with an F on the bottom right-hand corner of the device. The Jam programming and test language can be used to program MAX 7000A devices with in-circuit testers, PCs, or embedded processors. For more information on using the Jam language, see Application Note 88 (Using the jam Language for ISP & ICR via an Embedded Processor). 609MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Programming with External Hardware IEEE Std. 1149.1 (JTAG) MAX 7000A devices can be programmed on Windows-based PCs with an Altera Logic Programmer card, the MPU, and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardtvare Data Sheet. The MAX+PLUS II software can use text- or waveform-format test vectors created with the MAX+PLUS II Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation. Data I/O, BP Microsystems, and other programming hardware manufacturers provide programming support for Altera devices. For more information, see Programming Hardware Manufacturers. MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std. 1149.1-1990. Table 4 describes the JTAG instructions supported by MAX 7000A devices. The pin-out tables starting on page 632 of this data Bo un da ry-Sca n sheet show the location of the JTAG control pins for each device. If the Support JTAG interface is not required, the JTAG pins are available as user 1/O pins. Table 4. MAX 7000A JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD | Allows a snapshot of signals at the device pins ta be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASS Places the 1-bit bypass register between the TDI and TDoO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. IDCODE Selects the IDCODE register and places it between the TDI and TDo pins, allowing the IDCODE to be serially shifted out of TDo. USERCOCDE Selects the 32-bit USERCODE register and places tt between the TDI and TL pins, allowing the USERCODE value to be shifted out of Tbo. USERCODE instructions are available for MAX 7OOOAE devices only. UESCODE These instructions select the user electronic signature (UESCODE) and allow the UESCODE to be shifted out of Too. UESCODE instructions are available for EPM7128A and EPM7256A devices only. ISP Instructions These instructions are used when programming MAX 7000A devices via the JTAG ports with the BitBlaster, ByteBlaster, or ByteBlasterMV download cable, or using a Jam File (.jam), Jam Byte-Code File (.jbe), or Serial Vector Format File (.svf} via an embedded processor or test equipment. 610 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet a a, 8 ee Altera Corporation The instruction register length of MAX 7000A devices is 10 bits. The UES register length in MAX 7O00A devices is 16 bits. The MAX 7O00AE USERCODE register length is 32 bits. Tables 5 and 6 show the boundary- scan register length and device IDCODE information for MAX 7000A devices. Table 5. MAX 7808A Poundary-Scan Register Length Device Poundary-Scan Register Length EPM7032AE 96 EPM7064AE 192 EPM7128A 288 EPM7128AE 288 EPM7256A 480 EPM7256AE 480 EPM7512AE 624 Table 6. 32-Bit MAX 700A Device IDEODE Note (1) Device iDCODE (32 bits) Version | Part Number (16 Bits) | Manufacturer's | 1 (1 Bit) (4 Bits) identity (11 Bits}| (2) EPM7032AE O001 0111 0000 0011 0010] 00001101110 1 EPM7064AE }| 0001 |0111 0000 0110 0100} 00001101110 1 EPM7128A o000 0111 0001 0010 1000] 00001101110 1 EPM7128AE QO001 0111 0001 0010 1000] 00001101110 1 EPM7256A o0000 0111 0010 0101 01170] 00001101110 1 EPM7256AE ] 0001 |0111 0010 0101 0110} 00001101110 1 EPM7512AE o001 0111 0101 0001 0010] 00001101110 1 Notes to tables: ) (2) The most significant bit (MSB) is on the left. The least significant bit (LSB) for all JTAG IDCODEs is 1. See Application Note 39 (IEEE 1149.1 (TAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST. 611MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Figure 8 shows the timing information for the JTAG signals. Figure 8. TMS TDI TCK TDO Signal to Be Captured Signal to Be Driven xX X_ MAX 7000A JTAG Waveforms X x X K Table 7 shows the JTAG timing parameters and values for MAX 7000A devices. Table 7. JTAG Timing Parameters & Values for MAX 7000A Devices Symbol Parameter Min | Max | Unit tycp | TCK clock period 100 ns tycH = | TCK clock high time 50 ns tic. TCK clock low time 50 ns tupsu | JTAG port setup time 20 ns typy = | JTAG port hald time 45 ns typco | JTAG port clock to output 25 ns typzx |JTAG port high impedance to valid output 25 ns typxz |JTAG port valid output to high impedance 25 ns tussy | Capture register setup time 20 ns tsH Capture register hold time 45 ns tysco | Update register clock to output 25 ns tyszx | Update register high impedance to valid output 25 ns tysxz | Update register valid output to high impedance 25 ns 612 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Programmable Speed/Power Control Output Configuration Altera Corporation MAX 7000A devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more, because most logic applications require only asmall fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX 7000A device for either high-speed or low-power operation. As a result, speed- critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (t; pq) for the any trac tic tac teny and tspxp parameters. MAX 7000A device outputs can be programmed to meet a variety of system-level requirements. MultiVolt 1/0 Interface The MAX 7000A device architecture supports the MultiVolt1/O interface feature, which allows MAX 7000A devices to connect to systems with differing supply voltages. MAX 7000A devices in all packages can be set for 2.5-V, 3.3-V, or 5.0-V 1/O pin operation. These devices have one set of Vcc pins for internal operation and input buffers (VCCINT), and another set for 1/O output drivers (VCCIC). The VCCIO pins can be connected to either a 3.3-V or 2.5-V power supply, depending on the output requirements. When the VCCI pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with Vccjo levels lower than 3.0 V incur anominally greater timing delay of top> instead of top;. Inputs can always be driven by 2.5-V, 3.3-V, or 5.0-V signals. Table 8 describes the MAX 7O00A MultiVolt I/O support. Table &. MAX 7000A MultiVait /O Support Vecio Voltage Input Signal () Output Signal () 2.5 3.3 5.0 2.5 3.3 5.0 2.5 we ae a 3.3 ef va vw A 613MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Open-Drain Output Option MAX 7000A devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane. Open-drain output pins on MAX 7000A devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a Vyy of 3.5 V. When the open-drain pin is active, it will drive low. When the pin is inactive, the trace will be pulled up to 5.0 V by the resistor. The open- drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The Ip, current specification should be considered when selecting a pull-up resistor. Programmable Ground Pins Each unused 1/0 pin on MAX 7O00A devices may be used as an additional ground pin. In EPM7128A and EPM7256A devices, utilizing unused 1/O pins as additional ground pins requires using the associated macrocell. In MAX 7Q00AE devices, this programmable ground feature does not require the use of the associated macrocell; therefore, the buried macrocell is still available for user logic. Slew-Rate Control The output buffer for each MAX 7000A 1/0 pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for low-noise performance. Each 1/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the output signal. 614 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Power Sequencing & Hot-Socketing Design Security Generic Testing Altera Corporation Because MAX 7000A family devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. The Vccjg and Veer power planes can be powered in any order. Signals can be driven into MAX 7000A devices before and during power up without damaging the device. Additionally, MAX 7000A devices do not drive out during power up. Once operating conditions are reached, MAX 7000A devices operate as specified by the user. All MAX 7000A devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security, because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. MAX 7000A devices are fully functionally tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 9. Test patterns can be used and then erased during early stages of the production flow. Figure . MAX 700A AC Test Canditions Power supply transients can affect AC measurements. Simulfaneous transitions of multiple outputs should be avoided for accurafe measurement. Threshold fests must not be performed under AC conditions. Large-amplitude, fast-ground- current transients normally oceur as fhe device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the fest system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.6-V outputs. Numbers without brackets are for 3.3-V devices or outputs. voc 703 3 [521 Q] Device Cutput 8,060 0 [481 Q] Ci (includes JIG capacitance) Device input rise and fall times < 2 ns 615MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information 0 p erati ng Tables 9 through 12 provide information on absolute maximum ratings, ays recommended operating conditions, operating conditions, and Con d itions capacitance for MAX 7000A devices. Table 9. MAX 7000A Device Absolute Maximum Ratings Note (1) Symbol Parameter Conditions Min Max Unit Voc Supply voltage With respect to ground (2) -0.5 46 Vv Vi DC input voltage -2.0 5.75 Vv lout DC output current, per pin -25 25 mA Tste Storage temperature No bias -65 150 C Ta Ambient temperature Under bias -65 135 C Ty Junction temperature FineLine BGA, PQFP, and TQFP 135 ec packages, under bias Table 18. MAX 7000A Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit Vecnt | Supply voltage for internal logic and | 3) 3.0 3.6 Vv input buffers Vecio Supply voltage for outputdrivers, | (3) 3.0 3.6 Vv 3.3-V operation Supply voltage for output drivers, | 3) 2.3 27 Vv 2.5-V operation Vecisp | Supply voltage during in-system 3.0 3.6 Vv programming Vv Input voltage (2), (4) 0.5 5.75 Vv Vo Output voltage 0 Vocio Vv Ta Ambient temperature Fer commercial use 0 70 2c For industrial use 40 85 2 Ty Junction temperature For commercial use 0 90 2c For industrial use 40 105 ec tr Input rise time 40 ns tr Input fall time 40 ns 616 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 11. MAX 700A Device DE Operating Conditions _ Note (4) Symbol Parameter Conditions Min Max Unit Vin High-level input voltage 17 5.75 Vv Vit Low-level input valtage (2) -0.5 0.8 Vv Vou 3.3-V high-level TTL output voltage | loy =-8 MA DC, Vecig = 3.00 V (6) 2.4 Vv 3.3-V high-level CMOS output lon = 0.1 MA BC, Vecio = 3.00 V (6) Vecio 0.2 Vv voltage 2.5-V high-level output voltage loq = 100 HA DC, Vecio = 2.30 V (6) 2.1 Vv lon =1 MA DC, Vooig = 2.30 V (6) 2.0 Vv loy =-2 MA DC, Vecig = 2.30 V (6) 1.7 Vv Vor 3.3-V low-level TTL output voltage | lo, = 8 MA DC, Veciq = 3.00 V (7) 0.45 Vv 3.3-V low-level CMOS output lo, = 0.1 MA DC, Vecig = 3.00 V (7) 0.2 Vv voltage 2.5-V low-level output voltage lo, = 100 HA DS, Veco = 2.30 V (7) 0.2 Vv lo, =1 mA DC, Vocig = 2.30 V (7) 0.4 Vv lo, = 2 mA DC, Vocig = 2.30 V (7) 0.7 Vv I Input leakage current Vi = Voecint or ground -10 10 HA loz Tri-state output off-state current Vo = Vecint or ground -10 10 pA Risp Value of I/O pin pull-up resistor Vecio = 3.0 to 3.6 V (8) 20 50 kQ during programming in-system or Vocio = 2.310 2.7 V (8) 30 80 koQ during power-up Vocio =2.3103.6V (9) 20 74 ko Table 12. MAX 700A Device Capacitance sNote (10) Symbol Parameter Conditions Min Max Unit Cin Input pin capacitance Vin =OV.f=1.0 MHz 8 pF Cho lO pin capacitance Vout = 0 V. f= 1.0 MHz 8 pF Nates fo tables: (1) See the Operating Requirements for Altera Devices Data Sheet in this data book. (2) Minimum DC input voltage is -0.5 V. During transitions, the inputs may undershoot to 2.0 V or overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Vec must rise monotonically. (4) In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven betore Veent and Verjo are powered. (5) These values are specified in Table 10 on page 616. (6) The parameter is measured with 50% of the outputs each sourcing the specified current. The Iz; parameter refers to high-level TTL or CMOS output current. (7) The parameter is measured with 50% of the outputs each sinking the specified current. The Ij; parameter refers to low-level TTL or CMOS output current. (8) For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system. (9) For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed devices during power-up. (10) Capacitance is measured at 25 C and is sample-tested only. The o 1 pin (high-voltage pin during programming) has a maximum capacitance of 20 pF. Altera Corporation 617MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Figure 10 shows the typical output drive characteristics of MAX 7000A devices. Figure 10. Output Drive Characteristics of MAX 7000A Devices 3.3 6O- 40 Typical |, Output 4 Current (mA) 20 lot Veoint = 3.3 Room Temperature 1 1 1 1 2 3 Va Output Voltage (V) 25 Typical |, Output Current (mA) 60 40 20 Vecnt = 3.3 Vecio= 2.5V Room Temperature 1 1 1 1 1 2 3 4 Vo Output Voltage (V} Timing Model 618 MAX 7000A device timing can be analyzed with the Quartus and MAX+PLUS I software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 11. MAX 7OQOA devices have predictable internal delays that enable the designer to determine the worst-case timing of any design. The MAX+PLUS II software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation. Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Figure 17. MAX 7000A Timing Modal Internal Output pe| Enable Delay foe Input > Global Control! C>j Delay Delay v tin tetoa Register Output Parallel Delay Delay L.. Logic Array , Expander Delay t t I Dele a Delay {pExe th toce tone Aa al (PRE fons : CLR bez > Register ten tows Control Delay ~}_-__________j|_; t P thac (Come 2 tic FSU ZX fren fen ie) Shared Delay Fast oP) Expander Delay tio Pe isexp y > poy The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 12 shows the timing relationship between internal and external delay parameters. * ee ae See Application Note 94 (Understanding MAX 7000 Timing) in this data book for more information. Altera Corporation 619MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Figure 12. MAX 7000A Switching Waveforms fp & fp <2 ns. inputs are driven at 3 V for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. VO Pin Input Pin PIA Delay Shared Expander Delay Logic Array Input Parallel Expancer Delay Logic Array Output Output Pin Global Clock Pin Global Clock at Register Data or Enable Logie Array Output} Input or YO Pin Clock into PIA Clock into Logic Array Clock at Register Data from Logic Array Register to PIA to Logic Array Register Output to Pin 620 Combinatorial Mode x i feo +i X Global Clock Mode ig i t= fon fou et les op fsu it fy Array Clock Made in i- tac *E ls face 44 fiw to i. feu fy X x ; \ ipo +i ia toy, foun. fppeet belo y . ie ton it lop Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Tables 13 through 20 show EPM7128A, EPM7256A, and MAX 7O00AE AC operating conditions. Table 13. EPM7128A External Timing Parameters _Note (1) Symbol Parameter Conditions Speed Grade Unit 6 7 -10 12 Min | Max | Min | Max | Min | Max | Min | Max tep1 Input to non- C1 =35 pF 6.0 7.5 10.0 12.0 ns registered output (2) tops \/O input te non- C1 =35 pF 6.0 7.5 10.0 12.0 ns registered output (2) tsu Global clock setup | (2) 4.2 5.3 7.0 8.5 ns time ty Global clock hold (2) 0.0 0.0 0.0 0.0 ns time tesu Global clock setup 2.5 3.0 3.0 3.0 ns time of fast input tey Glebal clock hold 0.0 0.0 0.0 0.0 ns time of fast input teo1 Global clock to C1 =35 pF 1.0 3.7 1.0 46 1.0 6.1 1.0 7.3 ns output delay ten Global clock high 3.0 3.0 40 5.0 ns time te. Global clock low time 3.0 3.0 40 5.0 ns tasu Array clock setup (2) 1.9 24 3.1 3.8 ns time tan Array clock hold time | (2) 1.5 2.2 33 43 ns tacoi Array clock to output | C1 = 35 pF 1.0 6.0 1.0 75 19 10.0 1.0 12.0 ns delay (2) tacu Array clock high time 3.0 3.0 40 5.0 ns tac. Array clock low time 3.0 3.0 40 5.0 ns tent Minimum global (2) 6.9 8.6 11.5 13.8 ns clock period fent Maximum internal (2), (3) 144.9 116.3 87.0 725 MHz global clack frequency tacnt Minimum array clock | (2) 6.9 8.6 11.5 13.8 ns pericd facnt Maximum internal (2), (3) 144.9 116.3 87 72.5 MHz array clock frequency TMax Maximum clock (4) 166.7 166.7 125.0 100.0 MHz frequency Altera Corporation 621MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 74. EPM7128A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions Speed Grade Unit -6 7 10 -12 Min | Max | Min | Max | Min | Max | Min | Max tiny Input pad and buffer delay 0.6 0.7 09 11 ns tio lO input pad and butter 0.6 OF 0.9 11 ns delay tein Fast input delay 27 3.1 3.6 3.9 ns tsexp Shared expander delay 2.5 3.2 43 5.1 ns tpexp Parallel expander delay 0.7 0.8 11 1.3 ns trap Logic array delay 24 3.0 41 49 ns tac Logic control array delay 24 3.0 41 49 ns tor Internal output enable delay 0.0 0.0 0.0 0.0 ns tony Qutput butfer and pad delay | C1 = 35 pF 0.4 0.6 07 0.9 ns slow slew rate = off tone OCutput buffer and pad delay | C1 = 35 pF 0.8 14 1.2 1.4 ns slow slow rate = off (5) tons Output buffer and pad delay | C1 = 35 pF 5.4 5.6 5.7 5.9 ns slow slew rate = on Vecio =25Vor3.3V ta Qutput butfer enable delay | C1 = 35 pF 40 40 5.0 5.0 ns slow slew rate = off tyne Cutput buffer enable delay | C1 = 35 pF 45 45 5.5 5.5 ns slow slew rate = off (5) tong Cutput buffer enable delay | C1 = 35 pF 9.0 9.0 10.0 10.0 | ns slow slew rate = on yz Qutput butfer disable delay |C1 = 5 pF 40 40 5.0 5.0 ns tou Register setup time 1.9 24 3.1 3.8 ns ty Register hold time 1.5 2.2 3.3 43 ns tesu Register setup time of fast 0.8 11 14 14 ns input try Register hold time of fast 17 1.9 1.9 19 ns input tap Register delay 1.7 2.1 28 3.3 ns tcome Combinatorial delay 1.7 2.1 28 3.3 ns tic Array clock delay 24 3.0 41 4.9 ns ten Register enable time 2.4 3.0 41 49 ns teroB Global control delay 1.0 1.2 1.7 2.0 ns tpar Register praset time 3.4 3.9 5.2 6.2 ns 622 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 14. EPM7728A Internal Timing Parameters (Part 2 of 2) Symbal Parameter Conditions Speed Grade Unit 6 7 10 12 Min | Max} Min | Max | Min | Max | Min | Max ferp Register clear time 3.1 3.9 5.2 6.2 ns Epi, PIA delay (2) 0.9 11 15 1.8 ns th pa Low-power adder (6) 11.0 10.0 10.0 10.0 | ns Table 15. EPM7256A External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit 6 7 -10 12 Min | Max | Min | Max | Min | Max | Min | Max tep1 Input to non-registered C1 =35 pF 6.0 7.5 10.0 12.0 ] ns output (2) tep2 lO inputte non-registered |O1 =35 pF 6.0 7.5 10.0 12.0 ] ns output (2) tsu Global clock setup time (2) 3.7 46 6.2 7.4 ns ty Global clock hold time (2) 0.0 0.0 0.0 0.0 ns tesu Global clock setup time of 2.5 3.0 3.0 3.0 ns fast input tey Global clock hold time of 0.0 0.0 0.0 0.0 ns fast input teo1 Global clock to output delay | C1 = 35 pF 1.0 3.3 1.0 42 1.0 5.5 1.0 6.6 ns ten Global clock high time 3.0 3.0 4.0 40 ns te. Global clock low time 3.0 3.0 4.0 40 ns tasu Array clock setup time (2) 0.8 1.0 1.4 1.6 ns tay Array clock hold time (2) 1.9 2.7 4.0 5.1 ns taco1 Array clock to output delay | C1 =35 pF 1.0 6.2 1.0 7.8 1.0 | 103) 10 | 124] ns (2) tacu Array clock high time 3.0 3.0 4.0 40 ns tac. Array clock low time 3.0 3.0 4.0 40 ns tent Minimum global clock (2) 6.4 8.0 10.7 128 ] ns period fent Maximum internal global (2), (3) 156.3 125.0 93.5 78.4 MHz clock frequency tacnt Minimum array clock period | (2) 6.4 8.0 10.7 12.8 ] ns facnt Maximum internal array (2), (3) 156.3 125.0 93.5 78.4 MHz clock frequency tax Maximum clock frequency | (2), (4) 166.7 166.7 125.0 125.0 MHz Altera Corporation 623MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 16 EPM7256A Internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit 6 7 10 12 Min | Max} Min | Max} Min | Max} Min | Max tiny Input pad and butfer delay 0.3 0.4 05 06] ns tio VO input pad and buffer delay 0.3 0.4 0.5 0.6] ns tein Fast input delay 24 3.0 3.4 3.8] ns tsexp Shared expander delay 2.8 3.5 47 5.6] ns tpexp Parallel expander delay 0.5 0.6 0.8 1.0] ns trap Logic array delay 2.5 3.1 42 5.0] ns trac Logic control array delay 2.5 3.1 4.2 5.0] ns toe Internal output enable delay 0.2 0.3 04 0.5] ns topr Output buffer and pad delay C1 =35 pF 0.3 0.4 05 0.6] ns slow slaw rate = off Vecio = 3.3 tone Output butter and pad delay C1 =35 pF (5) 0.8 0.9 1.0 1.147 ns slow slew rate = off Vecio = 2.5 tons Output butter and pad delay C1 =35 pF 5.3 5.4 5.5 5.6] ns slow slew rate = on Vecio =25Vor3.3V tox Output butter enable delay C1 =35 pF 4.0 4.0 5.0 5.0] ns slow slaw rate = off tyxe Output butter enable delay C1 =35 pF (5) 45 4.5 5.5 5.5] ns slow slew rate = off tog Output butter enable delay C1 =35 pF 9.0 9.0 10.0 10.0] ns slow slaw rate = on Vecio =25Vor33V iy Output butter disable delay C1=5pF 4.0 4.0 5.0 5.0] ns tou Register setup time 1.0 1.3 1.7 2.0 ns ty Register hold time 17 24 3.7 47 ns tesu Register setup time of fast input 1.2 14 1.4 1.4 ns toy Register hold time of fast input 1.3 1.6 1.6 1.6 ns tap Register delay 1.6 2.0 2.7 3.2 | ns tcome Combinatorial delay 1.6 2.0 27 3.2] ns tic Array clock delay 27 3.4 45 5.4] ns ten Register enable time 2.5 3.1 4.2 5.0] ns teros Global control delay 11 14 1.8 2.2] ns toar Register preset time 2.3 2.9 3.8 46] ns torr Register clear time 2.3 2.9 3.8 46] ns tpia PIA delay (2) 1.3 1.6 2.1 2.6] ns tipa Low-power adder (6) 11.0 10.0 10.0 10.0] ns 624 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 17. MAX 7000AE External Timing Parameters Notes (1), (7) Symbol Parameter Conditions Speed Grade Unit 5 6 Min | Max | Min | Max | Min | Max tepi Input to non- C1 = 35pF (2) 45 5.0 6.0 ns registered output tppe lO input to nen- C1 = 35 pF (2) 4.5 5.0 6.0 ns registered output tsu Global clock setup (2) 3.0 3.2 3.7 ns time ty Global clock hold time | (2) 0.0 0.0 0.0 ns tesu Global clock setup 2.5 2.5 25 ns time of fast input tey Global clock hold time 0.0 0.0 0.0 ns of fast input teo1 Global clock to output | C1 = 35 pF 1.0 2.8 1.0 3.0 1.0 3.3 ns delay tou Global clock high time 2.0 2.0 3.0 ns tet Global clock low time 2.0 2.0 3.0 ns tasu Array clock setup time | (2) 14 1.0 08 ns tay Array clock hold time | (2) 0.8 0.8 19 ns taco1 Array clock to output | C1 = 35 pF (2) 44 5.2 1.0 6.2 ns delay tacu Array clock high time 2.0 2.0 3.0 ns tacL Array clock low time 2.0 2.0 3.0 ns tent Minimum global clock | (2) 5.2 5.5 64 ns period font Maximum internal (2), (3) 192.3 181.8 156.3 MHz global clock frequency tacnt Minimum array clock | (2) 5.2 5.5 64 ns period Tacnt Maximum internal (2), (3) 192.3 181.8 156.3 MHz array clock frequency Tmax Maximum clock (4) 250.0 250.0 166.7 MHz traquency Altera Corporation 625MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 18. MAX 7O00AE Internal Timing Parameters Notes (1), (7) Symbol Parameter Conditions Speed Grade Unit 4 5 6 Min | Max | Min | Max | Min | Max tiny Input pad and buffer delay 0.3 03 03 ns tio lO input pad and butter delay 0.3 0.3 03 ns tein Fast input delay 2.6 2.6 24 ns tsexp Shared expander delay 1.9 2.4 28 ns tpexp Parallel expander delay 0.5 0.6 05 ns trap Logic array delay 1.9 2.5 25 ns trac Logic control array delay 1.8 2.3 25 ns toe Internal cutout enable delay 0.0 0.0 02 ns topr Output buffer and pad delay C1 = 35 pF 0.3 0.4 03 ns slow slow rate = off Vecio = 3.3 tone Output buffer and pad delay C1 = 35 pF (5) 0.8 0.9 08 ns slow slow rate = off Veco =2.5V tons Output buffer and pad delay C1 = 35 pF 5.3 5.4 53 ns slow slew rate = on Vecio =25Vor3.3aV tox Output buffer enable delay C1 = 35 pF 4.0 4.0 40 ns slow slow rate = off tyxe Output buffer enable delay C1 = 35 pF (5) 4.5 45 45 ns slow slow rate = off tog Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 ns slow slew rate = on Vecio =25Vor3.3aV iy Output buffer disable delay C1 =5pF 4.0 4.0 40 ns tou Register setup time 14 0.8 1.6 ns ty Register hold time 0.8 1.0 17 ns tesu Register setup time of fast input 0.9 08 12 ns toy Register hold time of fast input 1.6 1.7 13 ns tap Register delay 1.2 14 16 ns tcome Combinatorial delay 1.3 1.0 16 ns tic Array clock delay 1.9 2.3 27 ns ten Register enable time 1.8 2.3 25 ns teros Global control delay 1.0 0.9 14 ns toar Register preset time 2.3 2.6 23 ns torr Register clear time 2.3 2.6 23 ns tpia PIA delay (2) 0.7 0.8 13 ns tipa Low-power adder (6) 12.0 12.0 11.0 ns 626 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 79. MAX 7000AE External Timing Paramefers Notes (1), (7) Symbol Parameter Conditions Speed Grade Unit 7 -10 12 Min | Max | Min | Max | Min | Max tpp1 Input to nen- C1 = 35 pF (2) 7.5 10.0 12.0 ns registered output tepe \/ input to non- C1 =35 pF (2) 75 10.0 12.0 ns registered output tsu Global clock setup (2) 49 6.6 7.8 ns time ty Global clock hold time | (2) 0.0 0.0 0.0 ns tesu Global clock setup 3.0 3.0 3.0 ns time of fast input tey Global clock hold time 0.0 0.0 0.0 ns of fast input teoi Global clock to output | C1 = 35 pF 1.0 45 1.0 5.9 1.0 71 ns delay tou Global clock high time 3.0 4.0 5.0 ns te Global clock low time 3.0 4.0 5.0 ns tasu Array clock setup time | (2) 1.6 2.1 2.4 ns tay Array clock hold time | (2) 2.1 3.4 44 ns taco Array clock to output | C1 =35 pF (2) 7.8 10.4 12.5 ns delay tacu Array clock high time 3.0 40 5.0 ns tact Array clock low time 3.0 4.0 5.0 ns tent Minimum global clock | (2) 8.4 11.2 13.3 ns period font Maximum internal (2), (3) 119.0 89.3 75.2 MHz global clock frequency tacnt Minimum array clock | (2) 8.4 11.2 13.3 ns period tacnt Maximum internal (2), (3) 119.0 89.3 75.2 MHz array clock frequency tax Maximum clock (4) 166.7 125.0 100.0 MHz frequency Altera Corporation 627MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 20. MAX 7O000AE Internal Timing Parameters Notes (1), (7) Symbol Parameter Conditions Speed Grade Unit 7 10 12 Min | Max | Min | Max | Min | Max tiny Input pad and butfer delay 0.4 0.6 07 ns tio /O input pad and buffer delay 0.4 0.6 07 ns tan Fast input delay 3.3 3.7 41 ns isexp Shared expander delay 3.6 49 5.9 ns tpexp Parallel expander delay 0.8 14 1.3 ns trap Logic array delay 3.7 5.0 6.0 ns trac Logic control array delay 3.4 46 5.6 ns tor Internal cutput enable delay 0.0 0.0 0.0 ns ton Qutput buffer and pad delay C1 =35 pF 06 0.7 0.9 ns slow slew rate = off Veoio =3.3V tone QCutput buffer and pad delay C1 =35 pF (5) 1.1 1.2 14 ns slow slew rate = off Vooio =2.5V tong Output butter and pad delay C1 = 35 pF 5.6 57 5.9 ns slow slew rate = on Vecio =25Vor3.3aV tad QCutput buffer enable delay C1 =35 pF 40 5.0 5.0 ns slow slew rate = off tye Cutput buffer enable delay C1 =35 pF (4) 45 5.5 5.5 ns slow slew rate = off tng Output butter enable delay C1 = 35 pF 9.0 10.0 10.0 ns slow slew rate = on Vecio =25Vor3.3V iz OCutput buffer disable delay Ci =5pF 40 5.0 5.0 ns isu Register setup time 1.3 17 2.0 ns ty Register hold time 2.4 3.8 48 ns troy Register setup time of fast input 11 11 11 ns toy Register hold time of fast input 1.9 1.9 1.9 ns tap Register delay 2.1 2.8 3.3 ns tcome Combinatorial delay 1.5 2.0 24 ns tic Array clock delay 3.4 46 5.6 ns ten Register enable time 3.4 46 5.6 ns tgtop Global control delay 1.4 1.8 2.2 ns tppe Register preset time 3.9 5.2 6.2 ns torr Register clear time 3.9 5.2 6.2 ns tpra PIA delay (2) 1.3 17 2.0 ns tipa Low-power acder (6) 10.0 10.0 10.0 ns 628 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Nates fo tables: (1) These values are specified in Table 10 on page 616. (2) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. (3) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. (4) The fyyay values represent the highest frequency for pipelined data. (5) Operating conditions: Veejg = 2,540.2 V for commercial and industrial use. (6) The f;p4 parameter must be added to the tyan, frac: fic, Lacy, fen, and fsexp parameters for macrocells running in low-power mode. (7) MAX 7000AE timing values are preliminary. Power Supply power (P) versus frequency (fax, in MHz) for MAX 7000A . devices is calculated with the following equation: Consumption P= Pinr + Plo = Iceinr X Veer + Plo The Pyg value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices} in this data book. The Iccqyt Value depends on the switching frequency and the application logic. The Iccqyy value is calculated with the following equation: lecinr = (A xX MCyon) + [Bx (MCory MCron)] + (C X MCusap X fMax X togic) The parameters in this equation are: MCyon = Number of macrocells with the Turbo Bit option turned on, as reported in the MAX+PLUS I Report File (.rpt) MCprpy = Number of macrocells in the device MCusep = Total number of macrocells in the design, as reported in the Report File fMax = Highest clock frequency to the device togic = Average percentage of lopic cells togpling at each clock (typically 12.5%) A,B,C = Constants, shown in Table 21 Altera Corporation 629MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information 630 Table 217. MAX 7000A Iec Equation Constants Device A B C EPM7032AE (1) 0.46 0.28 0.032 EPM7064AE (1) 0.46 0.28 0.032 EPM7128A (1) 0.46 0.28 0.032 EPM7128AE (1) 0.46 0.28 0.032 EPM7256A (1) 0.46 0.28 0.032 EPM7256AE (1) 0.46 0.28 0.032 EPM7512AE (1) 0.46 0.28 0.032 Note: (1) Values tor these devices are preliminary. This calculation provides an I-- estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output lead. Actual I should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Figure 13 shows the typical supply current versus frequency for MAX 7OO0A devices. Figure 13. leg vs. Frequency for MAX 7000A Devices (Part 1 of 2) EPM7032AE Typical log Active (mA) 79 EPM7064AE - sor Von = 3.3 | Room Temperature 1823 Miz *0 L zo b L BOF b > hat Sper sob Typical loc Active (mA) 40 Veo =3.3 V Room Temperature ~ High Soest 681 MHz 30 58 1 MHz Lo Bo Mone Turba 20 * Abate Tube EPM?128A & EPM?128AE 120 160 140 120 Typical lec 100 Active (mA) e0 60 40 20 L job 1 1 1 1 J 0 50 400 150 200 250 9 Frequency (MHz} Von = 3.3 V Room Temperature 181 8 MHz * Bagi: Stovest 56 17 MHz * ~ Fe "Low Bear 0 50 100 150 200 250 Frequency (MHz) Altera Corporation 0 100 150 200 250 Frequency (MHz} 631MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Figure 13. pe vs. Frequency for MAX 7000A Devices (Part 2 of 2) EPM7256A4 & EPM7256AE EPM7512AE 600 - 350 |- Ven =3.3V Voo = 3.3 V Room Temperature soo b Reom Temperature 300 |- 156 3 MHz 118 MHz 250 |- 4o0 Typical Ine 200 + Typical lng a Active (mA) eal Speed Active (mA) 300 mo High Suess . 59.76 MHz 7 14 MHz 100 Oa 200 Ca Lew Power Lew Pawar SO - too F 1 1 1 1 1 1 1 1 1 1 J 0 =0 100 160 200 o 20 40 60 80 100 120 140 Frequency (MHz=) Frequency (MHz} D evi ce Tables 22 through 32 show the pin names and numbers for the pins in MAX 7000A and MAX7OQ0AE device packages. Pin-Quts 632 Table 22. EPM7032AE Dedicated Pin-Outs Dedicated Pin 44-Pin PLCC 44-Pin TOFP INPUT/GCLK1 43 37 INPUT /GCLRn 1 39 INPUT/OE1 44 38 INPUT /OBZ/GCLKZ 2 40 TDI (7) 7 1 TMs (7) 13 7 TCK (7) 32 26 TDO (7) 38 32 GNDINT 2, 42 16, 36 GNDIOC 10, 30 4,24 VCCINT (3.3 V) 3, 23 17, 41 vecro (2.5 Vor 3.3 V) 15, 35 9,29 No Connect (N.C.) - - Total User I/O Pins (2) 36 36 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 23. EPM7032AE 1/0 Pin-Outs LAB Mc 44-Pin 44-Pin LAB Mc 44-Pin 44-Pin PLCC TOFP PLCC TOFP A 1 4 42 B 17 41 35 2 5 43 18 40 34 3 6 44 19 39 33 4 7 ft) 1 (1) 20 38 (1) 32 (1) 5 8 2 21 37 31 6 9 3 22 36 30 7 11 5 23 34 28 8 12 6 24 33 ef 9 13 (1) 7 (1) 25 32 (1) 26 (1) 10 14 8 26 31 25 11 16 10 27 29 23 12 17 11 28 28 22 13 18 12 29 27 21 14 19 13 30 26 20 15 20 14 31 25 19 16 21 15 82 24 18 Altera Corporation 633MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 24. EPM7064AE Dedicated Pin-Outs Dedicated Pin 44-Pin 44-Pin 100-Pin 100-Pin PLCC TOFP TOFP FineLine BGA INPUT/GCLK1 43 37 87 AG INPUT/GCLRn 1 39 89 B5 INPUT/OE1 44 38 88 B6 INPUT/OB2/GCLK2 2 40 30 A5 TDI (7) 7 1 4 Al TMs (7) 13 7 15 F3 TCK (7) 32 26 62 F8 Too (Tt) 38 32 73 A1O GNDINT 22, 42 16, 36 38, 86 C3, D6, D7, E5, F6, G4, G5, H8 GNDIO 10, 30 4, 24 11, 26,48, 59,74, |- 95 VCCINT (3.3 V Only) 3, 23 17,41 39, 51 D5, G6 vecro (25 Var3.3V) 15,35 9, 29 3,18, 34, 51, 66, 82|C8, D4, E6, F5, G7, H3 No Connect (N.C.) - - 1,2, 5, 7, 22, 24, Bi, B10, C1, CS, 27, 28,49, 50,53, |C10, D8, E83, E4, 55, 70, 72, 77,78 |H1, H9, H10, J1, J2, J10, Ki, KS Total User I/O Pins (2) 36 36 68 68 634 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 25. EPM7064AE 1/0 Pin-Outs (44-Pin PLCC & 44-Pin TQFP Packages) LAB MC 44-Pin 44-Pin LAB MC 44-Pin 44-Pin PLCC TOFP PLCC TQFP A 1 12 6 Cc 33 24 18 2 - - 34 - - 3 11 5 35 25 19 4 3 36 26 20 5 2 37 27 21 8 - - 38 - - 7 - - 39 - - 8 7 (1) 1 (7) 40 28 22 9 - - 41 29 23 10 - - 42 - - 11 6 44 43 - - 12 - - 44 - - 13 - - 45 - - 14 5 43 46 31 25 15 - - 47 - - 16 4 42 48 32 (1) 26 (71) B 17 21 15 D 49 33 27 18 - - 50 - - 19 20 14 51 34 28 20 13 13 52 36 30 21 18 12 53 37 31 22 - - 54 - - 23 - - 55 - - 24 17 11 56 38 (1) 32 (1) 25 16 10 57 39 33 26 - - 48 - - ef - - 59 - - 28 - - 60 - - 29 - - 61 - - 30 14 8 62 40 34 31 - - 63 - - 32 13 (7) 7 (7) 64 41 35 Altera Corporation 635MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 26. EPM7064AE 1/0 Pin-Outs (100-Pin TOFP & 100-Pin FineLine PGA Packages) LAB Nc 100-Pin 100-Pin LAB Mc 100-Pin 100-Pin TOFP FineLine TOFP FineLine BGA BGA A 1 14 F4 Cc 33 40 K6 2 13 E2 34 41 J6 3 12 E1 35 42 H6 4 10 De 36 44 K7 5 g DI 37 45 J7 6 8 D3 38 46 H7 7 6 ce2 39 47 J8 8 4 (1) At (1) 40 48 K8 ) 100 B2 41 52 K10 10 99 A2 42 54 J9 11 98 A3 43 56 er) 12 97 B3 44 57 G10 13 96 A4 45 58 G8 14 94 B4 46 60 FS 15 83 C4 47 61 F1i0 16 g2 C5 48 62 (1) F8 (1) B 17 37 K5 D 49 63 F7 18 36 J5 50 64 E9 19 35 H5 51 65 E10 20 33 K4 52 67 E8 21 32 J4 53 68 E7 22 31 H4 54 69 bg 23 30 J3 55 71 Dio 24 29 K3 56 73 (1) AiO (7) 25 25 K2 57 75 Ba 26 23 H2 48 76 AQ 27 21 G2 59 79 A8 28 20 Gt 60 80 B8 29 19 G3 61 at AZ 30 17 Fe 62 83 B7 31 16 Fi 63 84 C7 32 15 (1) F3 (1) 64 85 ce Notes ta tables: (1) (2) 636 This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports tor in-system programming, this pin is not available as a user I/O pin. The user I/O pin count includes dedicated input pins and all I/O pins. Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 27. EPM7128A & EPM7128AE Dedicated Pin-Outs (2) Dedicated Pin 84-Pin | 100-Pin | 100-Pin | 144-Pin 256-Pin PLCC TOFP | FineLine}| TQFP FineLine BGA BGA INPUT/GCLE1 8&3 87 AG 125 DS INPUT/GCLRn 1 89 B5 127 E8 INPUT/OE1 84 88 B6 126 ES INPUT/ORZ/GCLKZ |2 90 AS 128 D8 TDI (1) 14 4 Al 4 D4 TMs (7) 23 15 F3 20 J6 TCK (7) 62 62 F& 8&9 J11 TRe (7) 71 73 AiO 104 D13 GNDINT 42, 82 38, 86 D6, G5 52, 57, A8, C9, GO, K8, PS 124, 129 GNDIO 7, 19, 32, | 11, 26, C3,D7, |38,13,17, |A8, B10, Ce, B14, F, G10, H8, JS, K7, 47,59, 72]43, 59, E5, F6, 33,59, 64, |L11, M3, P6, P10, R2, R3, 71, 715 74,95 G4, H8 85, 105, 135 VCCINT 3, 43 39,91 D5, G6 51, 58, BS, C8, G8, KS, P8& (3.3 V only) 123, 130 VCCIO 13, 26, 3,18, 34, |C8,D4, |24, 50,73, ]B3, B5, C14, E15, Fl1, G3, G7, G15, H9, (2.5 Vor3.3 V) 38, 53, 51, 66, 82|E6, F5, 76, 95, J8, K10, L3, L6, M15, P14, T2, T3 66, 78 G7, H3 115, 144 No Connect (N.C.)) [- - - 1, 2, 12, Al, A2, A4, A5, A6, A7, AS, A10, All, Al2, 19, 34, 35, | A13, Al4, A15, A16, B1, Be, B4, B6, B7, 36,43, 46, |B8, B11, B12, B13, B14, B15, B16, C1, 47, 48,49, |C3, C4, C6, C11, C13, C15, C16, D1, D2, 66, 75,90, |]D3, D15, D16, E1, E2, E3, E14, E16, F1, 103,108, |Fe, F15, F16, G1, G2, G14, G16, H1, He, 120,121, |H15, H16, J1, J2, J15, J16, K1, K2, K3, 122 K14, K15, K16, L1, L2, L15, L16, M1, M14, M16, Ni, N2, N3, N14, N15, N16, P1, Pe, P3, P4, P12, P13, P15, P16, R1, R4, Rd, R6, R7, R8, R98, R11, R12, R13, R14, R15, R16, T4, T5, T6, T7, T8, TS, T10, 711, 712, T13, 714, 716 Total User YO Pins | 68 84 84 100 100 Altera Corporation 637MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 28. EPM7128A & EPM7128AE 1/0 Pin-Outs (Part 1 of 2) LAB} MC | 84-Pin| 100- | 100-Pin |144-Pin} 256-Pin | LAB} MC | 84-Pin| 100- | 100-Pin | 144- | 256-Pin PLCC | Pin | FineLine} TOFP | FineLine PLCC | Pin |FineLine} Pin | FineLine TOFP | BGA BGA TQFP | BGA | TQFP | BGA A {1 - 2 Cl 143 F4 G {33 [- 25 Ki 32 N4 2 |- - - - - 34 |- - - - - 3 |12 1 Bt 142 E4 35 [31 24 J1 31 M4 4 |- - - 141 cs 36 |- - - 30 M2 5 14 100 B2 140 E5 37 130 23 H1 29 L4 6 10 99 A2 139 D5 38 |29 22 H2 28 L5 7 - - - - - 39 |- - - - - 8 9 98 AS 138 D 40 |28 21 G2 27 K5 9 - 97 Bs 137 E6 a 20 G1 26 K4 10 |- - - - - 42 |- - - - - 11 18 96 A4 136 D7 43 |27 19 G3 25 K6 12 |- - - 134 [C7 44 |- - - 23 J3 13 |6 94 B4 133 E7 45 [25 17 F2 22 J5 14 {5 93 C4 132 F7 46 |24 16 Ft 21 J4 150 |- - - - - 47 |- - - - - 16/4 92 C5 131 F8 48 |23 (1) [15 (7) |F38 (7) |20 (7) |J6 (7) B |17 |22 14 F4 18 J7 D |49 |41 37 K5 56 Ng 18 |- - - - - 50 |- - - - - ig j21 13 E2 16 H5 51 |40 36 J5 55 Ma 20 |- - - 15 H3 52 |- - - 54 P7 21 |20 12 El 14 H4 53 1/39 35 H5 53 L 22 |- 10 E3 11 H6 54 [- 33 K4 45 N7 23) |- - - - - 55 |- - - - - 24 118 9 E4 10 H7 56 [37 32 J4 44 M7 25 117 8 De 9 GS 57 [36 31 H4 42 L7 26 |- - - - - 58 |- - - - - 27 116 7 D1 8 G4 59 [35 30 J3 41 M6 28 |- - - 7 F3 60 |- - - 40 PS 29 | 15 6 D3 6 G6 61 134 29 K3 39 N 30 |- 5 C2 5 F5 62 |- 28 J2 38 M5 31 |- - - - - 63 |- - - - - 32. )14 (7) [4 (1) |A1 (7) |4(1) |D4 (1) 64 133 27 Kz 37 N5 638 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 28. EPM7128A & EPM7128AE 1/0 Pin-Outs (Part 2 of 2) LAB | MC | 84-Pin| 100- | 100-Pin |144-Pin| 256-Pin | LAB} MC | 84-Pin| 100- | 100-Pin | 144- | 256-Pin PLCC Pin | FineLine | TQFP | FineLine PLCC Pin |FineLine| Pin | FineLine TOFP BGA BGA TOFP BGA TOFP BGA E |65 1/44 40 K6 60 Ng G |97 163 63 F7 91 J10 66 |- - - - - 98 |- - - - - 67 |45 41 J6 61 M3 99 |64 64 ES 92 H12 68 |- - - 62 R10 100 |- - - 93 H14 69 |46 42 H6 63 L9 101 165 65 E10 94 H13 7O |- 44 K7 65 NiO 102 |- 67 E8 96 H11 71 oJ- - - - - 103 |- - - - - 72 |48 45 J7 67 Mio 104 |67 68 E7 97 H10 73 |49 46 H7 68 Lio 105 168 69 DBS 98 G12 74 |- - - - - 106 |- - - - - 75 150 47 J8 69 M11 107 163 70 Did 99 G13 76 |- - - 70 P41 108 | - - 100 Fi4 77 =(|51 48 K8 71 N11 108 |70 71 D8 101 Gi 78 |- 49 KS 72 Ni2 110 |- 72 cg 102 Fil2 73a |- - - - - 111 J- - - - - 80 152 50 K10 74 N13 112 |71 (7) | 73 (7) |A10 (7) | 104 (7)|D13 (7) F jai |- 52 J10 77 M13 H |113 |- 75 c10 106 Fi3 82 |- - - - - 114 |- - - - - 83 154 53 H10 78 L13 115 173 76 Bio 107 E13 84 |- - - 79 L14 116 |- - - 109 Cle 85 |55 54 Hg 80 Li2 117 |74 7f BS 110 El2 86 [56 55 J3 81 Mi2 118 175 78 AS 111 Di2 87 |- - - - - 119 |- - - - - 88 |57 56 G3 82 Kile 120 |76 79 A8& 1i2 D11 gg |- 57 G10 83 K13 j2i |- 80 B8 113 E11 90 |- - - - - 122 |- - - - - 91 |58 58 G8 84 K11 123 |77 81 AZ 114 D10 92 |- - - 86 J14 124 |- - - 116 C10 93 |60 60 Fg 87 J12 125 |73 83 B7 117 E10 94 |61 61 F10 88 J13 126 |80 84 C7 118 F10 95 |- - - - - 127 |- - - - - 96 |62 (7) |62 (7) | F8 (7) 89 (7) | J11 (7) 128 |81 85 C 119 Fg Nates fo tables: This pin can function as either a JTAG port ora user I/O pin. If the device is configured to use the JTAG ports for BST or in-system programming, this pin is not available as a user I/O pin. The user I/O pin count includes dedicated input pins and all 1/O pins. () (2) Altera Corporation 639MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 29. EPM7256A & EPM7256AE Dedicated Pin-Outs Dedicated Pin 100-Pin TQFP | 144-Pin TOFP | 208-Pin POFP 256-Pin FineLine BGA INPUT/GCLK1 87 125 184 Bg INPUT/GCLRna 89 127 182 E8 INPUT /OB1 88 126 183 E9 INPUT/OER2/GCLK2 |90 128 181 D8 TDI (7) 4 4 176 D4 TMs (1) 15 20 127 J TCK (1) 62 89 30 J11 TDO (7) 73 104 189 B13 GNDINT 38, 86 52, 57, 124, 129|75, 82, 180,185 |A8, CS, G9, K8, PS GNDIO (2) 11, 26,43,59, |3,13,17,33, |14,32,50,72, |AS8, B10, C2, D14, F6, G10, H8, 74, 95 59, 64, 85, 105, |94, 116, 134, J8, K7, L11, M3, P6, P10, R2, 135 152, 174, 200 R38, 71, 715 VCCINT (3.3 V Only) |39, 91 51,58, 123, 130|74, 83, 179,186 |B9, C8, G8, KS, Ps VCCIo (2.5 Vor3.3 V)13, 18,34,51, |24,50, 73,76, |5, 23, 41,63, 85, |B3, B5, C14, E15, F11, G3, G7, (2) 66, 82 95,115, 144 107, 125, 148, G15, H9, J8, K10, L3, L6, M15, 165, 191 P14, T2, T3 No Connect (N.C.} - - 1, 2,51, 52,53, |A1, A2, A6, Al2, A13, A14, A15, 54, 103, 104, A16, B1, B2, B15, B16, C1, C15, 105, 106, 155, C16, D1, D3, D15, D16, Gi, 156, 157, 158, G16, H15, H16, J1, K1, L1, L2, 207, 208 M1, M16, Ni, N2, N14, N15, N16, P1, P2, P15, P16, R1, R14, R15, R16, T7, T8, 710, 711, 714, T16 Total User I/O Pins (3) | 84 120 164 164 640 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 30. EPM7256A & EPM7256AE 1/0 Pin-Outs (Part 1 of 4) LAB | MC | 100-Pin | 144-Pin | 208-Pin | 256-Pin | LAB | MC | 100-Pin | 144-Pin|208-Pin| 256-Pin TOFP | TOFP | POFP | FineLine TOFP | TOFP | POFP | FineLine BGA PGA A {1 - - 153 C3 G 133 - 36 108 N4 2 - - - - 34. |= - - - 3 - 2 154 C4 35 - 35 109 P3 4 - - - - 36s - - - 5 - 1 159 E5 37 - 34 110 N3 6 - 143 160 D5 38 - - 111 M4. 7 - - - - 39 |[- - - - 8 2 - 161 C5 40 25 32 112 M2 g 1 - 162 B4 At 24 31 113 L4 10 - - - - 42 - - - - 11 100 142 163 A4 43 23 30 114 L5 12 - - - - 44 - - - - 13 - 141 164 AS 45 22 29 115 K6 14 99 140 166 D6 46 - - 117 K5 15 - - - - 47 - - - - 16 98 139 167 C6 48 21 28 118 K4 B |1i7 J- - 141 F5 D |49 31 44 92 N6 ig |- - - - 50. | - - - - 19 - 190 142 Fe 51 30 43 93 TS 20. | - - - 52. | - - - 21 - 9 144 E1 53 29 42 95 M6 22 - - 145 F4 54 28 4) 96 R5 ee - - - 55 [= - - - 24 8 8 146 F3 56 - 40 97 M5 25 7 7 147 E2 57 - - 98 P5 26 |- - - - 58 |= - - - 27 6 6 148 D2 59 - 39 99 N5 2g |- - - - 60 |- - - - 29 5 5 149 E3 61 - 38 100 T4 30 |- - 150 E4 62 - - 101 R4 31. |- - - - 63. o|- - - - 32 14/1) 4 (1) 151 D4 (7) 64 27 37 102 P4 Altera Corporation 641MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 30. EPM7256A & EPM7256AE 1/0 Pin-Outs (Part 2 of 4) LAB | MC | 100-Pin | 144-Pin | 208-Pin | 256-Pin | LAB | MC | 100-Pin | 144-Pin | 208-Pin| 256-Pin TOFP | TOFP | POFP | FineLine TQFP | TOFP | POFP | FineLine BGA BGA E |j65 |- - 168 B G |97 J- - 119 K3 66 |- - - - a - - - 67 |- - 169 E6 99 |- 27 120 K2 68 - - - - 100 |- - - - 69 - 138 170 F7 101 |- 26 121 J7 7O |- - 171 E7 102 |- - 122 H7 710 - - - 103 |- - - - 72 197 137 172 D7 104 |20 25 123 J5 73 196 136 173 C7 105 |19 23 124 J2 74 |- - - - 106 |- - - - 75 194 134 175 B7 107 117 22 126 J3 76 |- - - - 108 |- - - - 77. ~+|93 133 176 (1) |A7 jo9 |16 24 127 (1) |J4 78 I- 132 177 F8 tio |- - 128 H6 79 [- - - - qi [- - - - go | 92 131 178 Bs 112 115 (7) 20/1) |129 J6 (1) F jai |- - 130 H5 H 1113 |37 - 79 M8 g2. | - - - - 114 |- - - - 83 - 19 131 Hi 115 |36 54 80 N8 84 |- - - - die |- - - - 85 |- 18 132 H2 117 |- 53 81 L8 86 - - 133 H3 118 |35 - 84 R7 87 I- - - - 119 |- - - - 88 114 16 135 H4 120 |- 49 86 P7 8g (1/13 15 136 G6 121 |- 48 87 N7 90 |- - - - 122 |- - - - 91 1/12 14 137 G5 123 |- 47 88 M7 92 |- - - - 124 |- - - - 93 | 10 12 138 G2 125 |33 46 89 L7 94 |- - 139 G4 126 |- - 90 T 95 |- - - - 127 |- - - - 96 (|9 11 140 Fi 128 |32 45 91 R6 642 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 38. EPM7256A & EPM7256AE {/0 Pin-Outs (Part 3 af 4) LAB | MC | 100-Pin | 144-Pin| 208-Pin | 256-Pin | LAB | MC | 100-Pin | 144-Pin|208-Pin| 256-Pin TOFP | TOFP | POFP | FineLine TOFP | TOFP | POFP | FineLine BGA PGA | 1128 |80 114 187 C11 K [161 J- - 38 K11 130 |- - - - 162 |- - - - 131 |81 116 196 B11 163 |57 82 37 K12 132 |- - - - 164 |- - - - 133 |- 117 195 All 165 |- 83 36 K14 134 |- - 194 Fio 166 |- - 35 K13 135 |- - - - 167 |- - - - 136 |- 118 183 E10 168 |58 84 34 K15 137 |- 119 192 A10 169 |- 86 33 K16 138 |- - - - 170 |- - - - 139 |83 120 180 C10 171 60 87 31 J13 140 |- - - - 172 |- - - - 141 |84 121 189 (7) |D10 173 |61 88 30 (1) |J14 142 |- - 188 F9 174 |- - 29 J12 143 |- - - - 175 |- - - - 144 185 122 187 Ag 176 |62 (7) |89 (7) |28 J11 (7) J 145 163 - 27 J15 L 177 J- - 78 R8 146 |- - - - 178 |- - - - 147 |64 30 26 J16 179 |- 55 77 T3 148 |- - - - 180 |- - - - 149 |65 91 25 J10 181 - 56 76 R93 150 |- - 24 H14 182 |- - 73 Ng 151 |- - - - 183 |- - - - 152 |- 92 22 H13 184 |40 60 71 M9 153 |- 93 2) Hi2 185 |41 61 70 LS 154 |- - - - 186 |- - - - 155 |67 94 20 H11 187 |42 62 69 R10 156 |- - - - 188 |- - - - 157 |- 96 19 H10 189 |44 63 68 N10 158 |- - 18 G11 190 |- - 67 M10 159 |- - - - isi |- - - - 160 |68 97 17 Gi4 192 |45 65 66 L10 Altera Corporation 643MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 38. EPM7256A & EPM7256AE 1/0 Pin-Outs (Part 4 of 4) LAB | MC | 100-Pin | 144-Pin| 208-Pin | 256-Pin | LAB | MC | 100-Pin | 144-Pin |208-Pin| 256-Pin TOFP | TOFP | PQFP | FineLine TOFP | TOFP | POFP | FineLine BGA BGA M |193 |- 106 4 B14 O |225 |- - 49 R13 194 |- - - - 226 |- - - - 195 |75 107 3 C13 227 |- 74 48 P13 i96 |- - - - 228 |- - - - 197 |- 108 206 B13 229 |- 75 47 N13 198 |- - 205 Fi2 230 |- - 46 M14 i99 |- - - - 231 |- - - - 200 |- 109 204 El2 232 [52 77 45 M13 201 76 110 203 Di2 233 153 78 44 L13 202 |- - - - 234 |- - - - 203 |77 111 202 C12 235 [54 79 43 L14 204 |- - - - 236 |- - - - 205 |- - 201 Bil2 237 [55 80 42 Li2 206 |78 112 199 E11 238 |- - 40 L15 207 |- - - - 239 |- - - - 208 |79 113 198 D11 240 [56 81 39 L16 N |209 |- - 16 G13 P |241 |46 66 65 Ri1 210 |- - - - 242 |- - - - 211 |69 98 15 Gle 243 |47 67 64 P11 212 |- - - - 244 |- - - - 213 |- 99 13 F16 245 |48 68 62 N11 214 |- - 12 F1i5 246 |49 69 61 M11 215 |- - - - 247 |- - - - 216 |70 100 11 F13 248 |- - 60 T12 217 |- 101 10 F14 249 |- 70 59 R12 218 |- - - - 250 |- - - - 219 |71 102 9 E16 251 |- - 58 Mi2 220 |- - - - 252 |- - - - 221 |72 103 8 E14 253 |- 71 57 P12 222 |- - 7 E13 254 |- - 56 N12 223 |- - - - 255 |- - - - 224 173(1) |104 (1) |6 D13 (7) 256 |50 72 55 Ti3 644 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Notes fo tables: (1) This pin can function as either a JTAG pin ora user 1/0 pin. If the device is programmed to use the JTAG ports for BST or in-system programming, this pin is not available as a user I/O pin. (2) EPM7512AE devices in the 208-pin PQFP package support vertical migration trom EPM7256E, EPM72565S, and EPM7256A devices. EPM7512AE devices contain additional I/O pins which are no connects on the EPM7256E, EPM?72565, and EPM7256A devices. To support these additional I/O pins, EPM7512AE devices have two additional VCCIO (pins 105 and 207) and GNDIO (pins 51 and 158) pins that are no-connect pins on the EPM7256E, EPM72568, and EPM7256A devices. To achieve vertical migration between the EPM7256A and EPM7512AE devices, the no- connect pins 105 and 207 may be tied tovcc10 and pins 51 and 158 may be tied to GND IO on the EPM7256A devices. On the EPM7256E and EPM7256S devices, these no-connect pins must not be tied to VCCIO or GNDIO. (3) The user I/O pin count includes dedicated input pins and all I/O pins. Table 31. EPM7512AE Dedicated Pin-Outs Dedicated Pin 144-Pin 208-Pin 256-Pin 256-Pin TOFP POFP (7) BGA FineLine BGA INPUT/GCLK1 125 184 Li Ds INPUT/GCLRn 127 182 K2 E8 INPUT/OE1 126 183 Ki E9 INPUT /OBZ/GCLK2Z 128 181 K3 D8 TDI (2) 4 176 A2 D4 TMS (2) 20 127 Bi2 J TOK (2) 89 30 Vi2 Ji TDO (2) 104 189 Ye D13 GNDINT 52,57, 124, 129 75, 82, 180, 185 J20, K4, K18, L2, |A8, C9, G9, K8, Ps Li7 GNDIO 3,13, 17, 33, 59,64, 114, 32, 50,51, 72, |A1, B2,B19,B20, |A3, B10, C2, D14, 85, 105, 135 94,116,134,152, |C3,C18,D4,D17, |F6, G10, H8, J9, K7, 158, 174, 200 U4, U17, V3, V18, |L11, M3, P6, P10, V19, We, W19, Y1, |R2,R3, 71, 715 Y20 VCCINT 51, 58, 123, 130 74, 83, 179, 186 J1, J19, L4, M19, |B9, C8, G8, K9, P8 M20 VCCLO 24 50, 73, 76, 5, 23,41,63,85, |C4,C17,D3,D5, |B3, B5, C14, E15, 95, 115, 144 105, 107, 125, 148, |D16, D18, E4, E17, |F11, G3, G7, G15, 165, 191, 207 T4, 717, U3, U5, Hs, J8, K10,L38, L6, U16, U18, V2, V4, |M15, P14, T2, T3 V17 No Connect (N.C.} - - - - Total User /O Pins (3) | 120 176 212 212 Altera Corporation 645MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 32. EPM7512AE 1/0 Pin-Outs (Part 1 of 8) LAB | MC | 144-Pin |208-Pin|256-Pin| 256-Pin | LAB | MC |144-Pin| 208-Pin | 256-Pin | 256-Pin TOFP | POFP | BGA |FineLine TOFP | POFP | BGA |FineLine a BGA (1) BGA A 1 134 173 H3 D7 Cc 133 142 163 F4 E4 2 - - - - 34 - - - - 3 - - - - 35 - - - - 4 - - - - 36 - - - - 5 - - H2 C7 37 141 164 E3 C5 6 - - - - 38 - - - - 7 - - - - 39 - - - - 8 - - - - 40 - - - - 9 - 175 H1 B7 41 140 166 E2 AS jo J- - - - 42 - - - - 11 133 176 (2) | J4 A? 43 - 167 F3 D5 Pe - - - 44 - - - - 13 |- - - - 45 - - - - 14 132 177 J3 F8 46 139 168 E1 E5 15 - - - - 47 - - - - 16 131 178 J2 B& 48 - - Fe E6 B |i7 |- 169 G4 D D |49 2 - B3 B2 18 |- - - - 50 - - - - ig |- - - - 51 - - - - 20. |- - - - 52 - - - - 21 138 170 FA C 53 1 - C2 A2 22. |- - - - 54 - - - - 23. |- - - - 55 - - - - 24 | - - - - 56 - - - - 25 | 137 171 G3 Be 57 - 159 Bi B4 26 |- - - - 58 - - - - 27 ~-| 136 172 Ge AG 59 - 160 C1 A4 28 | - - - - 60 - - - - 29 | - - - - 61 - - - - 30. |= - Gt F7 62 - 161 D2 C4 31 - - - - 63 - - - - 32. | - - H4 E7 64 143 162 DI C3 646 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 32. EPM7512AE 1/0 Pin-Outs (Part 2 of 8) LAB | MC | 144-Pin |208-Pin|256-Pin| 256-Pin | LAB | MC |144-Pin| 208-Pin | 256-Pin | 256-Pin TOFP | POFP | BGA |FineLine TOFP | POFP | BGA |FineLine a BGA (1) BGA E j65 |- - BS E3 G |97 - - er) H6 66 |- - - - 98 - - - - 67 |7 153 C5 C1 99 15 141 D9 G5 68 |- - - - 100 |- - - - 69 - - D Bi 101 14 142 A8 G4 70 |- - - - 102 |- - - - 71 - - - - 103 |- - - - 72 |- - - - 104 |- - - - 73 - 154 A4 Al 105 - 144 B8 G2 74 |- - - - 106 |- - - - 75 6 155 B4 D2 107 - 145 C8 Gi 76 |- - - - tos) |- - - - 77 |- - - - 109 |- - - - 78 | 5 156 A3 D3 110} 12 146 Ds G6 79 |= - - - Wi [- - - - so 64/2) +1157 JA2 (2) | D4 (2) 112 |- - AT F5 F 181 - 147 BY F2 H 113 19 135 All Ji 82 - - - - 114 |[- - - - 83 - 148 C7 F3 115 - 136 A10 H7 84s - - - 116 |- - - - 85 11 149 AG Fi 117 18 137 Bio H5 a - - - 118 |- - - - a7 |- - - - tig |= - - - a8 | - - - 120 |- - - - 8g - - D7 F4 121 - - Di0 H2 90 |- - - - 122 |- - - - 91 10 150 B6 El 123 - 138 C10 H3 92 |- - - - 124 |- - - - an - - - 125 |- - - - 94 9 151 AS D1 126 - 139 Ag H1 95 |- - - - 127 |- - - - 96 (|8 - C6 E2 128 | 16 140 Bg H4 Altera Corporation 647MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 32. EPM7512AE 1/0 Pin-Outs (Part 3 of 8) LAB | MC | 144-Pin |208-Pin|256-Pin| 256-Pin | LAB | MC |144-Pin| 208-Pin | 256-Pin | 256-Pin TOFP | POFP | BGA |FineLine TOFP | POFP | BGA |FineLine a BGA (1) BGA | 129 |- - Di2 K1 K |161 29 115 Bi N4 130 |- - - - 162 |- - - - 131 - 12g Ci2 J7 163 - 117 C15 M2 132 = |- - - - 164 - - - - 133 |20(2) |130 B12 (2) | J6 (2) 165 |- 118 AI7 M1 134 |- - - - j66 |- - - - 135 |- - - - 167 |- - - - 136 |- - - - 168 |- - - - 137. |- 131 Ai2 J5 169 |28 119 B15 M4. 138 |- - - - 170 |- - - - 139 |[- - Dit J4 171 |[- - D14 M5 140 |- - - - 172. |- - - - 141 J- - - 173 |- - - - 142 |- 132 C11 J3 174 - 120 Al6 L5 143) |- - - - 175 - - - - 144 |- 133 Bit J2 176 27 121 A15 L4 J 7145 [- 122 C14 L2 L 177 34 109 A20 Ri 146 |[- - - - 178 |- - - - 147. |- - Bi4. | Lt 179 |- - - - 148 |- - - - iso [- - - - 149 =|26 123 Al4 K6 181 32 110 Aig P2 150 |- - - - 182 |- - - - 151 |- - - - is3[- - - - 152 |- - - - 184 [- - - - 153 | 25 124 D13 K5 185 |- 114 B17 N3 154 |- - - - ise [- - - - 155 123 126 Ci3s | K4 187 [- 112 Ai8 N2 156 |- - - - 188 |- - - - 157 |- - - - 189 |- - - - 158 22 127 (2) |B13 K3 190 31 113 D15 P1 159 |- - - - 191 - - - - 160021 128 A13 K2 192 30 114 C16 Ni 648 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 32. EPM7512AE 1/0 Pin-Outs (Part 4 of 8) LAB | MC |144-Pin|208-Pin|256-Pin| 256-Pin | LAB | MC |144-Pin| 208-Pin | 256-Pin | 256-Pin TOFP | POFP | BGA |FineLine TOFP | POFP | BGA |FineLine (1) BGA (1) BGA M |i93) |- 101 E18 | P5 O |225 {47 88 Hig R7 194 |- - - - 226 |- - - - 195 |- - - - 227 | 46 89 H18 P7 196 |- - - - 228 |- - - - 197 |- 102 D20 | N5 229 | 45 90 H17 | 17 198 |- - - - 230 |- - - - 199 |- - - - 231 |- - - - 200 |- - - - 232 |- - - - 201 |37 103 Di9 | T4 233 |- 31 G2o L8 202 |- - - - 234 |- - - - 203 |- 104. |C20 | R4 235/44 92 Gig N7 204 |- - - - 236 |- - - - 205 |- - - - 237 |- - - - 206 |36 106 cig |P4 238 |- - Gis M7 207. |- - - - 239 |- - - - 208 = |35 108 Big |P3 240 |43 93 F20 L7 N |209 |42 95 Gi7 | Re P |241 [54 79 K20 Mg 210 |- - - - 242 |- - - - ati [- - - - 243 |- - - - 2120 |[- - - - 244 |- - - - 213 [41 96 a 245 |- 80 K19 Lg 214 [- - - - 246 |- - - - 215 |- - - - 247) |- - - - 216 |- - - - 248 |- - - - 217 |40 97 E20 _|N6 249 | 53 81 K17 R8 218 |- - - - 250 |- - - - 219 |39 98 F18 M6 251 |- 84 J18 T8 220 |- - - - 252 |- - - - 221 |- - - - 253 |- - - - 222 |- 99 Eig | R5 254 | 49 86 J17 NB 223 |- - - - 255 |- - - - 224 |38 100 FI7 | T5 256 | 48 87 H20 M8 Altera Corporation 649MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 32. EPM7512AE 1/0 Pin-Outs (Part 5 of 8) LAB | MC | 144-Pin |208-Pin|256-Pin| 256-Pin | LAB | MC |144-Pin| 208-Pin | 256-Pin | 256-Pin TOFP | POFP | BGA |FineLine TOFP | POFP | BGA |FineLine a BGA (1) BGA Q |257 [55 78 L20 Ng S |289 |66 62 P17 K14 258 |- - - - 290 |- - - - 259 |- - - - 291 |- - - - 260 |- - - - 292 |- - - - 261 |- 77 Lig T3 293 |67 61 Rig M12 262 |- - - - 294 |- - - - 263 |- - - - 295 |- - - - 264 |- - - - 296 |- - - - 265 |56 76 L18 R9 297 68 60 T20 N12 266 |- - - - 298 |- - - - 267 |- 73 Mig |L10 293 |69 59 Rig = |T12 268 |- - - - 300. |- - - - 269 |- - - - 301. |- - - - 270 | 60 71 M17 | M10 302. |- 58 T19 R12 271 |- - - - 303 |- - - - 272 | 61 70 N20 | N10 304 |70 57 T18 T13 R |273 |62 69 Nig | R10 T |305 |- 56 R17 P12 274 | - - - - 306 |- - - - 275 |63 68 Nig |T10 307. |- - - - 276 |- - - - 308 |- - - - 277 | - 67 Ni7 |M11 309. |- 55 U20 = |T14 278 |- - - - 310 |- - - - 279 | - - - - 311 |= - - - 280 |- - - - 312) |- - - - 281 |- 66 P20 N11 313 {71 54 Uig {P13 282 |- - - - 314. |- - - - 283 | 65 65 Pi9 | P11 315 |72 53 v20 R13 284 |- - - - 316 |- - - - 285 |- - - - 317. |- - - - 286 | - - P18 Ri 318 - 52 Weo Ri4 287 |- - - - 319 |- - - - 288 | - 64 R20 (| Ti 320. |74 49 wis | R15 650 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 32. EPM7512AE 1/0 Pin-Outs (Part 6 of 8) LAB | MC |144-Pin|208-Pin|256-Pin| 256-Pin | LAB | MC |144-Pin| 208-Pin | 256-Pin | 256-Pin TOFP | POFP | BGA |FineLine TOFP | POFP | BGA |FineLine (1) BGA (1) BGA U |s21 {75 48 Yig = |P15 Ww |353 | 82 35 wi4 = |Li6 322 |- - - - 354 |- - - - 323 |- - - - 355 |- - Y14 L13 324 |- - - - 356 |- - - - 325 |- 47 Yig | N15 357 (183 34 U13 L12 326 |- - - - 358 |- - - - 327 |- - - - 359 | - - - 328 |- - - - 360 |- - - - 329 |- 46 Wi7 |T16 361 | 84 33 v13 K12 330 |- - - - 362 |- - - - 331 - 45 Y17 R16 363 86 31 W13 K14 332 |- - - - 364 |- - - - 333 |- - - - 365 |- - - - 334 |77 44 Ui5 | P16 366 [87 30 (2) |Y13 K15 335 |- - - - 367 |- - - - 336 |78 43 vie | N14 368 | 88 29 U12 K16 Vv |337 |79 42 wie |Ni6 x [369 Jas2) |[- Vi2 (2) |J11 (2) 338 |- - - - 370 |- - - - 339 |80 40 vis [M14 371 |- 28 wiz |J12 340 |- - - - 372 |- - - - 341 |- 39 Yie |N13 373 |- 27 12 J13 342 |- - - - 374. |- - - - 343 |- - - - 375 |- - - - 344 |- - - - 376 |- - - - 345 =|81 38 W15 Mis 377 - 26 Vii Ji4 346 |- - - - 378 |- - - - 347) | - - U14 M13 379 - - U11 J15 348 |- - - - 380 |- - - - 349 |- - - - 381 |- - - - 350 |- 37 Yi5 | L14 382 |- 25 wit K13 351 |- - - - 383 |- - - - 352 |- 36 v14 Li5 384 90 24 Yi J16 Altera Corporation 651MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Table 32. EPM7512AE 1/0 Pin-Outs (Part 7 of 8) LAB | MC | 144-Pin |208-Pin|256-Pin| 256-Pin | LAB | MC |144-Pin| 208-Pin | 256-Pin | 256-Pin TOFP | POFP | BGA |FineLine TOFP | POFP | BGA |FineLine a BGA (1) BGA Y 7385 |91 22 Y10 H1i0 AA [417 - 10 V7 Fi4 386 |- - - - 418 |- - - - 387) |- 21 W10 H1i1 419 - 9 Y6 Fi5 388 | - - 420 |- - - - 389 |92 20 Vio | Ht2 421 |98 8 U7 F16 390 |- - - - 422 |- - - - 391 |- - - - 423 |- - - - 392 |- - - - 424 |- - - - 393 |- - Uio0 | H15 425 |- - we E12 394 |- - - - 426 |- - - - 395 |- 19 Y9 H16 427 |99 7 5 E13 396 |- - - - 428 |- - - - 397 |- - - - 429 |- - - - 398) |- 18 ws H14 430 100 6 V6 E14 399 |- - - - 431 |- - - - 400 |93 17 v9 H13 432 | 101 - W5 E16 Z 1401 - - US Gi2 BB | 433 - - V5 D16 402 |- - - - 434 - - - - 403 |- 16 8 G13 435 102 4 U6 C16 404 |[- - - - 436 |- - - - 405 94 15 W8 Gi4 437 - - Y4 B16 406 |- - - - 438 |- - - - 407 |- - - - 439 |- - - - 408 |- - - - 440 |- - - - 409 96 13 V8 G16 441 - 3 Ww4 A16 410 |- - - - 442 |- - - - 411 - 12 U8 Gil 443 103 2 3 D15 412 |- - - - 444 - - - - 4i3 [- - - - 445 |- - - - 414 |97 1 Y7 Fi2 446 1104 (2) |1 2 (2) 1D13 (2) 415 |- - - - 447 | - - - - 416 |- - W7 F13 448 1106 208 wa C15 652 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Table 32. EPM7512AE 1/0 Pin-Outs (Part 8 of 8) LAB | MC | 144-Pin | 208-Pin|256-Pin| 256-Pin | LAB MC | 144-Pin| 208-Pin | 256-Pin | 256-Pin TOFP | POFP | BGA |FineLine TOFP | POFP | BGA |FineLine (1) BGA {T) BGA ce {449 |- - Wi B15 FE |481 - 196 P3 D11 450 |- - - - 482 |- - - - 451 - - - - 483 - - - - 452 |- - - - 484 - - - - 453 |107 - V1 Al5 485 113 195 P2 C11 454 |- - - - A486 - = - - 455 |- - - - 487 |- - - - 456 - - - - 488 - - - - 457 |108 206 U2 B14 489 114 194 P1 All 458 - - - - 490 - - - - 459 |- 205 U1 Al4 491 116 193 N4 B11 460 |- - - - 492 |- - - - 461 - - - - 493 - - - - 462 |- 204 T3 B13 494 117 - N3 Fig 463 |- - - - 495 |- - - - 464 |109 203 R4 Al3 496 - - Ne E10 DD |465 |- 202 T2 C13 FF | 497 118 192 N1 Dio 466 |- - - - 498 |- - - - 467 |- - - - 499 |- - - - 468 |- - - - 500 |- - - - 469 |110 201 R3 Di2 501 - - M4 c10 470 |- - - - 502 | - - - - 471 |- - - - 503 |- - - - 472 |- - - - 504. |- - - - 473 111 199 T1 c12 505 119 190 M3 A1o 474 |- - - - 506 |- - - - 475 - 198 Re Ble 507 120 189 (2) |M2 J10 476 - - - - 508 - - - - 477 - - - - 509 - - - - 478 |112 197 P4 Al2 510 121 188 M1 F9 479 |- - - - 511 - - - - 480 |- - R1 E11 512 122 187 L3 Ag Altera Corporation 653MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Notes to tables: (1) (2) (3) The EPM7512AE device in the 208-pin POFP package supports vertical migration from the EPM7256E, EPM72568, and EPM?256A devices. The EPM7512AE device contains additional 1/O pins which are no connects on the EPM7256E, EPM72565, and EPM7256A devices. To support these additional 1/0 pins, the EPM7512AE device has two additional VCCIO (pins 105 and 207) and GNDIO (pins 51 and 158) pins that are no-connect pins on the EPM7256E, EPM72565, and EPM7256A devices. To achieve vertical migration between the EPM7256A and EPM7512AE devices, the no-connect pins 105 and 207 may be tied to VCCIO and pins 51 and 158 may be tied to GNDIO on the EPM7256A devices. On the EPM7256E and EPM7256S devices, these no-connect pins must not be tied to VCCIO or GNDIO. EPM7512AE devices have identical pin-outs. This pin may function as either a JTAG port ora user I/O pin. If the device is configured to use the JTAG ports for in-system programming, this pin is not available as a user I/O pin. The user I/O pin count includes dedicated input pins and all 1/0 pins. Figures 14 through 21 show the package pin-out diagrams for MAX 7O00A devices. Figure 14. 44-Pin PLE/TOFP Package Pin-Out Diagram Package outlines not drawn to scale. g 4 4 3G a Ce. Sf .e% Nea Saba ogog ouogy 5 ebb. eo b555, QSarrtadn Zeaa Qe<e@S2z2z22z5 22 pop 2222222528 Pin 34 6 54 3 2 1 44 4342 41 40 al VORTD I 30 lo KONTDY e ES 10 nel 33 fo VOATDO} = re} E EF fOTDO} LJ VO | 0 AERA ath Wo aN De Ra\ LE 1/0 GND 36 plo GND -> 10 25 voc vo WO F= veo WO EPM7032AE mp io EPM7032AE = VO nO VOATM 8} EPM7064A4E 3309 Ifo 1G 82 Pl VONTOK) WORTMS) EPM7064AE a I/O yoo 31 0 10 FS Orr ok) nC so GND veo bs 10 WO 29 110 10 E> GND VO - |'O 18 19 20 2422 23 24 25 2627 28 geogoaoavogggcag - - SS 222924235 Fini2 2ELeegeseeE Fin2s 44-Pin PLCC 44-Pin TQFP 654 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Figure 15. 84-Pin PLE Package Pin-Out Diagram Package outline not drawn to scale. 2 ges rc =z Biug 0. 55559 8 ao go SQIQOFECVLSsz2gRQIgYoQgS f reeurantronr gs geesRRERR vo [12 74 10 vocio 18 73 vo voto! Ey i4 72 1 ond vo 1s 7 Al vorco vo 16 By a 70 Ivo vo C17 sa vo vo C18 68 [I vo GND 13 a? Fo vo I] 20 66 ccI> vo Ep 21 6s Ovo vo Cee 64 Ovo voTMs I] 23 =p vo [24 EPM7128A 62 O vorrch vo (25 EPM7128AE sl FI vo vocio 26 60 vo vo 27 53 A sno vo [28 $6 1 vo vo 23 sf Ovo vo E30 56 Fo vo at 55 Al vo snp E]se S41 vo Baen beers PPP FF BR RB DODDDODODOODODOOODOUOOOODOo gegececegcesEoogsgegoogs oa 8 8G Bo TTS > o > > Figure 16. 100-Pin TQFP Package Pin-Out Diagram Package outline nof drawn to scale. Pint Pin 76 EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE Altera Corporation 655MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Figure 17. 100-Pin FineLine BGA Package Pin-Cut Diagram Package outline not drawn to scale. Al Balt Pad Corner \ Indicates \ slat} @ AP ogoooooo0cd0oo BFFOocOoOOooOoCooo Oo cer OOo 00 Cc Oooo 0 JN OTS RYA\ Drocooococoo Oo FFooooocooceo Fr ooooooco0o0 0 EPM7064AE es OCOO0COCOOC Oo EPM7128A EPMy128AE HH Oocoooccoooao EPM7256AE yyoooodondoo0odco KJ Oooo 0coeoo000 1 9 8 Ff 6 5&5 4 3 2 14 Figure 18. 144-Pin TQFP Package Pin-Out Diagram Package outline not drawn fo scale. Indicates focation of Pin? EPM71284 EPM7128AE EPM7256A EPM7256AE EPM7512AE 656 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Figure 19. 208-Pin POFP Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Fin | A JANOS RYA\ EPM7256A EPM7256AE EPM7512A4E ce Pin 53 Pin 105 Altera Corporation 657MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information Figure 20. 256-Pin BGA Package Pin-Out Diagram Package outline not drawn to scale. Af Balt Pad Gorner a Indicates Location of Ball Af ANTERAN EPM7512AE ax EB eccuuvtZz=r AL TAammoIoeSs eooo0000 eooooon ooo000 ooo0o00 ooo00o0 oooooad eo0o0000 oooo0oad ooooo5o oooo00 ooo0000 o0oo0000 eooodoa 000000 oooooad ooooo$n oooo0ooo0 ooo0000 o0oo0000 oooooo ooo000$0 90000000000000 aecoooacca00co00aco0d eooo0ocoe0o0o00g0g00 goaooao0ceoo0 000000 gooo0oo0oo0c0o0oo0o0000d gacoo0g00000coqe00 gHooaoo0dceooo00000 9eoo0o00on00000005 eooo0o0coo0ac00c00d eo000ce000g0g00 eocoo0oocoaoo0onodc00d 9o000000000006 aecooaceca0co00co0od goeooocoooo0o 0000 oeooo0o0conoa00dc00sd ecaoaooceo0oono000d goo0oo0oco0oo0o000a00d goo0oca0odgo00000 9o0000000000000 eooo0o000o0ago0000d ecoogcao0cao0o00c00d 658 201918171615 141312111098 7 65 432 1 Altera CorporationPreliminary Information MAX 7000A Programmable Logic Device Family Data Sheet Figure 21. 256-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. Indicates Location of pallAt | -@ /NDTS RMA EPM7 128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Altera Corporation odo pdwezazeroActauart meow se Al Yall Pad Comer |_- c00000000D0000000 ao00oo0o000000 00000 oocooo0oo0o000000 00nd ooocoo0oo00000 000000 ooo0oo0ooo0ooo0oo0oo0o000o0035 oo0o0coo0o0o000000 00006 oooo0oo00o0o00000 000 ooo0oo0oo0o0o0000000 000 ooo0oo0oo0o0oo0oo0o0o00o0o0o03o oocoo0oo0o00c00000 000 eooo0oo0oo0o0o0o0o0o0o00q0000 ooo0oo0oo0o0cogo0o00000 000 aeocoo0oo0o0000000 coo oocoooo0oo00co0o00000 005 ooo0oo0oo0oo0o0o0q0o0o00q0000 oooooo0oo0oo0oo00o0o00000 16 15 1413 1211 189 8 7 6 & 43 2 1 659