1
TM
March 1997
HD-15531
CMO S Ma nc he ster Enc od er - D ec od er
Features
• Support of MIL -STD- 1553
• Data Rate (15531B) . . . . . . . . . . . . . . . .2.5 Megabit/Sec
• Data Rate (15531). . . . . . . . . . . . . . . . .1.25 Megabit/Sec
• Variabl e Fram e Length to 32 Bits
• Sync Identification and Lock-In
• Separate Manchester II Encode, Decode
• Low Ope rating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
Description
The Intersil HD-15531 is a high performance CMOS device
intended to service the requirements of MIL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two sec-
tions, an Encoder and a Decoder. These sections operate
independently of each other, except for the ma ster reset and
word length functions. This circuit provides many of the
requirements of MIL-STD-1553. The Encoder produces the
sync pulse and the parity bit as well as the encoding of the
data bits. The Decoder recognizes t he sync pulse a nd identi-
fies it as well as decoding the data bits and checking parit y.
The HD-15531 also surpasses the requirements of MIL-
STD-1553 by allowing the word length to be programmable
(from 2 to 28 data bits). A frame consists of three bits for
sync fo llowed by t he data word (2 to 28 data bi ts) foll owed by
one bit of parity, thus, the frame length will vary from 6 to 32
bit periods. This chip also allows selection of either even or
odd parity for the Encoder and Decoder separately.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MIL-STD-1553 over both temperature and
voltage. For high speed applications th e 15531B wil l support
a 2.5 Megabit/sec data rate.
The HD-15531 can also be used in many party line digital
data communications applications, such as a local area net-
work or an env ironment al cont rol sys tem drive n from a si ngle
twisted pair of fi ber optic cab le throughout a buil ding.
PACKAGE TEMP. RANGE
(oC) 1.25MBIT
/SEC 2.5MBIT
/SEC PKG.
NO.
PDIP -40 to 85 - HD3-15531B-9 E40.6
CERDIP -40 to 85 HD1-15531-9 HD1-15531B-9 F40.6
-55 to 125 HD1-15531-8 HD1-15531B-8 F40.6
DESC
(CERDIP) -55 to 12 5 5962-
9054901MQA HD1-15531 F40.6
-55 to 125 5962-
9054902MQA HD1-15531B F40.6
FN2961.1
CA UTION: The se devices are s ensi tiv e to el ectrosta tic di schar ge; follow proper IC H andling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
2
Pinout
HD-15 531 (CERDIP, PDI P)
TOP VIEW
Block Diagrams
ENDODER
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
TAKE DATA’
VCC
VALID WORD
TAKE DATA
SERIAL DATA OUT
SYNCHR DATA
SYNCHR DATA SEL
SYNCHR CLK
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLK
SYNCHR CLK SEL
DECODER CLK
TRANSITION SEL
NC
COMMAND SYNC
DECODER PARITY SEL
DECODER RESET
COUNT C0
33
34
35
36
37
38
39
40
32
31
30
29
24
25
26
27
28
21
22
23
COUNT C1
DATA SYNC
ENCODER CLK
COUNT C4
NC
ENCODER SHIFT CLK
SEND CLK IN
SEND DATA
ENCODER PARITY SEL
SYNC SEL
ENCODER ENABLE
SERIAL DATA IN
COUNT C2
MASTER RESET
GND
COUNT C3
÷ 6 OUT
BIPOLAR ONE OUT
BIPOLAR ZERO OUT
OUTPUT INHIBIT
÷ 2
÷ 6
VCC
25
27
32
BIPOLAR
ONE OUT
BIPOLAR
ZERO OU T
SYNC
SELECT
ENCODER
ENABLE
ENCODER
SHIFT
CLK
SEND
DATA SERIAL
DATA IN
34 28 29 31
ENCODER
CLK
37
GND
MASTER RESET
SEND CLK IN
21
22
33
24 ÷ 6 OUT
1
26
OUTPUT
INHIBIT
30
CHARACTER
BIT
COUNTER
ENCODER
PARITY
SELECT
20 40 23 36 39
C0C1C2C3C4
FORMER
HD-15531
3
DECODER
Pin Descr iption
PIN
NUMBER TYPE NAME SECTION DESCRIPTION
1V
CC Bot h Posi tive su pp ly pin. A 0.1µF decoupling capacitor from VCC (pin 1) to GROUND
(pin 21) is recommended.
2 O VALID WORD Decoder Output high indicates receipt of a valid word, (valid parity and no Manchester
errors).
3 O TAKE DATA ’ Dec oder A co nti nuous , fr ee ru nnin g si gnal p rov ided for host ti ming or data hand ling . Whe n
data i s pr esent on the bu s, this signal will b e synchronized to the incoming dat a
and will be identical to TAKE DATA.
4 O T AKE DATA Dec od er Outpu t is hi gh du rin g rec ei pt of d at a afte r id ent i f icat io n of a val id syn c pu lse an d
t wo vali d Ma nc he ster bi ts.
5 O SERIAL DATA OUT Decoder Delivers received data in correct NRZ format.
6 I SYNCHRONOUS
DATA Decoder Input presents Manchester data directly to character identification logic.
SYNCHRONOUS DATA SELECT must be held high to use this input. If not
used, this pin must be held hi gh.
7 I SYNCHRONOUS
DATA SELECT Decoder In high state allows the synchronous data to enter the character identification
logic. Tie this input low for asynchronous data.
8 I SYNCHRONOUS
CLOCK Decoder Input provide s externally synchroniz ed clock to the decoder, for use when re-
ceiv ing synchronous data. This input must be ti ed high when not in use.
9 I D EC ODE R C LO CK Dec od er Inpu t dri ves t he tra ns iti on fi n der, a nd t he syn ch ron iz er whi ch i n tur n supp li es t he
clock to the balance of the decoder. Input a frequency equal to 12X the data rate.
10 I SYNCHRONOUS
CLOCK SELCT Decoder In h igh state directs the SYNCHRONOUS CLOCK to control the decoder char-
acter identification logic. A low state selects th e DECODER CL OCK.
11 I BIPOLAR ZERO IN Decoder A high input should be applied when the bus is in its negative state. This pin must
be held high when the unipolar input is used.
12 I BIPOL A R ON E IN Dec od er A hi gh inp ut s ho ul d be ap pl ie d whe n t he bus i s i n i ts po si t iv e s tat e. Thi s pi n mus t
he held low when the unipolar input is used.
13 I UNIPOLAR DATA IN Decod er With pin 11 high and pin 12 lo w, this pi n ent ers unipolar data into the tran siti on
finder circuit. If not us ed th is input must be hel d low.
BIPOLAR
ONE IN
BIPOLAR
DECODER
MASTER
13
12
11
9
15 SYNCHRONIZER
8
10
22
DECODER
SYNCHRONOUS
SYNCHRONOUS DECODER
VALID WORD
SERIAL
TAKE DATA
COMMAND SYNC
DATA SYNC
4
17
5
2
16
19
DECODER
RESET
14
3TAKE DATA’
PARITY
20 40 23 36 39
BIT
COUNTER
CLOCK
7 8
SYNCHRONOUS SYNCHRONOUS
C0C1C2C3C4
TRANSITION
FINDER DATA
SELECT
GATE
PARITY
CHARACTER
IDENTIFIER
BIT
UNIPOLAR
DATA IN
ONE IN
CLK
CLK SELECT
CLK
CLK SELECT
RESET
DATA OUT
SELECT
SHIFT CLK
CHECK
RATE
CLK
SELECT
DATA
DATADATA SELECT
HD-15531
4
14 O DECODER SHIFT
CLOCK Decoder Output which delivers a f requ ency (DEC O DER CLOCK + 1 2), synchronous by
the recovered serial data stream.
15 I TRANSITION SE-
LECT Decoder A high input to this pin causes th e transition find er to synchronize on every tran-
sition of input data. A low input causes the transition finder to synchronize only
on mid-bit transitions.
16 NC Blank Not connected.
17 O COM MAND SYNC De co der Ou t p ut of a high from t hi s pin oc cu r s during ou tp ut of de co de d data whi ch wa s
preced ed by a C ommand (or Status) synchronizing character.
18 I DECODER PARITY
SELECT Decoder An input for parity sense, calling for even parity with input high and odd parity
with input low.
19 I DEC ODE R RE S ET Decod er A hig h in pu t to thi s p in duri ng a risi n g ed ge of DE COD ER S HI F T CLOCK r eset s
the deco der bit co unti ng logic to a condition ready for a new word.
20 I COUN T C 0 Bot h One o f fiv e b in ary inp ut s whi ch est a blis h t he to tal b it co unt t o b e en code d or de -
coded.
21 GROUND Both Supply pin .
22 I MASTER RESET Both A high on th is pin clear s 2:1 count ers in both encoder and decoder, and resets
the ÷ 6 c ir cu it.
23 I COUNT C2 Both See pin 20.
24 O ÷ 6 OUT Encoder Output from 6:1 divider which is driven by the ENCODER CLOCK.
25 O BIPOLAR ZERO
OUT Encoder An active low output designed to drive the zero or negative sense of a bipolar
line driver.
26 I OUTPUT INHIBIT Encod er A low on this pin forces pin 25 and 27 high, the inactive sta tes.
27 O BIPOLAR ONE OUT Enc od er An ac tive lo w o ut p ut de si gn ed to dr i ve the on e o r pos it i ve s en se o f a bi po la r li ne
driver.
28 I SERIAL DATA IN Encoder Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLO CK.
29 I ENCODER ENABLE Encod er A high on t his pin initiat es the encode cycle. (Subject to the preceding cycle be-
ing c omplete).
30 I SYNC SELECT Encoder Actuate s a Command sync for an input high and Data sync for an inp ut lo w.
31 I ENCODER PARITY
SELECT Encoder Sets transmit parity odd for a high input, even for a low input.
32 O SE ND DATA Encod er Is an active high output which e nables the exter nal source of serial da ta.
33 I SEN D CL OC K I N E ncod er Cl o ck inpu t at a f r eq uency e qu al to th e da ta r ate X 2, u su al ly d rive n by ÷ 6 ou tp ut.
34 O ENCODER SHIFT
CLOCK Encoder Output for shifting data into the Encoder. The Encoder samples SDI pin-28 on
the low-to-high transition of ESC.
35 NC Blank Not connected.
36 I COUNT C3 Both See pin 20.
37 I ENCODER CLOCK Enc oder In put to the 6:1 di vider, a frequen cy equal to 12 times the data rate is usu ally
in put here.
38 O D ATA SY N C Deco der Outp ut of a high fro m thi s pin oc cu r s during ou tp ut of de co de d data whi ch wa s
preceded by a data synchronizing character.
39 I COUNT C4 Both See pin 20.
40 I COUNT C1 Both See pill 20.
Pin Descr iption (Continued)
PIN
NUMBER TYPE NAME SECTION DESCRIPTION
HD-15531
5
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by divid-
ing the DECODER CLOCK. The frame length is set by pro-
gramming the COUNT inputs. Parity is selected by
programming ENCODER PARITY SELECT high for odd par-
ity or low f o r ev en par it y .
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK .
This cycle lasts for one word length or K + 4 ENCODER
SHIFT CLOCK periods, where K is the number of bits to be
sent. At the next low-to-high transition of the ENCODER
SHIFT CLOCK, a high SYNC SELECT input actuates a
Command sync or a low will produce a Data sync for the
word . When the Encoder is ready to accept data, the
SEND DATA output will go high for K ENCODER SHIFT
CLOCK periods . During these K periods the data should
be clocked into the SERIAL DATA input with every high-to-
low transition of the ENCODER SHIFT CLOCK - so it
can be sampled on the low-to-high transition. After the sync
and Manchester II encoded data are transmitted through the
BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder
adds on an additional bit with the parity for that word . If
ENCODER ENABLE is held high continuously, consecutive
words will be encoded without an interframe gap.
ENCODER ENABLE must go low by time (as shown) to
prevent a consecutive word from being en coded. At any time
a low on OUTPUT INHIBIT input will force both bipolar out-
puts to a high state but will not affect the Encoder in any
other way.
To abort the Encoder transmission, a positive pulse must be
applied at MASTER RESET. Any time after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal cou nters and initi alizes the Encoder for a new word.
Decoder Operation
To operate the Decoder asynchronously requires a single
clock with a frequency of 12 times the desired data rate
applied at the DECODER CLOCK input. To operate the
Decoder synchronously requires a SYNCHRONOUS
CLOCK at a frequency 2 times the data rate which is syn-
chronized with the data at every high-to-low transition
applied to the SYNCHRONOUS CLK input. The Manchester
II coded data can be presented to the Decoder asynchro-
nously in one of two ways. The BIPOLAR ONE and
BIPOLAR ZERO inputs will accept data from a comparator
sensed t ransformer co upled bus as specif ied in Milit ary Spec
1553. The UNIPOLAR DATA input can only accept nonin-
verted Manchester II coded data. (e.g., from BIPOLAR ONE
OUT on an Encoder through an inverter to Unipolar Data
Input).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized , the type of sync is indicated by a high
level at either COMMAND SYNC or DATA SYNC output. If
the sync character was a command sync the COMMAND
SYNC output will go high and remain high for K SHIFT
CLOCK periods , where K is the number of bits to be
received. If the sync character was a data sync, the DATA
SYNC output will go high. The TAKE DATA output will go
high and remain high - while the Decoder is transmit-
1
2
4
3 4
5
5
FIGURE 1. ENCODER
SEND CLOCK
BIT K-1 BIT K-3 BIT K-4 BIT K-5 BIT 4BIT K-2MSB BIT 3 BIT 2 BIT 1
PARITYBIT 1BIT 2BIT 3BIT 4
BIT 4 BIT 3 BIT 2 BIT 1 PARITY
1ST HALF 2ND HALF MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4
SYNC SYNC MSB BIT K-1
4 5321
VALID
TIMING 0 1 2 3 4 5 6 7 N-3 N-2 N-1 NN-4
ENCODER
SHIFT CLOCK
ENCODER
ENABLE
SYNC
SELECT
SEND
DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
DON’T CARE
DON’T CARE
BIT K-2 BIT K-3 BIT K-4
1
2
3
2 3
HD-15531
6
ting the decoded data through SERIAL DATA OUT. The
decoded data available at SERIAL DATA OUT is in NRZ
format. The DECODER SHIFT CLOCK is provided so that
the decoded bits can get shifted into an external register on
every low-to-high transition of this clock - . Note that
DECODER SHIFT CLOCK may adjust its phase up until the
ti me that TAKE DATA goes hi gh.
After all K decoded bits have been transmitted the data i s
checked for parity. A high input on DECODER PARITY
SELECT will set the Decoder to check for even parity or a
low input will set the Decoder to check for odd parity. A high
on VALID WORD output indicates a successful reception
of a word without any Manchester or parity errors. At this
time the Decoder is looking for a new sync character to start
another output sequence. VALID W ORD will go low approx-
imately K + 4 DECODER SHIFT CLOCK periods after it
goes high, if not reset low sooner by a valid sync and two
valid Manche ster bits as shown .
At any time in the above sequence a high input on
DECODER RESET during a low-to-high transition of
DECODER SHIFT CLOCK will abort transmission and ini-
tialize the Decoder to star t lo oking for a new sync character .
2 3
3
4
1
SERIAL
1 S T HALF
TIMING
SYNCHRONOUS
CLOCK
DECODER
SHIFT
CLOCK
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
TAKE DATA
2ND HALF
SYNC SYNC
MSB
MSB
BITK-1
BITK-1
BITK-2
BITK-2
BITK-3
BITK-3
BITK-5
BITK-4 BITK-5
BITK-4
012345678 N-3N-2N-1N
BIT 3 BIT 2 PARITYBIT 1
BIT 2BI T 3 BIT 1 PARITY
BITK-1
VALID WORD
DATA SYNC
COMMAND
MSB BITK-2 BITK-3 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
3 421
(MAY BE HIGH FROM PREVIOUS RECEPTION)
UNDEFINED
DATA OUT
SYNC
FIGURE 2. DECODER
HD-15531
7
Frame Counter
DATA BITS FRAME LENGTH
(BIT PERIODS)
PIN WORD
C4C3C2C1C0
26LLHLH
37LLHHL
4 8 LLHHH
5 9 LHLLL
610LHLLH
711LHLHL
812LHLHH
913LHHLL
10 14 L H H L H
11 15 L H H H L
12 16 LHHHH
13 17 H L L L L
14 18 H L L L H
15 19 H L L H L
16 20 H L L H H
17 21 H L H L L
18 22 H L H L H
19 23 H L H H L
20 24 H L H H H
21 25 H H L L L
22 26 H H L L H
23 27 H H L H L
24 28 H H L H H
25 29 H H H L L
26 30 H H H L H
27 31 H H H H L
28 32 HHHHH
NOTE:
1. Th e ab ov e tabl e de mo nstr a tes al l po ssi b le comb in at ion s of frame len gt hs ra ng ing f r om 6 to 32 bi t s. The pi n wor d descr i be d her e is com-
mon to both the Encoder and Decoder.
HD-15531
8
Typical Timing Diagrams for a Manchester Encoded UART
VCC
SH/LD SI
7416574165
PARALLEL IN
OHCK SH/LD CK
PARALLEL OUT
MASTER
RESET
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
40
39
38
37
36
35
34
33
32
31
30
29
21
22
23
24
25
26
27
28
COUNT C0
DECODER
PARITY SELECT
COMMAND
SYNC
TRANSITION
SELECT
UNIPOLAR
DATA IN
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
SYN C CLOCK
SELECT
DECODER
CLOCK
SYNC
CLOCK
SYNC DATA
SELECT
COUNT C4
COUNT C1
COUNT C3
COUNT C2
BIPOLAR
ZERO OUT
INHIBIT
OUTPUT
BIPOLAR
ONE OUT
ENCODER
ENABLE
SYNC
SELECT
ENCODER
PARITY SEL.
NC
SI
NC
AB CKH AB CK
7416474164
OH
DATA SYNC
SYNC DATA
TAKE DATA
VALID WORD
FIGURE 3. HOW TO MAKE OUR MTU LOOK LIKE A MANCHESTER ENCODED UART
VALID
ENCODER ENABLE
SYNC SELECT
PAR ALLEL IN
BIPOLAR ONE OUT
BIPOLAR ZERO OUT
VALID
LSB
P
SYNC MSB PARITY
P
FIGURE 4. ENCODER TIMING
HD-15531
9
MIL-STD-1553
The 1553 Standard defines a time division multiplexed data
bus for application within aircraft. The bus is defined to be
bipolar, and encoded in a Manchester II format, so no DC
comp onent appear s on the bus. Thi s a llows t ransfor mer cou-
pling and excellent isolation among systems and their envi-
ronment.
The HD-15531 supports the full bipolar configuration,
assuming a bus driver configuration similar to that in
Figure 1. Bipolar inputs from the bus, like Figure 2, are also
accommodated.
The signaling format in MIL-STD-1553 is specified on the
assumption that the network of 32 or fewer terminals are
controlled by a central control unit by means of Command-
Wor ds, and Data. Terminals respond with Stat us Wo rds, and
Data. Each word is preceded by a synchronizing pulse, and
followed by parity bit, occupying a total of 20µs. The word
format s are shown in Figure 4. The sp ecial abbreviat ions are
as follows:
P P arity, which is defined to be odd, taken acr oss all
17 bits.
R/T Rec eive on l ogical zero, tra nsm it on ONE.
ME Message Error if logical 1.
TF Terminal Flag, if set, calls for controller to request
self-test data.
BIPOLAR ONE IN
BIPOLAR ZERO IN
LSB
P
SYNC MSB PARITY
P
COMMAND SYNC
VALID WORD
PARALLEL OUT VALID VALID
FROM PREV IOUS
RECEPTION
FIGURE 5. DECODER TIMING
FIGURE 6. SIMPLIFIED MIL-STD-1553 DRIV E R FIGURE 7. SIMPLIFIED MIL-STD-1553 RECEIVER
“0”
“1”
BUS
+
-
+
-
“1”
“0”
“1” R EF
“0” R EF
HD-15531
10
FIGURE 8. MIL-STD-1553 CHARACTER FORMATS
FIGURE 9. M IL-STD-1553 WORD F ORMATS
NOTE:
1. This page is a summary of MIL-STD-1553 and is no t in tended to des crib e the operation of the HD-15531.
BIT
PERIOD BIT
PERIOD BIT
PERIOD
LOGICAL ONE DATA
LOGICAL ZERO DA TA
COMMAND
SYNC
DATA
SYNC
TERMINAL
SYNC
0 1 2 3 4 5 6 7 8 9 10111213141516171819
COMMAND WORD (FROM CONTRO LLER TO TERMINAL)
DATA WORD (SENT EITHER DIRECTION)
STATUS WORD (FROM TERMINAL TO CONTROLLER)
515 51
P
ADDRESS SUB ADDRESS
/MODE DATA WORD
COUNT
SYNC
R/T
DATA WORD
1
P
51 9 11
TERMINAL
ADDRESS CODE FOR FAILURE MODES PSYNC TF
16
HD-15531
11
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clas s 1
Ope rat i ng Condit ions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range (TA)
HD-15531-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
HD-15531-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Encoder/Decoder Clo ck Rise Time (TECR, TDCR). . . . . . .8ns Ma x
Encoder/Decoder Clock Fall Time (TECF, TDCF) . . . . . . . .8ns Max
Thermal Resistance (Typical) θJA θJC
CERDIP Package . . . . . . . . . . . . . . . . . . 35oC/W 9oC/W
PDIP Pack age. . . . . . . . . . . . . . . . . . . . . 50oC/W N/A
Storage Temperature Range . . . . . . . . . . . . . . . . .-65oC to +150oC
Maximu m Junction Temperat ure
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates
Sync. Transition Span (TD2). . . . . . . . . . . 18 TDC Typical, (Note 1)
Short Data Transition Span (TD4). . . . . . . . 6 TDC Typical, (Note 1)
Long Data Transition Span (TD5) . . . . . . . 12 TDC Typical, (Note 1)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this spec ification is not implied.
DC Electrical Specifications VCC = 5.0V ±10%, TA = -40oC to +85Co (HD-15531-9)
TA = -55oC to +125Co (HD-15531-8)
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS
In put LOW Voltag e VIL VCC = 4.5V and 5.5V - 0.2 VCC V
Inpu t HIGH Voltage VIH VCC = 4.5V and 5.5V 0.7 VCC -V
In p ut LOW Clock Voltage VILC VCC = 4.5V and 5.5V - GND +0.5 V
In p ut HIGH Clo ck Vo ltage VIHC VCC = 4.5V and 5.5V VCC -0.5 - V
Ou tput LOW Voltage VOL IOL = +1.8mA, VCC = 4.5V (Note 2) - 0.4 V
Output HIGH Voltage VOH IOH = -3.0m A, V CC = 4.5V (Note 2) 2.4 - V
Input L eakage Current IIVI = VCC or GND, VCC = 5.5V -1 .0 +1.0 µA
Standby Supply Current ICCSB VIN = VCC = 5.5V,
Output s Ope n -2mA
Operating Power Supply Curre nt ICCOP VIN = VCC = 5.5V, f = 15MHz,
Output s Ope n -10mA
Functi onal Test FT(Not e 3) - - -
NOTES:
1. TDC = Decoder clock period = 1/ FDC.
2. Interchanging of force and sense conditions is permitted.
3. Tested as follows: f = 15MHz, VIH = 70% VCC, VIL = 20 % VCC, CL= 50pF, VOH ≥ VCC/2 and VOL ≤ VCC/2.
Capacitance TA = +25oC, Freq uency = 1MHz
SYMBOL PARAMETER TYP UNITS TEST CONDI TIONS
CIN I np ut C ap ac itan ce 25 pF All me as u rem ents are r efe renc ed to dev ic e G N D
COUT Output Capacitance 25 pF
HD-15531
12
AC Electrical Specifications VCC = 5V ±10%, TA = -40 oC to +85oC (HD-15530-9)
TA = -55oC to +125oC (HD-15530-8)
SYMBOL PARAMETER
HD-15531 HD-15531B
UNITS TEST CONDITIONS (NOTE 2)MIN MAX MIN MAX
ENCODER TIMING
F EC En c od er Clo ck Fr eq ue nc y - 15 - 30 MHz VCC = 4.5V and 5.5V, CL = 50pF
FESC Send Clock Frequency - 2.5 - 5.0 MHz VCC = 4.5V and 5.5V, CL = 50pF
FED Encoder Data Rate - 1.25 - 2.5 MHz VCC = 4.5V and 5.5V, CL = 50 pF
TMR Master Reset Pulse Width 150 - 150 - ns VCC = 4.5V and 5.5V, CL = 50pF
TE1 Shift Clock Delay - 125 - 80 ns VCC = 4.5V and 5.5V, CL = 50pF
T E2 Se r i al Dat a Setu p 75 - 50 - n s VCC = 4.5V and 5.5V, CL = 50pF
TE3 Serial Data Hold 75 - 50 - ns VCC = 4.5V and 5.5V, CL = 50pF
TE4 Enabl e Setup 90 - 90 - ns VCC = 4.5V and 5.5V, CL = 50pF
TE5 Enabl e Pul se Width 100 - 100 - ns VCC = 4.5V and 5.5V, CL = 50pF
TE6 Sync Setup 55 - 55 - ns VCC = 4.5V and 5.5V, CL = 50pF
TE7 Sync Pulse Width 150 - 150 - ns VCC = 4.5V and 5.5V, CL = 50pF
TE8 Send Data Delay 0 50 0 50 ns VCC = 4.5V and 5.5V, CL = 50pF
TE9 Bipol ar Output Delay - 130 - 130 ns VCC = 4.5V and 5.5V, CL = 50pF
TE10 Enab le Hold 10 - 10 - ns VCC = 4.5V and 5.5V, CL = 50pF
TE 11 S y n c Hold 95 - 95 - ns VCC = 4.5V and 5.5V, CL = 50pF
DECODER TIMING
FDC Decoder Clock Frequency - 15 - 30 MHz VCC = 4.5V and 5.5V, CL = 50pF
FDS Decoder Sync Clock - 2.5 - 5.0 MHz VCC = 4.5V and 5.5V, CL = 50pF
FDD Decoder Data Rate - 1.25 - 2.5 MHz VCC = 4.5V and 5.5V, CL = 50pF
TD R Decoder Reset Pulse Width 150 - 1 50 - ns VCC = 4.5V and 5.5V, CL = 50pF
TDRS Decoder Reset Setup Time 75 - 75 - ns VCC = 4.5V and 5.5V, CL = 50pF
TDRH Decoder Rese t Ho ld Time 10 - 10 - ns VCC = 4.5V and 5.5V, CL = 50pF
TMR Master Reset Pulse 150 - 150 - ns VCC = 4.5V and 5.5V, CL = 50pF
TD1 Bipolar Dat a Pul se Widt h TDC + 10
(N ote 1) - TDC + 10
(N ote 1) -nsV
CC = 4.5V and 5.5V, CL = 50 pF
TD3 One Zer o Overlap - TDC - 10
(N ote 1) - TDC - 10
(N ote 1) ns VCC = 4.5V and 5.5V, CL = 50pF
TD6 Sy nc Delay (ON) -20 110 -2 0 110 n s VCC = 4.5V and 5.5V, CL = 50pF
TD7 T ake Data Delay (ON) 0 110 0 110 n s VCC = 4.5V and 5.5V, CL = 50pF
TD8 Serial Data Out Delay - 80 - 80 ns VCC = 4.5V and 5.5V, CL = 50pF
TD9 Sync Delay (OFF) 0 110 0 110 ns VCC = 4.5V and 5.5V, CL = 50pF
TD10 Take Data Delay (OFF) 0 110 0 110 ns VCC = 4.5V and 5.5V, CL = 50pF
TD1 1 Va li d Wo r d D ela y 0 110 0 11 0 n s VCC = 4.5V and 5.5V, CL = 50pF
TD12 Sync Clock to Shift C lock
Delay -75-75nsV
CC = 4.5V and 5.5V, CL = 50 pF
TD13 Syn c Data Setu p 75 - 75 - n s VCC = 4.5V and 5.5V, CL = 50pF
NOTES:
1. TDC = Decoder clock period = 1/FDC.
2. AC Testing as follows: Input levels: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing Reference
levels: VCC/2; Output load: CL = 50pF.
HD-15531
13
Timing Waveforms
FIGURE 10. ENCODER TIMING
SEND CLOCK
TE1
TE2 TE3
VALID
ENCODER SHIFT CLOCK
SERIAL DATA IN
SEND CLOCK
ENCODER SHIFT CLOCK
ENCODER ENABLE
ENCODER SHIFT CLOCK
SYNC SELECT
SEND DATA
SEND CLOCK
BIPOLAR ONE OUT OR
BIPOLAR ZERO OUT
VALID
TE1 TE10
TE4 TE11
TE5 TE6
VALID
TE7
TE8
TE9
HD-15531
14
FIGURE 11. DECODER TIMING
Timing Waveforms (Continue d)
DATA SYNC
BIT PERIOD BIT PERIOD BIT PERIOD
TD2
COMMAND SYNC TD2
TD3 TD3
TD2
TD4
ONEONE ZERO
TD1
TD1
TD1
TD3 TD3
TD1
TD1
TD1
TD3 TD3 TD3 TD3
TD1
TD4 TD5
TD5
TD2
TD2
COMMAND SYNC
TD2 TD2
TD4 TD5 TD5 TD4 TD4
ZERO ONE ONEONE
DATA SYNC
BOI
BZI
BOI
BZI
BOI
BZI
UI
UI
UI
TD3
NOTE: UNIPOLAR IN = 0, FOR NEXT DIAGRAMS.
NOTE: BIPOLAR ONE IN = 0, BIPOLAR ZERO IN = 1, FOR NEXT DIAGRAMS.
TD2
TD2
HD-15531
15
FIGURE 12. DECODER TIMINGS
Timing Waveforms (Continue d)
TAKE DATA
TD6
TD7
TD8
DATA BIT
TD9
TD10
TD10
TD11
TDRS
TDR
TDRH
DECODER SHIFT CLOCK
COMMAND/DATA SYNC
SERIAL DATA OUT
DECODER SHIFT CLOCK
COMMAND/DATA SYNC
TAKE DATA
VALID WORD
DECODER SHIFT CLOCK
DECODER RESET
DECODER SHIFT CLOCK
TD12
TD13 TD13 TD13 TD13
SYNCHRONOUS
DECODER SHIFT
SYNCHRONOUS INPUT (W ITH EXTERNAL BIT SYNCHRONIZATION)
CLOCK IN
CLOCK
SYNCHRONOUS
CLOCK IN
SYNCHRONOUS
DATA IN MANCHESTER
PHASES
HD-15531
16
All Intersil U.S. pro ducts are manufactured, assembled and tested uti lizin g ISO9000 quali ty systems.
Intersil Corporati on’s quali ty certifi cations can be viewed at www.intersil.com/desi gn/quali ty
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsi diaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Test Lo ad Circuit
NOTE:
1. Includes st ray and jig capacitance.
AC Testing Input, Output Waveform
NOTE:
1. AC Testing: All input signals must switch between VIL and VIH,
input rise and fall times are driven at 1ns per volt .
DUT
CL (NOTE 1)
FIGURE 13.
INPUT
50% 50%
OUTPUT
VOL
VOH
VIH
VIL
FIGURE 14.
HD-15531
