Am4055/5055 * Am4056/5056 - Am4057/5057 Quad 128-Bit, Dual 256-Bit and Single 512-Bit Static Shift Registers Distinctive Characteristics @ Operation guaranteed from DC to 1.5MHz Internal recirculate @ 100% reliability assurance testing in compliance with @ Single TTL compatible clock MIL-STD-883 FUNCTIONAL DESCRIPTION LOGIC SYMBOLS These devices are a family of static P-channel MOS shift 1 registers in three configurations. The Am4055/5055 is a | quad 128-bit register; the Am4056/5056 is a dual 256-bit 2ina Rc outa R 14 register; and the Am4057/5057 is a single 512-bit register. 13]INB Am4055/5055 ours }- 4 . All three devices include on chip recirculate. The registers iw IND snIeTREaisTeR = OuTC 12 vss a oe are all clocked by a single low-level clock input. Be- 9 cr OUT DF-~ 7 Veo . Pin 10 cause the registers are static, the clock may be stopped indefinitely in the LOW state without loss of data. Each of the registers has a single data input; data on the input is 73 written into the register on the HIGH-to-LOW clock edge. 1]INa Amd066/5056 OUTAF 2 A single recirculate control (RC) on each chip determines I~] ING DUAL 28681 | Vsg = Pin S whether the registers on that chip are to write data in from 6)cP ouTsp 4 Vpp= Ping the data inputs or recirculate the data appearing on the Yaa = Pin? output. If RC is LOW, new data is written in; if RC is HIGH 1 then the data on the output will be written back into the register input on the next clock pulse. 2IT Re sizeitsuierncister OUTP 3 Vgg = Pin 4 5 lcr Vop = Ping Vgg = Ping MOS-450 LOGIC BLOCK DIAGRAM (One Register Shown) RC D. nBIT STATIC 'N SHIFT REGISTER ouT our cP INPUT CLOCK Am4055/5055 n= 128 Am4056/5056 n= 256 Aeoetess Am4057/5057_ n= 512 MOS-451 ORDERING INFORMATION CONNECTION DIAGRAMS Am4055/5055 Am4056/5056 Package Temperature Order Type Range Number 16-Pin Molded DIP 0C to +70C MM5055N 16-Pin Hermetic DIP 0C to +70C MM5055D 16-Pin Hermetic DIP 55Cto+125C = MM4055D TO-100 Can 0C to +70C MMS5056H TO-100 Can ~55C to +125C = MM4056H Am4057/5057 8-Pin Molded DIP OC to +70C MM5057N mea 8-Pin Hermetic DIP 0C to +70C MM5057D cd 81] Yop 8-Pin Hermetic DIP 65C to +125C + =MM4057D wEfz 7 [nc out (]3 6} Yac VgsL] 4 5L1ce MOS-452 5-53 Am40/5055 Am40/5056 Am40/5057 MAXIMUM RATINGS (Above which the useful life may be impaired) Storage Temperature Temperature (Ambient) Under Bias Vop Supply Voltage Vag Supply Voltage 65C to +160C 55C to +125C Vss 10V to Vgg +0.3V Vsg 20V to Vsg +0.3V DC Input Voltage OPERATING RANGE Part Number Ambient Temperature Vss Vop VGG Am4055 Am4056 55C to +125C 5.0V +5% Am4057 Ov 12V 25% AmS055 AmS056 OC to +70C 5.OV +5% AmS057 ov 12V +5% ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted) Vsg 20V to Ves +0.3V Typ. Parameters Description Test Conditions Min. (Note 1) Max. Units Vou Output HIGH Voltage lon = 0.5mA 24 Volts VoL Output LOW Voltage loz = 1.6mA 0.4 Volts i i 4055/6/7 | Vss1.0 Vgst0.3 Vin Input HIGH Level Guaranteed input logical HIGH voltage 8S Ss Volts for all inputs 5055/6/7 | Vgs1.5 Vggt0.3 Guaranteed input logical LOW voltage Vsgsg18! 4. 1 Vit Input LOW Level for all inputs ss18.5 Vgs-4.2 Valts Vin = 10,0V, all other pins GND, Tie Input Leakage Current Ta = 28C 0.01 0.5 uA Ta = 25C, f < 2.2MHz 15.0 20.0 \pp VpDp Power Supply Current A tepwH = 160 ns f < 10KHz 13.0 18.0 \ Vac P Supply C : Data = 1010... f < 1.6MH2 10.5 15.5 mA owe urren GG GG er SUPPIY output open f < 2,.2MH2 13.0 19.0 f < 10KHz 65 9.0 Note: 1, Typical Limits are at Vss = 5,0V, Vea =-12V, 25C ambient. SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted) Am4055/6/7 Am5055/6/7 Parameters Description Test Conditions Min. Typ. Max. Min. Typ. Max. Units f Clock Frequency 0 1.0 9 1.5 MHz tgowH Clock HIGH Time 0.4 1.0 0.23 100 us topwl Clock LOW Time 0.4 oo 0.3 co us tr, tt Clock Rise and Fall Times 200 200 ns ts Set-up Time, D or RC Inputs (see definitions} ty = te < 10ns 260 410 ns th Hold Time, D or RC Inputs (see definitions) ty = tp < 10ns 120 40 ns tod Delay, Clock to Output LOW or HIGH Ry = 4k, CL = 10pF 350 700 250 345 ns Cin Capacitance, Data and RC Inputs (Note 2) = 1MHz, Vin =Vss 4 7 4 7 pF Cy Capacitance, Clock Input (Note 2) f= 1MHz, Vin=Vss 14 14 pF Notes: 2. This parameter is periodically sampled but not 100% tested. It is guaranteed by design. 3. At any temperature, tog min. is always much greater than t,{D) max. 5-54 Am40/5055 Am40/5056 Am40/5057 TIMING DIAGRAM bay am i" . v 90% 90% roa 10% 10% 90% ov owt ov te MAX. a] amax * D wy ROR - D . Vin Weg RY KY NA YY " ty MAX, oe |p th MAX ty MAX. eo] 1;MAX. " r LOR vm ne a 1 ORR Oe ov ov an tod MAX sv +5 over > ws wx ov ov WRITING NEW DATA RECIRCULATING MOS-453 KEY TO TIMING DIAGRAM WAVEFORM INPUTS OUTPUTS MUST BE WILL BE STEADY STEADY May CHANGE SL BE FROMH TOL NGING FROM HTOL MAY CHANGE oun BE FROMLTOH ANGING FROM L TOH DON T CARE, CHANGING ANY CHANGE STATE PERMITTED UNKNOWN < I t Zz a x x a u Typical Power-Supply Currents Versus Frequency 10k CLOCK PERFORMANCE CURVES Typical Data Output HIGH Current Versus Data Output Voltage 25 2.0 Ta 2 -55C Ta =+25C | Te = +125c fon nA 1.0 0.5 | Yop = GND Vgg = +5.0V =-12.0V 9 1 2 3 Vou (V? Typical Propagation Delay Versus Ambient Temperature 1 200 150 PROPAGATION DELAY ns Vgs = +5.0V Voo = OV Vag = -12.0V 1 CTT gg 168 vpp +O vgg*-120V 100 -65 -36-15 5 25 469 G5 85 105 125 AMBIENT TEMPERATURE - C 100k 1M FREQUENCY Rz 10M MOS-454 DEFINITION OF TERMS STATIC SHIFT REGISTER A shift register that is capable of maintaining stored data without being continuously clocked. Most static shift registers are constructed with dynamic master and static slave flip-flops. The data is stored dynamically while the clock is HIGH and is transferred to the static slaves while the clock is LOW. The clock may be stopped indefinitely in the LOW state, but there are limitations on the time it may reside in the HIGH state. -55 SET-UP and HOLD TIMES The shift register will accept the data that is present on its input around the time the clock goes from HIGH-ta-LOW. Because of variations in individual devices, there is some uncertainty as to exactly when, relative to this clock transition, the data will be stored. The set-up and hold times define the limits on this uncertainty. To guarantee storing the correct data, the data inputs should not be changed between the maximum set-up time before the clock transition and the maximum hold time after the clock transition. Data changes within this interval may or may not be detected. Am40/5055 Am40/5056 Am40/5057 Am4055/5055 RC Yon 1 16 DIE SIZES 0.101" X 0.140" Metallization and Pad Layouts 14 OUTA INA 2 INA QuTe@ 4 our A 12 INB 12 OWTC INC 5 IN B OUTD 7 OUT 8 yOIND a 9 1G ss CP vag Am4047/5057 RC Yoo 1 8 In 2 ouT 3 Am4056/5056 ac Ww 9 Yop