= ST, ST10F168 16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM HIGH PERFORMANCE CPU 16-BIT CPU WITH 4-STAGE PIPELINE 80ns INSTRUCTION CYCLE TIME AT 25MHz CPU CLOCK 400ns 16 X 16-BIT MULTIPLICATION 800ns 32/ 16-BIT DIVISION ENHANCED BOOLEAN BIT MANIPULATION FA- CILITIES ADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMS SINGLE-CYCLE CONTEXT SWITCHING SUPPORT MEMORY ORGANIZATION 256K BYTE ON-CHIP FLASH MEMORY 1K ERASING /PROGRAMMING CYCLES UP TO 16M BYTE LINEAR ADDRESS SPACE FOR CODE AND DATA (5M BYTE WITH CAN) 2K BYTE ON-CHIP INTERNAL RAM (IRAM) 6K BYTE ON-CHIP EXTENSION RAM (XRAM) FAST AND FLEXIBLE BUS PROGRAMMABLE EXTERNAL BUS CHARACTE- RISTICS FOR DIFFERENT ADDRESS RANGES 8-BIT OR16-BIT EXTERNAL DATA BUS MULTIPLEXED OR DEMULTIPLEXED EXTER- NAL ADDRESS / DATA BUSES FIVE PROGRAMMABLE CHIP-SELECT SIGNALS HOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT INTERRUPT 8-CHANNEL PERIPHERAL EVENT CONTROL- LER FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA TRANSFER 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH 56 SOURCES, SAMPLE-RATE DOWN TO 40ns TIMERS TWO MULTI-FUNCTIONAL GENERAL PURPOSE TIMER UNITS WITH 5 TIMERS -TWO 16-CHANNEL CAPTURE / COMPARE UNITS. 4-CHANNEL PWM UNIT SERIAL CHANNELS SYNCHRONOUS / ASYNCHRONOUS SERIAL CHANNEL HIGH-SPEED SYNCHRONOUS CHANNEL A/D CONVERTER 16-CHANNEL 10-BIT 7.76uS CONVERSION TIME FAIL-SAFE PROTECTION PROGRAMMABLE WATCHDOG TIMER OSCILLATOR WATCHDOG August 1999 PRELIMINARY DATA PQFP 144 (28 x 28 mm) (Plastic Quad Flat Pack) ON-CHIP CAN 2.0B INTERFACE ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION ON-CHIP PLL DIRECT OR PRESCALED CLOCK INPUT. UP TO 111 GENERAL PURPOSE //O LINES INDIVIDUALLY PROGRAMMABLE AS OUTPUT OR SPECIAL FUNCTION. PROGRAMMABLE THRESHOLD (HYSTERESIS) IDLE AND POWER DOWN MODES 144-PIN PQFP PACKAGE INPUT, CPU Core PEC Interrupt controller = Oo O ou < oO P. 1/75 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.ST10F168 TABLE OF CONTENTS Page I INTRODUCTION .......ccccceseeesteessessneeseeeeseeseeeeeesesesceeesaeeseeessaesseeesanesaneesanesaeesasnnsseeaeesnes 4 I PIN DATA o.oo. cece ee scene sense eeenee esses eenneeeseessesaeeeegeesesaneeeseneessaaeseaeneeeseaeseaeneeessaeaeaaneeetaas 5 Hl FUNCTIONAL DESCRIPTION .......:ccccccssssseeeesereeeceeeseesesnesseeesseesanessneesaneseenaaennsesanensnes 10 IV MEMORY ORGANIZATION .......cccccccsseesseessceesneeseneeseesseeeseceaeeseensaessceessnessneesanesaneaaeneaas 11 Vv FLASH MEMORY ........c:ccscecseesseessneesseesseesseeeescsesereesensneessnessneesneenaeenaees ceevanensenenesnanes 13 V4 PROGRAMMING / ERASING WITH ST EMBEDDED ALGORITHM KERNEL .......... 14 V.2 PROGRAMMING EXAMPLES ....... eee cee eee eneee tence sere seeeseeeesneeeeeeesaeenneetsaeenaes 16 V.3 FLASH MEMORY CONFIGURATION.......0.. ccc eee eeeeereeeeeeeeneeeneennteenieensieeeas 18 V.4 FLASH PROTECTION .......ceccccercentee cite eneeeereesn ener eenesineesieessieesieesenreserenentennaes 18 Vi CENTRAL PROCESSING UNIT (CPU)... ..:cseccsssssesseeeeeseseeseeeseessceessnessneesaeesaeeaeeneens 19 Vi INSTRUCTION SET SUMMARY... cc cec cece enter renee eentesiieesieetiieenieeeneenes 20 Vil EXTERNAL BUS CONTROLLER..........:eccseesseesseeeseeseeenseseseeenessuessceessnesaneesaneesenaneneeas 22 Vill INTERRUPT SYSTEM ........ccccccseeeseessseesseesseeseneeseeseeeeeesesecaeeesnesseeesanesanessneesaneseenaaenneas 23 IX CAPTURE / COMPARE (CAPCOM) UNIT .........:cessecsseesseesscesseeeseneesersnssneeseessanenenensaes 25 xX GENERAL PURPOSE TIMER UNIT..........:csccceseesseeessesseessneesseeseeneeeeesesaeeeenessneenenesans 27 X.4 GPT oo rr nn ne ee ernie seenentesineeenteniieenieenieenienetee 27 X.2 GPT 2 ooo rr nn nn ne nine seenentennneeenteniieenienieenieenete 27 Xl PWM MODULE ....0...ccccccee cceeesseessessneeseneeseeaeeeeennesesaeeecnesseesenesanesaeeesaneseenaaenesesoessanensaes 30 Xil PARALLEL PORTS... 01.00 cesssseeeeeeseeeeeeseeeecnesseeesenesaneesneesaeesaeeeeenesesaeeeseeesanesanessneesonenanes 31 Xill A/D CONVERTER. .....:cccccssesseeeseeeseenecnenene sncneesnesseeessnesaneesaeesanesaseeeseesesaneeseeesueesanesones 32 XIV SERIAL CHANNELS. ...... cc cceessceeseeeeeseeeereeeeeeeseessceesseessneesaeeseeaaeneesneaesane seneasenaessnsesanes 33 XV CAN MODULE ....0....eccccceeesseesseeesneeseeeeseesseeeeeceseseeescnessaeesaeesanesaeeaseneseseaeeaesesuessaeesanesanes 35 XVI WATCHDOG TIMER... ..ccccseeeeeeeeeseeeseeeecnesseeescnessneesneesseeseeeessneaaseeeeseessanessnessneesanenanes 35 XVII SYSTEM RESET j.....c:cceeceseeceseeeseeesceesseesaneeseeeeaeeseeeaeesesesesscnessaessneesaeesaneasenesesesnsanensaes 36 XVII ASYNCHRONOUS RESET (LONG HARDWARE RESET)..........:::ecceeeeteestersteenees 36 XVIL.2 SYNCHRONOUS RESET (WARM RESET) ........:eccceccecrceeeeneeeneeenneetieenneeeneeeetenes 37 XVIL3 SOFTWARE RESET .000.. cc ecceceeren een een erin e riser tieeeneecneetenesenresniresiesiietieeentenes 38 XVII.4 WATCHDOG TIMER RESET .......0 cece ier ener cn ereneenneenieeniiesiieesieenieetiee . 38 XVII.5 RESET CIRCUITRY 0... cer er rn nents niee teste siesenessntesenteenressiresiaeenaes 38 4] 2/75ST10F168 TABLE OF CONTENTS (continued) Page XVIII POWER REDUCTION MODES. .......csecccesecessseeeeeeeeeesneeeeneeeeeesaeseneeeeescaeseaseeeessnessennenenes 42 XIX SPECIAL FUNCTION REGISTER OVERVIEW. .......ccc0 ccsesecessseeeeeeeessseeseseeeesseeseneeeees 43 XIX. 1 IDENTIFICATION REGISTERS .........cecccceccceeeeeeeeeeceeeceeeeeeaeeeseeeesecaeeeseneesenureeeteaeeees 49 XX ELECTRICAL CHARACTERISTICS .......cccsssececeseeesseeeeeseeeesseeeeeeneeesseeeenseeeessseensenees . 50 XX.1 ABSOLUTE MAXIMUM RATINGS .......0.... cccceccceeeceececeececececeseseeeeceeeeseaeeesereeseceeesenees 50 XX.2 PARAMETER INTERPRETATION ...........::cccccecceeeeeeceeeeeeeseeeeeceeeseeeeecceeeesareeessaeessaees 50 XX.3 DC CHARACTERISTICS. ..........cccccccccecceeseeeeceeeeceeeesecaeeeceaeeseaeeeseaeeseceeeseceeseeieeesnnaeeees 50 XX.4 A/D CONVERTER CHARACTERISTICS. ...........:::cccccceeecceeeceeeeseeeeseceeeseeesesneeesenaeeees 53 XX.5 AC CHARACTERISTICS... ........::ccccccceeeeeccececeeeeeeeeeceaeeceeeeeseaeessaeeeseceeeesneesesieeetnnaeenes 54 XX.5. 1 T@St WAVETOFMS .......eeceeccceceeeeceeeeceeeceeeeeeeeececeeeecaceesaaeeececeesecaeeesaaeeseceeesiieeeseureesinaeeees 54 XX.5.2 Definition of internal timMiNg ...............:ecceeeececeece cence ee ceeeeeeeeeeseaeseeeeeesecaeeeseeeesneeesennees 54 XX.5.3 Clock generation MOCES..............cccccccceeeceeceeeeceeteeeeeeceaeeeeeeeeeteaeeeseeeeecsaeeessneeessieeeesiaeeess 55 XX.5.4 PrescCaler OPCration ........ cc ccc ce eetteeeeeeeeeeeeeeennieeees centieeeeeeeeeesessiieeeeeesenieeeeesenaes 56 XX.5.5 DireCt CVIVE oo. eee tier reenter etree neers ernie eee e rites eee sieeeeeeennineeeeseigneeeeeeas 56 XX.5.6 Oscillator Watchdog (OWD) ............:::ccccccceceeceeeeeeeeceeeecceeseaeeesaeeseceeeseeeseeuneesnneeneees 56 XX.5.7 Phase locked l0Op .........cccccccceeceececeeteetee ceieeeeeeeeiieeeeeeeinieeeeeeneeeeeeniieeeeessineeeesenaes 56 XX.5.8 External clock drive XTAL1 ...... eee eee eee e teenie eee eeecneeeeeeeecieeeeeeeiceeeseeenieeeeeeenaes . 57 XX.5.9 Memory cycle Variables ........... cc ccccccceeceeceeeeeceeeeeeeeeceeeeeseeeeeeeseeeaeeeeseenaeeeseeecieeeeeeenaees 58 XX.5.10 = Multiplexed DUS... 2... cceecceeee eee cecee cence ee ceceeeeeeeeeeenneee ceceeeeeccaeeeseseesseaeeeseeeessureeeseeees 58 XX.5.11 Demultiplexed DUS 00.0.2... cece tr eerie teenie ete eenieeeeeeeieeeeeeeiineeeseeeiinteeeesineeeeeenaees 64 XX.5.12 CLKOUT and READY........0..cccccceccccec cece ceeee cee ceeeeeeeeeeseeeeeceeeessueeessneeetnnee seeseneeeenieeeesaes 70 XX.5.13 External DUS arbitration........00... cece tener eeeteeeeeeicieeeeeenieeeeeeesiieeeeeesiiieeeeeetiieeeeeetaa 72 XXl PACKAGE MECHANICAL DATA .....ccccccsseeeeeeeeteeteee ceeeeeceeseneeeeeesnesesneeeeneneeeeseeeneee 74 XXIl ORDERING INFORMATION .......:ccsceecesceeesseeeeeeeeeeseeeeneeeeesccaesaseeeesecaesaseeeeeeseeeeasneeeneees 74 4] 3/75ST10F168 | - INTRODUCTION The ST10F 168 is a derivative of the ST Microelec- peripheral functionality and enhanced I/O capabil- tronics 16-bit single-chip CMOS microcontrollers. ities. It also provides on-chip high-speed It combines high CPU performance (up to 12.5 million instructions per second) with high Flash memory, on-chip high-speed RAM, and clock generation via PLL. Figure 1 : Logic Symbol . iS XTAL1 =___p Port 0 XTAL2 q _ 16-bit RSTIN > ~ Port 1 RSTOUT + 16-bit Vpp Port 2 V 16-bit AREF VacND 7 ST10F168 Port 3 Nv 15-bit EA @ Port 4 READY > 8-bit aa RD + WR/WRL #_ Port 7 Port 5 16-bit Port 8 8-bit 4] 4/75ST10F168 Figure 2 : Pin Configuration (top view) Il- PIN DATA 29 Fe, 22 +E OxFE 90 Dn owotogyre OO YaWAACE a8qggega08o4q ONHEOMONCA TOR Xx ZZ tedeetdaete NVUYGTEEEo 8 VCO@ECEESNS SRSEHtANLS tistiisitin wWaaAHK-SLSeEE DPojjsijogsI8 Boe eS Be Beem ans oooooonan >poanoanoanoaoa>s> santana onon BROWN TMNTODAROMTMNNr OMDARONMNTMANrOMwArOoONnNTSD TFOOSSTSSOSSOAHAAMMAAMAIAAMMDADANDNDNDDADAAWDARKRNAMMAERE aa eer rere ssh =r 6dV/lHOd FSSA OLGW/e'HOd FNIP L/S Ed A CNSel/y ed A INOEL/e Ed ANIA VO/e Ed A ILNOGL/L Ed AINIOL/O'Ed BINIZL/NIZXS/OIS LOO/G bed FINISXA/OlV LOO/F Led FINISXA/OIELOO/E b Sd FINIPXA/OIS LOD/e b Sd | LOW/ HOd bdv/r'H0d -0W/G'HOd vldv/9HOd SLOW/ZHOd OV/O"lld LYW/F Tk ovie Ikd eve lkd bviv'Ikd FNIEXAOILLOO/L bed Sv/G"TIhd FANIZ@XSOI0LOO/0l ed 9v/9"1kd FINI LXS/OIGDD/6 ed AIL kd oO FANIOXA/Ol890/8 ed dda by GA, SSA LL Hi SSA 8V/O'HId S A OIZDO/L ed 6V/FHId oe A OI9DO/9'ed OLW/eHIld A OIGDO/S' ed LEW/e Hkd A OWOO/F ed OlveDO/e lW/t'Hkd A OIEDO/E ed OISeDO/E LW/S Hd A OlZD0/ ed OI9ZDO/F LW/9'Hk-d AOILOO/b ed OIZ29DO/S W/Z Hd AI OI0D9/0'ed ada o1WLlx FIWLX HCNACL/SLNV/SL' Sd SSA HONar L/h lNW/Pl Sd NILSY AINIGL/S LNV/E LS Lois FINISL/ZLNV/2L'Sd WN HCNaSL/LENW/IL'Sd SSA HONAIL/OLNV/OL Sd dda A ONOV Aj, b AF A, CDrHNMTWONRDDOrTNAMTMNOR DDO NMTWO Orr rrrrmr rT TH NNNNNNNNNNO OOOO TUUUUoU Uo UU Ua ada uuu ue OudaudU urdu ur obUud udu oud ou QOANOrNMOODOODOOMAMYTNMOORDODDHD ODOOO000O BREE RP SSSessISseeses CRO SSANR>> 22 PANNS RSS LLKIELEE SHaat 900900000 OOOO OOS OS HARSH ERAS SGHoOKDHOnoOHOSOROQVIVIVOVOO SSSR SY Y YYW YYW YH W DW) AAAAH ES GSKHAALHSR SHNGA$HoONanaAaAnaoanAnAaAo OO Some onoeus KBR RRR IN POPP RRR oooonnoo00 5/75ST10F168 Il - PIN DATA (continued) Table 1 : Pin Description Symbol Pin Type Function P6.0 - P6.7 1-8 1/0 |8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The following Port 6 pins have alternate functions: 1 QO |P6.0 cso Chip Select 0 Output 5 O |P6.4 cS4 Chip Select 4 Output 6 | |P6.5 HOLD External Master Hold Request Input 7 O |P6.6 HLDA Hold Acknowledge Output 8 QO |P6.7 BREQ Bus Request Output P8.0 - P8.7 9-16 1/0 |8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins have alternate functions: 9 1/0 |P8.0 CC16I0 CAPCONM2: CC16 Capture Input / Compare Output 16 1/0 |P8.7 CC2310 CAPCONM2: CC23 Capture Input / Compare Output P7.0 - P7.7 19-26 1/0 |8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins have alternate functions: 19 QO |P7.0 POUTO PWM Channel 0 Output 22 O |P7.3 POUTS3 PWM Channel 3 Output 23 1/0 |P7.4 CC2810 CAPCONM2: CC28 Capture Input / Compare Output 26 1/0 |P7.7 CC3110 CAPCOM2: CC31 Capture Input / Compare Output P5.0 - P5.9 27-36 | |16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be P5.10-P5.15]| 39-44 | |the analog input channels (up to 16) for the A/D converter, where P5.x equals ANx (Analog input channel x), or they are timer inputs: 39 | |P5.10 T6EUD GPT2 Timer T6 External Up / Down Control Input 40 | |P5.11 T5EUD GPT2 Timer T5 External Up / Down Control Input 41 | |P5.12 T6IN GPT2 Timer T6 Count Input 42 | |P5.13 T5IN GPT2 Timer T5 Count Input 43 | |P5.14 T4EUD GPT1 Timer T4 External Up / Down Control Input 44 | |P5.15 T2EUD GPT1 Timer T2 External Up / Down Control Input 6/75 kyST10F168 Il - PIN DATA (continued) Table 1 : Pin Description (continued) Symbol Pin Type Function P2.0 - P2.7 47-54 1/0 |16-bit bidirectional |/O port, bit-wise programmable for input or output via direction P2.8- P2.15 57-64 bit. Programming an |/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins have alternate functions: 47 1/0 |P2.0 ccolo CAPCOM: CCO Capture Input / Compare Output 54 1/0 |P2.7 cc7lo CAPCOM: CC7 Capture Input / Compare Output 57 1/0 |P2.8 ccslo CAPCOM: CC8 Capture Input / Compare Output | EXOIN Fast External Interrupt 0 Input 64 1/0 |P2.15 CC1510 CAPCOM: CC15 Capture Input / Compare Output | EX7IN Fast External Interrupt 7 Input | T7IN CAPCOM2 Timer T7 Count Input P3.0 - P3.5 65-70, I/O |15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or P3.6 - P3.13, | 73-80, I/O Joutput via direction bit. Programming an I/O pin as input forces the corresponding P3.15 81 I/O Joutput driver to high impedance state. Port 3 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins have alternate functions: 65 | |P3.0 TOIN CAPCOM Timer TO Count Input 66 QO |P31 T6OUT GPT2 Timer T6 Toggle Latch Output 67 | |P3.2 CAPIN GPT2 Register CAPREL Capture Input 68 O |P33 T30UT GPT1 Timer T3 Toggle Latch Output 69 | |P3.4 T38EUD GPT1 Timer T3 External Up / Down Control Input 70 | |P3.5 T4IN GPT1 Timer T4 Input for Count / Gate / Reload / Capture 73 | |P3.6 T3IN GPT1 Timer T3 Count / Gate Input 74 | |P3.7 T2IN GPT1 Timer T2 Input for Count / Gate / Reload / Capture 75 0 |P3.8 MRST SSC Master-Receiver / Slave-Transmitter I/O 76 0 |P3.9 MTSR SSC Master-Transmitter / Slave-Receiver O/I Tf 1/0 |P3.10 TxDO ASCO Clock / Data Output (Asynchronous / Synchronous) 78 O |P3.11 RxDO ASCO Data Input (Asynchronous) or I/O (Synchronous) 79 O |P3.12 BHE External Memory High Byte Enable Signal WRH External Memory High Byte Write Strobe 80 /O |P3.13 SCLK SSC Master Clock Output / Slave Clock Input 81 O |P3.15 CLKOUT System Clock Output (=CPU Clock) 4] 7/75ST10F168 Il - PIN DATA (continued) Table 1 : Pin Description (continued) Symbol Pin Type Function P4.0 - P4.7 85-92 I/O |8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. For external bus configuration, Port 4 can be used to output the segment address lines: 85-89 O |P4.0-P4.4 A16-A20 Segment Address Line 90 O |P4.5 A2t Segment Address Line | CAN_RxD CAN Receiver Data Input 91 O |P4.6 A22 Segment Address Line 0 CAN_TxD CAN Transmitter Data Output 92 O |P4.7 A23 Most Significant Segment Addrress Line RD 95 OQ |External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/AWRL 96 O |External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL mode this pin is activated for low Byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. READY/ 97 | |Ready Input. The active level is programmable. When the Ready function is READY enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of wait state cycles until the pin returns to the selected active level. ALE 98 O |Address Latch Enable Output. In case of use of external addressing or of multi- plexed mode, this signal is the latch command of the address lines. EA 99 | |External Access Enable pin. A low level at this pin during and after Reset forces the ST10F 168 to start the program in internal memory space. A high level forces the ST10F 168 to start in the external memory space. POL.O - POL.7 [100 - 107,| I/O |Two 8-bit bidirectional I/O ports POL and POH, bit-wise programmable for input or POH.O 108, output via direction bit. Programming an I/O pin as input forces the corresponding POH.1 - POH.7] 111 - 117 output driver to high impedance state. In case of an external bus configuration, PortO serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demul- tiplexed bus modes. Demultiplexed bus modes Data Path Width: 8-bit 16-bit POL.O POL.7: DO - D7 DO - D7 POH.O POH.?7: VO D8 - D15 Multiplexed bus modes Data Path Width: 8-bit 16-bit POL.O POL.7: ADO - AD7 ADO - AD7 POH.O POH.?7: A8 A15 AD8 AD15 8/75 4]ST10F168 Il - PIN DATA (continued) Table 1 : Pin Description (continued) Symbol Pin Type Function P1L.0 - P1L.7 | 118-125 | I/O |Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or P1H.0 - P1H.7] 128-135 output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following Port1 pins have alternate functions: 132 | |P1H.4 CC2410 CAPCONM2: CC24 Capture Input 133 | JP1H.5 CC2510 CAPCON2: CC25 Capture Input 134 | |JP1H.6 CC2610 CAPCONM2: CC26 Capture Input 135 | |P1H.7 CC2710 CAPCON2: CC27 Capture Input XTAL1 138 | |XTAL1 Oscillator amplifier and internal clock generator input XTAL2 137 O |XTAL2: Oscillator amplifier circuit output. To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed. RSTIN 140 | |Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F168. An internal pullup resistor permits power-on reset using only a capacitor connected to Vgg. In bidirec- tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence. RSTOUT 141 OQ {Internal Reset Indication Output. This pin is set to a low level during hardware, soft- ware or watchdog timer reset. RSTOUT remains low until the EINIT (end of initial- ization) instruction is executed. NMI 142 | |Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = 0 in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI_pin must be low in order to force the ST10F168 to go into power down mode. If NMIis high and PWDCFG ='0, when PWRDN is executed, the part will continue to run in normal mode. If it is not used, pin NMI should be pulled high externally. VAREF 37 - |A/D converter reference voltage. VAGND 38 - |A/D converter reference ground. Vpp/RPD 84 - |Flash programming voltage. Programming voltage of the on-chip Flash memory must be supplied to this pin. It is used also as the timing pin for the return from interruptible powerdown mode. Vop 17,46, - 56,72, Digital Supply Voltage: 82,93, = + 5V during normal operation and idle mode. 109, 126, > 2.5V during power down mode. 136, 144 Vss 18,45, - 55,71, 83,94, Digital Ground. 110, 127, 139, 143 4] 9/75ST10F168 Ill - FUNCTIONAL DESCRIPTION The architecture of the ST10F168 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. Figure 3 : Block Diagram The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F168. 256K Byte Flash memory 6K Byte XRAM CAN_RxD P4.5 CAN_TxD P4.6 ExternalBus Controller 10-BitADC Interrupt Controller = rc s > = 3 Oo O oO oO O 2 <||& oO oO 16 Internal RAM 10/75 4]ST10F168 IV - MEMORY ORGANIZATION The memory space of the ST10F 168 is configured in a Von Neumann architecture. Code memory, data memory, registers and I/O ports are orga- nized within the same linear address space of 16M Byte. The entire memory space can be accessed bytewise or wordwise. Particular por- tions of the on-chip memory have additionally been made directly bit addressable. FLASH: 256K Byte of on-chip Flash memory. See Flash Memory on page 13 IRAM: 2K Byte of on-chip internal RAM (dual-port) is provided as a storage for data, sys- tem stack, general purpose register banks and code. A register bank is 16 wordwide (RO to R15) and / or bytewide (RLO, RHO, ..., RL7, RH7) gen- eral purpose registers. XRAM: 6K Byte of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code. The XRAM is connected to the internal XBUS and is accessed like an external memory in 16-bit demultiplexed bus-mode without wait state or read / write delay (80ns access at 25MHz CPU clock). Byte and Word access are allowed. The XRAM address range is O0ODOOOhH - 00E7FFh if the XRAM is enabled (XPEN bit 2 of SYSCON register). As the XRAM appears like external memory, it cannot be used for the ST10F168s system stack or register banks. The XRAM is not provided for single bit storage and 4] therefore is not bit addressable. If bit XPEN is cleared, then any access in the address range 00DO000h - 00E7FFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. SFR/ESFR: 1024 Byte (2 x 512 Byte) of address space is reserved for the Special Function Regis- ter areas. SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. CAN: Address range 00EFOOh - 00EFFFh is reserved for the CAN Module access. The CAN is enabled by setting XPEN bit 2 of the SYSCON register. Accesses to the CAN Module use demul- tiplexed addresses and a 16-bit data bus (Byte accesses are possible). Two wait states give an access time of 160ns at 25MHz CPU clock. No tristate wait state is used. Note If the CAN module is used, Port 4 can not be programmed to output all 8 segment address lines. Therefore, only 4 segment address lines can be used, reducing the external memory space to 5M Byte (1M Byte per CS line) To meet the needs of designs where more mem- ory is required than is provided on chip, up to 16M Byte of external RAM and / or ROM can be con- nected to the microcontroller. 11/75ST10F168 IV - MEMORY ORGANIZATION (continued) Figure 4 : ST10F168 on-chip memory mapping | Segment 2 | Segment 3 | Segment 4 | Segment 1 Segment 0 RAM, SFR and X-pheripherals are mapped into the address space. SYSCON.XP EN=1 enables CAN and XRAM (before EINIT) 0x14 0x50000 Ox4'FFFF 0x13 0x4C000 0x12 0x48000 Ox11 0x44000 Bank 3: 96K Byte 0x10 0x40000 OxOF | Ox3C000 OxOE | 0x38000 Ox3'7 FFF OxOD | 0x34000 OxO0C | 0x30000 O0x0B 0x2C000 Bank 2: 96K Byte OxOA | 0x28000 0x09 0x24000 0x08 0x20000 Ox1'FFFF 0x07 0x1C000 Bank 1H : 32K Byte 0x06 0x18000 Ox?'7FFF Bank iL: 16K Byte 0x05 0x14000 Ox1'3FFF Bank 0: 16K Byte 0x04 0x10000 0x02 0x08000 Ox0'7FFF Bank 1L: 16K Byte 0x01 0x04000 OxO'3FFF Bank 0: 16K Byte 0x00 0x00000 Data Absolut Page Memory Number Address OxOFFFF SFR Area 0x0 FE0O OxOFDFF IRAM : 2K Byte 0x0F600 OxOEFFF CAN Module 0x0 EFOO OxOE7FF XRAM : 6K Byte 0x0DO00 * Bank 0 and Bank 1 L may be remapped from segment 0 to segment 1 by setting SYSCON.ROMS1 (before EINIT) 12/75 4]ST10F168 V - FLASH MEMORY The ST10F168 provides 256K Byte of an electrically erasable and reprogrammable Flash Memory on-chip. The Flash Memory can be used both for code and data storage. It is organized into four 32-bit wide blocks allowing even double Word instructions to be fetched in one machine cycle. The four blocks of size16K, 48K, 96K and 96K Byte can be erased and reprogrammed individually (see Table 2 and Table 3). The Flash Memory can be programmed in a pro- gramming board or in the target system which provides high system flexibility. The algorithms to program or erase the flash memory are embed- ded in the Flash Memory itself (ST Embedded Algorithm Kernel, or STEAK). To start a program / erase operation, the users software has just to load GPRs with the address and data to be programmed, or sector to be erased. STEAK uses embedded routines, which check the validity of the programmed parameters, decode and then execute the programming or erase command. During operation, the STEAK routines carry out checks and retries to verify proper cell programming or erasing. When an error occurs, STEAK returns an error-code which identifies the cause of the error. A Flash Memory protection option prevents the read-back of the Flash Memory contents from external memory, or from on-chip RAM. Code operation from within the Flash continues as nor- mal. The first bank (16K Byte) and part of the second bank (16K Byte out of 48K Byte) of the on-chip Flash Memory of the ST10F168 can be mapped to either segment O (addresses 00000h to 07FFFh) or to segment 1 (addresses 10000h to 17FFFh) during the initialization phase. External memory can be used for additional system flexibility. Vopp =5V+ 10%, Vpp =12V+ 5%, Vss = OV, fopu = 25MHz, for Q6 version : Ta = -40, +85C and for Q2 version TA = -40, +125C. Table 2 : Flash Memory Characteristics Symbol Parameter Test Conditions Min. Typ. Max. Unit fepy |CPU Frequency during 5 - 25 MHz erasing / programming operation Cyc Erasing / Programming Cycles fepy = 25MHz - - 10001 tspra |Single Word Programming Time fopu = 25MHz - 10 301 ls tppRg |Double Word Programming Time fopyu = 25MHz - 10 30" us tespnk [Sector Erasing Time fopy = 25MHz - 0.8 601 s tretT |Data Retention Time Defectivity below 1ppm / year 10 - - year Note 1. Typical value for a non cycled flash. Maximum value is a software limit put inside STEAK. Can be changed after flash characterization by STMicroelectronics. Table 3 : Flash Memory Bank Organisation Bank Addresses (segment 0) Addresses (segment 1) Size (Byte) 0 000000h to OO3FFFh 010000h to 013FFFh 16K 1 004000h to OO7FFFh + 018000h to 01FFFFh 014000h to 01FFFFh 48K 2 020000h to 037FFFh 020000h to O3FFFFh 96K 3 038000h to O4FFFFh 038000h to O4FFFFh 96K ky 13/75ST10F168 V - FLASH MEMORY (continued) V.1 - Programming / erasing with ST Embedded Algorithm Kernel There are three stages to run STEAK : To load the registers RO to R4 with the STEAK command, the address and the data to be pro- gramed, or sector to be erased. Table 4 gives the STEAK parameters for each type of Flash programming / erasing operation. Table 5 de- fines the codes used in Table 4. To initiate the Unlock Sequence. The Unlock Se- quence is composed of two consecutive writes to an even address in the Flash active address space - the first write has direct addressing mode (MOV mem, Rwn) - the second write has indirect addressing mode (MOV [Rwm], Rwn). Rwn canbe any unused Word-GPR (R6 to R15) loaded with a value resulting in the same even address as mem. Table 4 : STEAK parameters To read the return values in RO. When the em- bedded programming / erasing algorithm re- turns to trigger point, return values are given in RO. Table6 gives the error-code definitions, Table 7 gives the return values in each register for each type of Flash programming / erasing command. Note The Flash Embedded STEAK Algorithms require at least 50 words on the Internal System Stack. STEAK verifies that there is enough free space on the System Stack, before performing a programming or eras- ing operation. The MDH, MDL and MDC register content are modified. Code examples for programming and erasing the Flash Memory using STEAK are given in Section V.2. Command RO R1 R2 R3 R4 Single Word programming 55Ash AddOff Ww nu 2TCL Double Word programming DD4sh AddOff DWL DWH 2TCL Multiple (block) programming AA5sh BegAddOff EndAddOff SourceAddr 2TCL Sector Erasing EEEEh 5555h Bnk Bnk 2TCL Read Status 7777h nu nu nu 2TCL Table 5 : Programming / erasing code definition s Segment of the Target Flash Memory cell, AddOff Segment Offset of the Target Flash Memory cell. Must be even value (Word-aligned address). Ww Data (Word) to be written in Flash. DWL,DWH |Data (double Word, DHL = low Word, DWH = high Word) to be written in Flash. Segment Offset of the FIRST Target Flash Memory Word to be written in a Multiple programming BegAddOff : command. Must be even value (Word-aligned address). Segment Offset of the LAST Target Flash Memory Word to be written in a Multiple programming command. EndAddOff |Must be even value (Word-aligned address). The value D = (EndAddOff - BegAddOff) must be: 0 <= D < 16384 (ie. up to one page (16K Byte) can be written in the flash with one multi-Word programming command). Start address for the block to be programmed. This address is using implicitly the data paging mechanism of the CPU. SourceAdd value must respect the following rules : SourceAdd |- SourceAdd + (EndAddOff - BegAddOff) < 16384. - Page 0 and 1 can NOT be used for source data if bit ROMS1 = 1 (in SYSCON register). Note that source data can be located in Flash (In pages 0, 1, 6 to 19 if bit ROMS1 = O", or in pages 4 to 19 if bit ROMS1 = 1). Bnk Number of the Bank to be erased. For security, R2 and R3 must hold the same value. 2TCL CPU clock period in nano-seconds (eg. R4 = 50d means CPU frequency is 20MHz). 14/75 kyST10F168 V - FLASH MEMORY (continued) Table 6 : RO error codes RO Value Meaning 00h Operation was successful Oth ROMEN bit inside SYSCON is not set or Flash is protected 02h Vpp voltage not present 03h Programming operation failed 04h Address value (R1) incorrect: not in Flash address area or odd address 05h CPU period out of range (must be between 10 ns to 1000 ns) 06h Not enough free space on system stack for proper operation 07h Incorrect bank number (R2,R3) specified 08h Erase operation failed 09h Bad source address for multi-Word programming command OAh Bad number of words to be copied in multi-Word programming command: one destination will not be in the flash, or one source operand will not be in the source page FFh Unknown or bad command Table 7 : Return values for each programming / erase command Programming | Ro R1 R2 R3 R4-R15 Command Single or Error Unchanged Data in Flash for}Data in Flash for}Unchanged double Word code location Segment +|location Segment + programming Segment Offset] Segment Offset + 2 (RO.[8:0] with R1) | (RO[8:0] with R1+2) Block Error |The last segment offset address of the | Undefined Unchanged programming |code |last written Word in Flash (failing Flash address if RO is not equal to zero) Erasing Error Undefined Unchanged code After status Error |Flash embedded rev Circuit identifiers : Unchanged read code | MSByte = major release R2 = #0787h LSByte = minor revision R3 = #0101h for this device Note The Flash Embedded STEAK Algorithms 4] require at least 50 words on the Internal System Stack for proper operation. The program itself verifies that there is enough free space on the System Stack before performing a programming or erasing operation, by computing the Word number between Stack Pointer (SP) and Stack Overflow register (STKOV ). The MDH, MDL and MDC register content are modified. Registers RO to R4 are used as Input Data for STEAK, and are modified as explained above (Return Values). Registers R5 to R15 are used internally by STEAK, but preserved on entry and restore on exit of STEAK. IT 1S VERY IMPORTANT TO TAKE INTO ACCOUNT THE FACT THAT STEAK USES UP TO 50 WORDS ON THE SYS- TEM STACK. TO PREVENT ANY ABNORMAL SITUATION, IT IS VERY IMPORTANT TO INITIALIZE COR- RECTLY THE STACK SIZE TO AT LEAST 64 WORDS, AND TO CORRECTLY INI- TIALIZE REGISTER STKOV. 15/75ST10F168 V - FLASH MEMORY (continued) V.2 - Programming Examples Programming a double Word ; code shown below assumes that Flash is mapped in segment 1 ; le. bit ROMS1 = 1 in SYSCON register ; Flash must be enabled, ie. bit ROMEN = 1 in SYSCON. MOV RO, #0DD40h ; DD4xh : Double Word programming command OR RO, #01h ; Selects segment 1 in flash memory MOV Rl, #00224h ; Address to be programmed is 010224h MOV R2, #03456h ; Data to be programmed at 010224h MOV R3, #04567h ; Data to be programmed at 010226h MOV R4, #050d ; 50ns is 20MHz CPU clock frequency MOV R7, #08000h ; R7 used for Flash trigger sequence #define FCR 08000h ; Flash Unlock Sequence consists in two consecutive writes, with the direct addressing mode and then the indirect addressing mode. FCR must represent an even address in the active address space of the Flash memory, and Rwn can be any unused Word GPR (R6 to R15)loaded with a value resulting in the same even address than FCR EXTS #1, #2 ; Flash can be mapped in segment 0 or 1 MOV FCR, R7 ; first part MOV [R7], R7 7 second part NOP ; WARNING: place 2 NOP operations after NOP ; the Unlock sequence to avoid all possible j pipeline conflicts in STEAK programs Note For easier coding, the standard data paging addressing scheme is overriden for the two MOV instructions of the Flash Trigger Sequence (EXTS instruction). However this coding also locks both standard and PEC interrupts and class A hardware traps. This override can be replaced by an ATOMIC instruction if the standard DPP addressing scheme must be preserved. 4] 16/75ST10F168 V - FLASH MEMORY (continued) Programming a block of data The following code is provided as an example to program a block of data. Flash to be programmed is from address 019000h to 019FFEh (included). Source data (data to be copied into flash) is located in external RAM from address 051000h (to 051FFEh, implicitly) : ; code shown below assumes that flash is mapped in segment 1 ; le. bit ROMS1 = 1 in SYSCON register ; Flash must be enabled, ie. bit ROMEN = *1 in SYSCON. MOV RO, #0AA50h ; AASxh : Multi Word programming command OR RO, #01h ; Selects segment 1 in Flash memory MOV Rl, #09000h ; First Flash Segment Offset Address MOV R2, #09FFEh ; Last Flash Segment Offset Address MOV R3, #09000h ; Source data address: use DPP2 as ; data page pointer SCXT DPP2,#20d ; Source is in page 20 (first page of ; segment 5): save previous DPP2 value ; and load it with source page number MOV R4, #050d ; 50ns is 20MHz CPU clock frequency MOV R7, #08000h ; R7 used for Flash trigger sequence #define FCR 08000h EXTS #1, #2 ; Flash can be mapped in segment 0 or 1 MOV FCR, R7 ; first part MOV [R7], R7 7 second part NOP ; WARNING: place 2 NOP operations after NOP ; the Unlock sequence to avoid all possible j pipeline conflicts in STEAK programs POP DPP2 7; restore DPP2 4] 17/75ST10F168 V - FLASH MEMORY (continued) V.3 - Flash memory configuration The default memory configuration of the ST10F168 Memory is determined by the state of the EA pin at reset. This value is stored in the Internal ROM Enable _ bit ROMEN of the SYSCON Register. When ROMEN = 0, the internal FLASH is disabled and external ROM is used for startup control. Flash memory can be enabled later by setting the ROMEN bit of SYSCON to 1. Ensure that the code which performs this setting is NOT running from external ROM in a segment that will be replaced by FLASH memory, otherwise unex- pected behaviour may occur. For example, if the external ROM code is located in the first 32K Byte of segment 0, the first 32K Byte of the FLASH must then be enabled in segment 1. This is done by setting the ROMS1 bit of SYSCON to 0, before or simultaneously with setting the ROMEN bit. This must be done in the externally supplied program, before the execution of the EINIT instruction. If program execution starts from external memory, but the Flash memory mapped in segment 0 is accessed later, then the code that sets the ROMEN bit must be executed either in segment 0 but above address 008000h, or from the internal RAM. Bit ROMS1 only affects the mapping of the first 32K Byte of the Flash memory. All other parts of the Flash memory (addresses 018000h_ - 04FFFFh) remain unaffected. Note: The SGTDIS Segmentation Disable / Enable must also be set to 0 to enable the use of the full 256K Byte of on-chip memory in addition to the external boot memory. The correct proce- dure for changing the segmentation registers must be observed to prevent an unwanted trap condition : Instructions that configure the internal memory must only be executed from external memory or from the internal RAM. An Absolute Inter-Segment Jump (JMPS) instruction must be executed after Flash enabling, before the next instruction, even if the next instruction is located in the consecutive address. Whenever the internal memory is disabled, ena- bled or remapped, the DPPs must be explicitly (re)loaded to enable correct data accesses to the internal memory and / or external memory. 18/75 V.4 - Flash protection If Flash Protection is active, data operands in the on-chip Flash Memory area can only be read by a program executed from the Flash Memory itself. Program branches from or into the on-chip Flash memory are possible in the Flash protection mode. Erasing and programming of the Flash memory is not possible as long as protection is active. Flash protection is controlled by the Protection UPROM Programming Bit (UPROG). UPROG is a hidden one-time programmable bit only accessi- ble in a special mode which can be entered via a Flash EPROM programming board for example. If UPROG is set to 1, Flash protection is active after reset. By default Flash Protection is disabled (UPROG=0). When flash protection is active (the default after reset if UPROG bit is set), then any read access in the flash by a code executed from external or internal RAM (IRAM or XRAM) will return the value OB88Bh. Any call of STEAK will return the error code 01 (Protected flash). Normally Flash protection should never be deacti- vated, once activated. If this has to be done, for example because the Flash memory has to be reprogrammed with updated program / variables, a zero value has to be written at any even address in the active address space of the Flash memory. This write can be done only by an instruction exe- cuted from the internal Flash Memory itself. For example: MOV FLASH, ZEROS ; Deactivate Flash Protection. ; Flash is any even address in Flash memory space. This instruction MUST be executed from Flash memory itself. After this instruction, the flash is temporarily de-protected, thus any read access of the flash from code executed from external memory or internal RAMs will be correctly executed, and calls of STEAK can be correctly performed (program- ming, erasing or status reading). Notes 1. That all STEAK commands re-activate the flash protection if bit UPROG is set when completed. 2. Currently the only way to program the UPROG one-time programmable bit is by using an external ST10F167 / ST10F168 EPB kit. iyST10F168 VI - CENTRAL PROCESSING UNIT (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedi- cated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F168s instructions can be exe- cuted in one instruction cycle which requires 80ns at 25MHz CPU clock. For example, shift and rotate instructions are processed in one instruc- tion cycle independent of the number of bit to be shifted. Multiple-cycle instructions have been opti- mized: branches are carried out in 2 cycles, 16 x 16-bit multiplication in 5 cycles and a 32/16 bit division in 10 cycles. The jump cache reduces the execution time of repeatedly performed jumps ina loop, from 2 cycles to 1 cycle. Figure 5 : CPU Block Diagram The CPU uses a bank of 16 word registers to run the current context. This bank of General Purpose Registers (GPR) is physically stored within the on-chip RAM area. A Context Pointer (CP) regis- ter determines the base address of the active reg- ister bank to be accessed by the CPU. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, one register bank may overlap others. A system stack of up to 2048 Byte stores tempo- rary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly com- pared against the stack pointer value on each stack access, for the detection of a stack overflow or underflow. Internal CPU RAM SP MDH RIS 2k Byte STKOV MLD _ aN\ STKUN Mul /Dv-HW] 4 Exec. Unit Bit-Mask Gen] [7 - Bank Instr, Ptr - General \ n 256K Byte Instr. Reg Purpose 4 \ Flash 4 4-Stage ALU RegistersS \ Pipeline a i memory 32 P 16-Bit _ = PSw Barrel-Shift RO Bank SYSCON ~ i cP - ~ Jj USCON 0 BUSCON 1 ADDRSEL 1 16 USCON 2 ADDRSEL 2 BUSCON 3 ADDRSEL 3 a Bank BUSCON 4 ADDRSEL 4 16 0 Data Pg. Pirs |[ Code Seg. Ptr. | ar 4] 19/75ST10F168 VI - CENTRAL PROCESSING UNIT (CPU) (continued) VI.1 - Instruction Set Summary The table below lists the ST10F168. The various addressing modes, instruction operation, parameters for conditional instructions of the ST10 Family Programming Manual. Table 8 : Instruction set summary execution of instructions, opcodes and a detailed description of each instruction can be found in the Mnemonic Description Bytes ADD(B) Add Word (Byte) operands 2/4 ADDC(B) Add Word (Byte) operands with Carry 2/4 SUB(B) Subtract Word (Byte) operands 2/4 SUBC(B) Subtract Word (Byte) operands with Carry 2/4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16 x 16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16 / 16-bit) 2 DIVL(U) (Un)Signed long divide register MD by direct GPR (82 / 16-bit) 2 CPL(B) Complement direct Word (Byte) GPR 2 NEG(B) Negate direct Word (Byte) GPR 2 AND(B) Bitwise AND, (Word / Byte operands) 2/4 OR(B) Bitwise OR, (Word / Byte operands) 2/4 XOR(B) Bitwise XOR, (Word / Byte operands) 2/4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR_ | AND /OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high /low Byte of bit-addressable direct Word memory with 4 immediate data CMP(B) Compare Word (Byte) operands 2/4 CMPD1/2 Compare Word data to GPR and decrement GPR by 1/2 2/4 CMPI1/2 Compare Word data to GPR and increment GPR by 1/2 2/4 PRIOR Determine number of shift cycles to normalize direct Word GPR and store result in 2 direct Word GPR SHL/SHR Shift left / right direct Word GPR 2 ROL/ROR Rotate left / right direct Word GPR 2 ASHR Arithmetic (sign bit) shift right direct Word GPR 2 MOV(B) Move Word (Byte) data 2/4 MOVBS Move Byte operand to Word operand with sign extension 2/4 MOVBZ Move Byte operand to Word operand. with zero extension 2/4 JMPA, JMPI, JMPR Jump absolute / indirect / relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 20/75 4]ST10F168 VI - CENTRAL PROCESSING UNIT (CPU) (continued) Table 8 : Instruction set summary Mnemonic Description Bytes CALLA, CALLI, CALLR | Call absolute / indirect / relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct Word register onto system stack and call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push / pop direct Word register onto / from system stack 2 SCXT Push direct Word register onto system stack and update register with Word operand 4 RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct Word register from system 2 stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIG Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2/4 EXTS(R) Begin EXTended Segment (and Register) sequence 2/4 NOP Null operation 2 iy 21/75ST10F168 Vil - EXTERNAL BUS CONTROLLER All external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four dif- ferent external memory access modes : 16/18/ 20/ 24-bit addresses and 16-bit data, demultiplexed. 16/18/ 20/ 24-bit addresses and 16-bit data, multiplexed. 16/18/ 20/ 24-bit addresses and 8-bit data, multiplexed. 16/18/ 20/ 24-bit addresses and 8-bit data, demultiplexed. In demultiplexed bus modes addresses are output on Porti and data are input / output on Port0O or POL, respectively. In the multiplexed bus modes both addresses and data use Port0 for input / out- put. Timing characteristics of the external bus inter- face (memory cycle time, memory tri-state time, length of ALE and read / write delay) are program- mable giving the choice of a wide range of memo- ries and external peripherals. Up to 4 independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics. These address windows are arranged hierarchically where BUSCOM4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are con- trolled by BUSCONDO. Up to 5 external CS signals (4 windows plus default) can be generated in 22/75 order to save external glue logic. Access to very slow memories is Supported by a Ready function. A HOLD/HLDA protocol is available for bus arbi- tration which shares external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After set- ting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to1 the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1M Byte, 256K Byte or to 64K Byte. Port4 outputs all 8 address lines if an address space of 16M Byte is used, otherwise four, two or no address lines. Chip select timing can be programmed. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines can change with the rising edge of ALE. The active level of the READY pin can be set by bit RDYPOLx in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the win- dow must be terminated with the active level defined by bit RDYPOLx in the associated BUS- CONx register. 4]ST10F168 Vill - INTERRUPT SYSTEM The interrupt response time for internal program execution is from 200ns to 480ns at 25MHz CPU clock. The ST10F168 architecture supports several mechanisms for fast and flexible response to ser- vice requests that can be generated from various sources (internal or external) to the microcontrol- ler. Any of these interrupt requests can be ser- viced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is Suspended and a branch to the interrupt vector table is performed, just one cycle is stolen from the current CPU activity to perform a PEC service. A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. Table 9 : Interrupt sources The ST10F168 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. A interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield is dedicated to each existing interrupt source. Thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. Once starting to be processed by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to ser- vice external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are sup- ported by means of the TRAP instruction in com- bination with an individual trap (interrupt) number. Table 9 shows all the available ST10F168 inter- rupt sources and the corresponding hard- ware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Source of Interrupt or PEC Service Request Requ 3 st Frieg Interrupt vector yur CAPCOM Register 0 CCOIR CCOIE CCOINT 000040h 10h CAPCOM Register 1 CC1IR CCI1IE CCt1INT 000044h 11h CAPCOM Register 2 cc2iR CC2IE CC2INT 000048h 12h CAPCOM Register 3 CC3IR CCS3IE CC3INT 00004Ch 13h CAPCOM Register 4 CC4IR CCA4IE CCA4INT 000050h 14h CAPCOM Register 5 CCS5IR CCSIE CCS5INT 000054h 15h CAPCOM Register 6 CC6IR CC6IE CCB6INT 000058h 16h CAPCOM Register 7 CC7IR CC7IE CC7INT 00005Ch 17h CAPCOM Register 8 CC8IR CC8IE CC8INT 000060h 18h CAPCOM Register 9 CCgIR CCS9IE CCS9INT 000064h 19h CAPCOM Register 10 CC10IR CCI1OlE CC1OINT 000068h 1Ah CAPCOM Register 11 CC11IR CC1IIE CC11INT 00006Ch 1Bh CAPCOM Register 12 Ccc12iR CC12lE CC12INT 000070h 1Ch CAPCOM Register 13 CC13IR CC1ISIE CC13INT 000074h 1Dh CAPCOM Register 14 CC14IR CCI14IE CC14INT 000078h 1Eh CAPCOM Register 15 CC15IR CC15IE CC15INT | 00007Ch 1Fh CAPCOM Register 16 CCi6IR CCI1I6IE CC16INT | 0000C0h 30h CAPCOM Register 17 CC17IR CCI17IE CC17INT | 0000C4h 31h CAPCOM Register 18 CC18IR CC18IE CC18INT | 0000C8h 32h CAPCOM Register 19 CC19IR CCI1I9IE CC1I9SINT | 0000CCh 33h iy 23/75ST10F168 Vill - INTERRUPT SYSTEM (continued) Table 9 : Interrupt sources (continued) Source of Interrupt or PEC Service Request Requ 3 st Frieg Interrupt vector yur CAPCOM Register 20 CC20IR CC20lE CC20INT 0000D0h 34h CAPCOM Register 21 CC21IR CC21IE CC21INT 0000D4h 35h CAPCOM Register 22 CC22IR CC221E CC22INT 0000D8h 36h CAPCOM Register 23 CC23IR CC23IE CC23INT | 0000DCh 37h CAPCOM Register 24 CC24IR CC24lE CC24INT 0000E0h 38h CAPCOM Register 25 CC25IR CC25lE CC25INT 0000E4h 39h CAPCOM Register 26 CC26IR CC26IE CC26INT 0000E8h 3Ah CAPCOM Register 27 CC27IR CC27IE CC27INT | 0000ECh 3Bh CAPCOM Register 28 CC28IR CC28lE CC28INT 0000F0h 3Ch CAPCOM Register 29 CC29IR CC29lE CC29INT 000110h 44h CAPCOM Register 30 CC30IR CCSOIE CC30INT 000114h 45h CAPCOM Register 31 CC31IR CCS3IIE CC31INT 000118h 46h CAPCOM Timer 0 TOIR TOIE TOINT 000080h 20h CAPCOM Timer 1 T1IR TIE TAINT 000084h 2th CAPCOM Timer 7 T7IR T7IE T7INT 0000F4h 3Dh CAPCOM Timer 8 T8IR T8IE T8INT 0000F8h 3Eh GPT1 Timer 2 T2IR T2IE T2INT 000088h 22h GPT1 Timer 3 T3IR TS3IE T3INT 00008Ch 23h GPT1 Timer 4 T4IR T4lE T4INT 000090h 24h GPT2 Timer 5 T5IR T5IE T5INT 000094h 25h GPT2 Timer 6 T6IR T6IE T6INT 000098h 26h GPT2 CAPREL Register CRIR CRIE CRINT 00009Ch 27h A/D Conversion Complete ADCIR ADCIE ADCINT 0000A0h 28h A/D Overrun Error ADEIR ADEIE ADEINT 0000A4h 29h ASCO Transmitter SOTIR SOTIE SOTINT 0000A8h 2Ah ASCO Transmitter Buffer SOTBIR SOTBIE SOTBINT 00011Ch 47h ASCO Receiver SORIR SORIE SORINT 0000ACh 2Bh ASCO Error SOEIR SOEIE SOEINT 0000BOh 2Ch SSC Transmitter SCTIR SCTIE SCTINT 0000B4h 2Dh SSC Receiver SCRIR SCRIE SCRINT 0000B8h 2Eh SSC Error SCEIR SCEIE SCEINT 0000BCh 2Fh PWM Channel 0...3 PWMIR PWMIE PWMINT 0000FCh 3Fh CAN Interface XPOIR XPOIE XPOINT 000100h 40h X-Peripheral Node XP1IR XP 1IE XPAINT 000104h 41h X-Peripheral Node XP2IR XP2IE XP2INT 000108h 42h PLL Unlock XP3IR XPSIE XP3INT 00010Ch 43h Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a stan- dard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the 24/75 trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution. Hardware trap services cannot not be interrupted by standard interrupt or by PEC interrupts. kyST10F168 VII - INTERRUPT SYSTEM (continued) Table 10 shows all of the possible exceptions or error conditions that can arise during run-time : Table 10 : Exceptions or error conditions that can arise during run-time Exception Condition Trap Flag | Trap Vector Vector Location Trap Number | Trap Priority Reset Functions Hardware Reset RESET 000000h 00h Il Software Reset RESET 000000h 00h Il Watchdog Timer Overflow RESET 000000h 00h UI Class A Hardware Traps Non-Maskable Interrupt NMI NMITRAP 000008h 02h I Stack Overflow STKOF | STOTRAP 000010h 04h II Stack Underflow STKUF | STUTRAP 000018h 06h II Class B Hardware Traps Undefined Opcode UNDOPG | BTRAP 000028h OAh | Protected Instruction Fault PRTFLT BTRAP 00'0028h OAh | Illegal Word Operand Access ILLOPA BTRAP 000028h OAh | Illegal Instruction Access ILLINA BTRAP 000028h OAh | Illegal External Bus Access ILLBUS BTRAP 000028h OAh | Reserved [2Ch -3Ch] [OBh OFh] sot ere Traps Any [00'0000h 00'01FCh] | Any [00h - 7Fh]] Current CPU in steps of 4h Priority IX - CAPTURE / COMPARE (CAPCOM) UNIT The ST10F168 has two 16 channel CAPCOM units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 320ns at 25MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture / compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow / under- flow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. In addition, external count inputs for CAPCOM timers TO and T7 allow event scheduling for the capture / com- pare registers relative to external events. iy Each of the two capture / compare register arrays contain 16 dual purpose capture / compare regis- ters, each of which may be individually allocated to either CAPCOM timer TO or T1 (T/or T8, respectively), and programmed for capture or compare functions. Each register has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin (except for CC24...CC27) to indicate the occurrence of a compare event. When a capture / compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the dedicated capture / compare register in response to an _ external event at the corresponding port pin which is associated with this register. In addition, a specific interrupt request for this capture / compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. 25/75ST10F168 IX - CAPTURE/COMPARE (CAPCOM) UNIT (continued) The contents of all the registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture / compare register, spe- cific actions will be taken based on the selected compare mode. Table 11 : Compare Modes The input frequencies f7,, for the timer input selector Txl, are determined as a function of the CPU clock. The timer input frequencies, the reso- lution and the periods which result from the selected pre-scaler option in Txl when using a 25MHz CPU clock are listed in the Table 12. The numbers of the timer periods are based on a reload value of 0000,,. Note that some numbers are rounded to 3 significant figures. Compare Modes Function Mode 0 Interrupt-only compare mode ; several compare interrupts per timer period are possible. Mode 1 Pin toggles on each compare match ; several compare events per timer period are possible. Mode 2 Interrupt-only compare mode ; only one compare interrupt per timer period is generated. Mode 3 Pin set 1 on match; pin reset 0 on compare time overflow ; only one compare event per timer period is generated. Double Register Mode | Two registers operate on one pin; pin toggles on each compare match ; several compare events per timer period are possible. Table 12 : CAPCOM timer input frequencies, resolution and periods Timer Input Selection Txl fepu = 25MHz 000, 001, 010, 011, 100, 101, 1105 111, fopy pre-scaler 8 16 32 64 128 256 512 1024 Input Frequency 3.125MHz | 1.56MHz | 781KHz | 391KHz | 195KHz | 97.7KHz | 48.8KHz | 24.4KHz Resolution 320ns 640ns 1.28Us | 256s | 5.12Us | 10.24Us | 20.48Us | 40.96LIs Period 21.0ms 41.9ms 83.9ms 167ms 336ms 671ms 1.34s 2.68s Table 13 : CAPCOM Channels Pin Assignement Channel cance 0) (1 2 3 4 5 6 7 |8 98 0 "1 12 13 14 45 Name CAPCOM | 1/0 cco cCi cc2 cc3 cCC4 ccC5 CC6 CC7 |ccs' ccs! ccio cco111 CC12 CC13 CC14 CCI5 Port 20 21 22 23 24 25 26 27128 29 210 211 212 213 214 215 PinNumber | 47. 48 49 50 51 52 53 54 | 57 58 59 60 61 62 63 64 CAPCON2 | I/O CC16 CCI17 CC18 CC19 CC20 CC21 CC22 CC23]CC24 CC25 CC26 CC27 CC28 CC29 CC30 CC31 Port 80 81 82 83 84 85 86 87 |1H4 1H5 1H6 1H7 74 75 76 7.7 Pin Number 9 10 011 12 13 14 15 16 | 132 133 134 135 23 24 25 26 Note 7. Input only. 26/75 4]ST10F168 X - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer / counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. X.1- GPT1 Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a pro- grammable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is con- trolled by the gate level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 14 lists the timer input frequencies, resolu- tion and periods for each pre-scaler option at 25MHz CPU clock. This also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode. The count direction (up / down) for each timer is programmable by software or may be altered dynamically by an external signal on a port pin (TXEUD). In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be connected directly to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOPO can be connected to an interrupt input. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow / under- flow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high reso- lution of long duration measurements. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal canbe constantly generated without software intervention. X.2 - GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture / reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a pro- grammable prescaler or with external signals. The count direction (up / down) for each timer is pro- grammable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is sup- ported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow / underflow. Table 14 : GPT1 timer input frequencies, resolution and periods Timer Input Selection T2l / T3l / T4I fepu = 25MHz 000, 001, 010, 011, 100, 101, 1105 111, Pre-scaler Factor 8 16 32 64 128 256 512 1024 Input Frequency 3.125MHz | 1.563MHz | 781.3KHz | 390.6KHz | 195.3KHz | 97.66KHz | 48.83KHz | 24.41KHz Resolution 320ns 640ns 1.28us 2.56us 5.12us 10.24us | 20.48us | 40.96us Period 21.0ms 41.9ms 83.9ms 167ms 336ms 671ms 1.34s 2.68s ky 27/75ST10F168 X - GENERAL PURPOSE TIMER UNIT (continued) The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6EOUT). The overflows / underflows of timer T6 can also be used to clock the CAPCOM timers TO or T1, and to cause a reload from the CAPREL register. The CAPREL register can capture the contents of T5 from an external signal transition on the corresponding port pin (CAPIN), and T5 may be optionally cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated on transitions of GPT1 timer T3 inputs T3IN and / or T3EUD. This is useful when T3 operates in Incremental Interface Mode. Table 15 lists the timer input frequencies, resolu- tion and periods for each pre-scaler option at 25MHz CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode. Table 15 : GPT2 timer input frequencies, resolution and periods Timer Input Selection T5I / T6l fepu = 25MHz 000B 001B 010B 011B 100B 101B 110B 111B Pre-scaler Factor 4 8 16 32 64 128 256 512 Input Frequency 6.25MHz |3.125MHz | 1.563MHz | 781.3KHz | 390.6KHz | 195.3KHz | 97.66KHz | 48.838KHz Resolution 160ns 320ns 640ns 1.28us 2.56us 5.12us 10.24us | 20.48us Period 10.49ms | 21.0ms 41.9ms 83.9ms 167ms 336ms 671ms 1.34s Figure 6 : Block Diagram of GPT1 T2EUD 4U/D > Interrupt CPU Clock . GPT Timer 12 [Request } 2" n=3...107 | T2 aS Ton ( | Mode Reload _.-= Control Capture _ WA [ fN% CPU Clock 12" n=3...10/| 73 J T3OUT T3IN { } ,| Mode >| GPT1 Timer T3 > T3OTLL- +t) he Control oot raeup { } i Ls Capture 14 Reload _, WA Interrupt T4IN ( }__ Mode Request CPU Clock OF a3 Control I >} 2" n=3... > Ly GPT1 Timer T4 Interrupt Request T4eEuD{ UID 28/75 irST10F168 X - GENERAL PURPOSE TIMER UNIT (continued) Figure 7 : Block Diagram of GPT2 T5EUD Lo U/D CPU Clock T5 interrupt Mode GPT2 Timer TS 2 > Request TSIN O {Control Cleart T Capture > Vv 1 | , Interrupt oaPnt V ~ Request GPT2 CAPREL VW Reload , Interrupt ~ Request tein} T6 J Toggle FF i T60TL T6OUT CPU ClooK or na2..9 | Mode GPT2 Timer T6 = be eof 2n n=2... ( } U/D CAPCOM T6EUD to Ll Timers 4] 29/75ST10F168 XI - PWM MODULE The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and sin- gle shot outputs. The Table 16 shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests. Table 16 : PWM unit frequencies and resolution at 25MHz CPU clock Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock / 1 40ns 97.66KHz 24.41KHz 6.104KHz 1.526KHz 0.381KHz CPU Clock / 64 2.56us 1.526KHz 381.5Hz 95.37HzZ 23.84Hz 5.96Hz Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock / 1 40ns 48.82KHz 12.20KHz 3.05KHz 762.9Hz 190.7Hz CPU Clock / 64 2.56us 762.9Hz 190.7Hz 47.68Hz 11.92Hz 2.98Hz Figure 8 : PWM Module Block Diagram PPx Period Register * Clock 1 } PTx Clock 2 pp Input Control 16-Bit Up/Down Counter * Up/Down/ Clear Control * User readable & writeable register Shadow Register PWx Pulse Width Register* Output Control Write Control Enable 30/75 4]ST10F168 XII - PARALLEL PORTS The ST10F168 provides up to 111 I/O lines organized into eight input / output ports and one input port. All port lines are bit-addressable, and all input / output lines are individually (bit-wise) programmable as input or output via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five I/O ports can be configured (pin by pin) for push-pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS-like), where the special CMOS-like input threshold reduces noise sensitivity to the input hysteresis. The input thresholds are selected with bit of PICON register dedicated to blocks of 8 input pins (2-bit for Port2, 2-bit for Port3, 1-bit for Port7, 1-bit for Port8). All pins of I/O ports also support an alternate pro- grammable function: 4] PortO and Port1 may be used as address and data lines when accessing external memory. Port 2, Port 7 and Port 8 are associated with the capture inputs or with the compare outputs of the CAPCOM units and / or with the outputs of the PWM module. Port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 4 outputs the additional segment address bit A16 to A23 in systems where segmentation is enabled to access more than 64K Byte of memory. Port 5 is used as analog input channels of the A/D converter or as timer control signals. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. All port lines that are not used for alternate func- tions may be used as general purpose I/O lines. 31/75ST10F168 XIll - A/D CONVERTER A10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conver- sion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The AD converter of the ST10F168 supports dif- ferent conversion modes : Single channel single conversion : the analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT register. Single channel continuous conversion : the analog level of the selected channel is repeatedly sampled and converted. The result of the conver- sion is stored in the ADDAT register. Auto scan single conversion : the analog level of the selected channels are sampled once and converted. After each conversion the result is stored inthe ADDAT register. The data can be transfered to the RAM by interrupt software management or using the powerfull Peripheral Event Controller data transfert. Auto scan continuous conversion : the ana- log level of the selected channels are repeatedly sampled and converted. The result of the con- version is stored in the ADDAT register. The data can be transfered to the RAM by interrupt software management or using the powerfull Peripheral Event Controller data transfert. Wait for ADDAT read mode : when using con- tinuous modes, in order to avoid to overwrite Table 17 : ADC sample clock and conversion clock the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated. Then, until the ADDAT regis- ter is read, the new result is stored in a tempo- rary buffer and the conversion is on hold. Channel injection mode when using continuous modes, a selected channel can be converted in between without changing the current operating mode. The 10 bit data of the conversion are stored in ADRES field of ADDAT2. The current continuous mode remains active after the single conversion is completed. The Table 17 shows conversion clock and sample clock of the ADC unit. A complete conversion will take 14tc + 2tgc + 4TCL. This time includes the conversion it self, the sampling time and the time required to trans- fer the digital value to the result register. For example at 25MHz of CPU clock, the minimum complete conversion time is 7.76us. The A/D converter provides automatic offset and linearity self calibration. The calibration operation is performed in two ways : A full calibration sequence is performed after a reset and lasts 1.6ms minimum (at 25MHz CPU clock). During this time, the ADBSY flag is set to indicate the operation. Normal conversion can be performed during this time. The duration of the calibration sequence is then extended by the time consumed by the conversions. Note After a power-on reset, the total unadjusted error (TUE) of the ADC might be worse than+2LSB (max.+4LSB). During the full calibration sequence, the TUE is constantly improved until at the end of the cycle, TUE is within the specified limits of t2LSB. One calibration cycle is performed after each conversion : each calibration cycle takes 4 ADC clock cycles. These operation cycles ensure constant updating of the ADC accuracy, com- pensating changing operating conditions. Conversion Clock tec Sample Clock tgc ADCTC ADSTC TCL = 1/2 x fytat At fopy = 25MHz - At fopy = 25MHz 00 TCL x 24 0.48us 00 tec 0.48us2 01 Reserved, do not use - 01 tec X 2 0.96us2 10 TCL x 96 1.92us 10 tec x 4 1.92us? 11 TCL x 48 0.96us 11 tec X 8 3.84us? Notes 1. See chapter XX. 2. tog = TCL x 24. 32/75 4]ST10F168 XIV - SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral com- ponents is provided by two serial interfaces: the asynchronous / synchronous serial channel (ASCO) and the high-speed synchronous serial channel (SSC). Two dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning. For transmission, reception and erroneous reception, 3 separate interrupt vectors are provided for each serial channel. ASCO ASCO supports full-duplex asynchronous com- munication at up to 781.25K Baud and half-duplex synchronous communication up to 5M Baud at 25MHz system clock. For asynchronous operation, the Baud rate gener- ator provides a clock with 16 times the rate of the established Baud rate. Table 18 lists various commonly used Baud rates together with the required reload values and the deviation errors compared to the _ intended Baud rate. For synchronous operation, the Baud rate genera- tor provides a clock with 4 times the rate of the established Baud rate. Table 18 : Commonly used Baud rates by reload value and deviation errors SOBRS = 0, fepy = 25MHz SOBRS = 1, fcpy = 25MHz Baud Rate (Baud) | Deviation Error | Reload Value Baud Rate (Baud) | Deviation Error | Reload Value 781250 +0.0% 0000, 520833 +0.0% 0000, 56000 +7.3% /-0.4% 000C,, / 000DY 56000 +3.3% / -7.0% 0008}, /0009,, 38400 +1.7% /-3.1% 0013,,/0014,, 38400 +4.3% / -3.1% 000C,, /000D}, 19200 +1.7% /-0.8% 0027, / 0028, 19200 +0.5% / -3.1% 001A}y /001By 9600 +0.5% /-0.8% 0050,,/ 0051, 9600 +0.5% / -1.4% 0035}, / 0036, 4800 +0.5% /-0.1% 00A1,,/00A2,, 4800 +0.5% / -0.5% 006B,, / 006C}, 2400 +0.2% /-0.1% 0144,,/0145,, 2400 +0.0% / -0.5% 00D8}, /00D9}, 1200 +0.0% /-0.1% 028A}, / 028By 1200 +0.0% / -0.2% 01B1,y/01B2, 600 +0.0% /-0.1% 0515,,/0516,, 600 +0.0% / -0.1% 0363}, / 0364, 95 +0.4% 1FFFY/1FFFY 75 +0.0% / 0.0% 1B1Fy,/1B20, 63 +0.9% 1FFFY /1FFFY 4] 33/75ST10F168 XIV - SERIAL CHANNELS (continued) High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible high-speed _ serial communication between the ST10F168 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and _ half-duplex synchronous communication; The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPl-compatible devices. Transmission and reception of data is Table 19 : Synchronous Baud rate and reload values double-buffered. A 16-bit Baud rate generator pro- vides the SSC with a separate serial clock signal. The serial channel SSC has its own dedicated 16-bit Baud rate generator with 16-bit reload capability, allowing Baud rate generation indepen- dent from the timers. SSCBR is the dual-function Baud rate Generator / Reload register. Table 19 lists some possible Baud rates against the required reload values and the resulting bit times for a 25MHz CPU clock. Note The deviation errors given in the Table 18 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASCO/SSC sampling frequency). Baud Rate Bit Time Reload Value Reserved use a reload value > 0. 0000,, 5M Baud 200ns 0001 3.3M Baud 303ns 0002, 2.5M Baud 400ns 0004, 2M Baud 500ns 00051, 1M Baud OOOoBy, 100K Baud 007Cy 10K Baud 100s 04E14 1K Baud 30D3 44 190.7 Baud 5.2ms FFFFy 34/75 4]ST10F168 XV - CAN MODULE The integrated CAN module completely handles the autonomous transmission and the reception of CAN frames according to the CAN specification V2.0 part B (active). The on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN Module Provides full CAN functionality on up to 15 message objects. Message object 15 can be configured for basic CAN functionality. Both modes provide separate masks for accep- tance filtering, allowing a number of identifiers in full CAN mode to be accepted and disregarding a number of identifiers in basic CAN mode. All mes- sage objects can be updated independently from other objects and are equipped for the maximum message length of 8 Byte. The bit timing is derived from the XCLK and is pro- grammable up to a data rate of 1M Baud. The CAN module uses two pins to interface to a bus transceiver. XVI - WATCHDOG TIMER The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunc- Table 20 : Watchdog time range (25MHz clock) tioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip start-up pro- cedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an inter- nal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high Byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). Each time it is serviced by the application soft- ware, the high Byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced Table 20 shows the watchdog time range for 25MHz CPU clock. Reload value in WOTREL Prescaler for fopy 2 (WDTIN = 0) 128 (WDTIN = 1) FFy 20.48us 1.31ms 00H 5.24ms 336ms 4] 35/75ST10F168 XVII - SYSTEM RESET Table 21 : Reset event definition Reset Source Short-cut Conditions Power-on reset PONR Power-on Long Hardware reset (asynchronous reset) LHWR trastin > 1032 TCL Short Hardware reset (synchronous reset) SHWR 4 TCL <t pasting 1032 TCL Watchdog Timer reset WDTR WDT overflow Software reset SWR SRST execution System reset initializes the MCU in a predefined state. There are five ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 21. XVIL1 - Asynchronous reset (Long Hardware Reset) An asynchronous reset is triggered when RSTIN pin is pulled low while Vpp pin is at low level. Then the MCU is immediately forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it waits for any internal access cycles to finish, it aborts external bus cycle, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high PortO pins and the reset sequence starts. Power-on reset The asynchronous reset must be used during the power-on of the MCU. Depending on crystal fre- quency, the on-chip oscillator needs about 10ms to 50ms to stabilize. The logic of the MCU does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on Figure 9 : Asynchronous Reset Timing conditions. To ensure a proper reset sequence, the RSTIN pin and the Vpp pin must be held at low level until the MCU clock signal is stabilized and the system configuration value on Port0 is settled. Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggerred by the hardware of the applica- tion. Internal hardware logic and application cir- cuitry are described in Reset circuitry chapter and Figures 12, 13 and 14. Exit of asynchrounous reset state When the RSTIN pin is pulled high, the MCU restarts. The system configuration is latched from PortO and ALE, RD and R/W pins are driven to their inactive level. The MCU starts program exe- cution from memory location 000000h in code seg- ment 0. This starting location will typically point to the general initialization routine. Timing of asyn- chronous reset sequence are summarized in Figure 9. 3or 4 CPU Clock! > CPU Clock | | | il | | | | ULL LLL LLL] 1 2 \\ | +> | Asynchronous Reset Condition | \ f ALE Porto yy Reset Configuration | Internal Reset / / / Signal # atching point of Porto | | for systemstart-up configuration | | | 36/75 vfST10F168 XVII - SYSTEM RESET (continued) Note 1. RSTIN rising edge to internal latch of PortO is 3CPU clock cycles if the PLL is bypassed and the prescaler is on (f cpy =f xta /2), else it is 4 CPU clock cycles. XVII.2 - Synchronous reset (Warm Reset) A synchronous reset is triggered when RSTIN pin is pulled low while Vpp pin is at high level. In order to properly activate the internal reset logic of the MCU, the RSTIN pin must be held low, at least, during 4 TCL (2 periods of CPU clock). The I/O pins are set to high impedance and RSTOUT pin is driven low. After RSTIN level is detected, a short duration of 12 TCL (approximately 6 periods of CPU clock) elapes, during which pending internal hold states are cancelled and the current internal access cycle if any is completed. External bus cycle is aborted. The internal pulldown of RSTIN pin is activated if bit BDRSTEN of SYSCON reg- ister was previously set by software. This bit is always cleared on power-on or after a reset sequence. Exit of synchrounous reset state The internal reset sequence starts for 1024 TCL (512 periods of CPU clock) and RSTIN pin level is sampled. The reset sequence is extended until RSTIN level becomes high. Then, the MCU restarts. The system configuration is latched from PortO0 and ALE, RD and RW pins are driven to their inactive level. The MCU starts program exe- cution from memory location 000000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of synchronous reset sequence are summarized in Figure 10 and 11. Figure 10 : Synchronous Warm Reset: Short low pulse on RSTIN 4TCL 12TCL +4 od 1024 TCL 6 or 8TCL? rem Nf Vpp 1 ee I 200uA Discharge (v \ Internally pulled low* | | ___+_ tr] 2 Vpp > 2.5V Asynchronous Reset not entereh. | | { | , iz | | T PortO JH \ Reset Configuration ' Latching point of Polo | for system start up qentiguration | | Internal HF Reset | | | | Signal Notes 1. RSTINassertion can be released there. 2. If during the reset condition (RSTIN low), Vpp voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. RSTINrising edge to internal latch of PortO is 3CPU clock cycles ifthe PLL is bypassed and the prescaler is on (fopy = itis 4 CPU clock cycles. fyTaL else 4) RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SUSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. If a synchronous reset is used as a power-up reset in place of an asynchronous reset, note that the behaviour of RSTIN (ie. pulled low or not during 1024 TCL) is undetermined. This should be not a problem, because in such power-up reset, the pin RSTIN must be maintained to 0 at least during two reset sequences (2"1024 TCL, 40.96us at 25MHz CPU clock). 4] 37/75ST10F168 XVII - SYSTEM RESET (continued) Figure 11 : Synchronous Warm Reset: Long low pulse on RSTIN <> TCL 1 ee 1024 TCL ws or 8 TCL! RSTIN | Internally pulled low? J PortO WH Reset Configuration ) | Latching point of Portd | forsystem stqrt-up Comfiguration | Internal tf Reset | | | | Signal Notes 1. RSTIN rising edge to internal latch of PortO is 3CPU clock cycles if the PLL is bypassed and the prescaler ison (fcpy = fyxta / 2), else it is 4 CPU clock cycles. 2. If during the reset condition (RSTIN low), Vpp voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. RSTINpin is pulled low if bit BDRSTEN (bit 5 of SYSCON register) was previously set by soft-ware. Bit BDRSTEN is cleared after reset. If a synchronous reset is used as a power-up reset in place of an asynchronous reset, note that the behaviour of RSTIN (ie. pulled low or not during 1024 TCL) is undetermined. This should be not a problem, because in such power-up reset, the pin RSTIN must be maintained to 0 at least during two reset sequences (2"1024 TCL, 40.96us at 25MHz CPU clock). XVII.3 - Software Reset A software reset sequence can be triggered at any time by the protected SRST (software reset) instruction. This instruction can be deliberately executed within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals system failure. On execution of the SRST instruction, the internal reset sequence is started. The microcontroller behaviour is the same as for a synchronous reset, except that only bit P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bit PO.7...P0.2 are cleared. XVIL4 - Watchdog Timer Reset When the watchdog timer is not disabled during the initialization, or serviced regularly during pro- gram execution, it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watch- dog reset completes a running external bus cycle if this bus cycle either does not use READY, or if 38/75 READY is sampled active (low) after the pro- grammed wait states. When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence is started. Bit PO.12...P0.8 are latched at the end of the reset sequence and bit PO.7...P0.2 are cleared. XVII.5 - Reset Circuitry Internal reset circuitry is described in Figure 13. The RSTIN pin provides an internal pullup resistor of 50KQ to 250KQ (The minimum reset time must be calculated using the lowest value). It also provides a programmable (BDRSTEN bit of SYSCON register) pulldown to output internal reset state signal (synchronous reset, watchdog timer reset or software reset). This bidirectional reset function is useful in appli- cations where external devices require a reset signal but cannot be connected to RSTOUT pin. iyST10F168 XVII - SYSTEM RESET (continued) This is the case of an external memory running codes before EINIT ( end of initialization) instruc- tion is executed. RSTOUT pin is pulled high only when EINIT is executed. The Vpp pin provides an internal weak pulldown resistor which discharges external capacitor at a typical rate of 200A. If bit PWDCFG of SYSCON register is set, an internal pullup resistor is activated at the end of the reset sequence. This pullup will charge any capacitor connected on Vpp pin. The simplest way to reset the ST10F168 is to insert a capacitor C1 between RSTIN pin and Vgg, and a capacitor between Vpp pin and Vgg (CO) with a pullup resistor RO between Vpp pin and Vec. The input RSTIN provides an internal pullup device equalling a resistor of 50kQ to 150kQ (the minimum reset time must be determined by the lowest value). Select C1 that produce a sufficient discharge time to permit the internal or external oscillator and /or internal PLL to stabilize. To insure correct power-up reset with controlled supply current consumption, specially if clock sig- nal requires a long period of time to stabilized, an asynchronous hardware reset is required during power-up. It is recommended to connect the external ROCO circuit shown in Figure 12 to the Vpp pin. On power-up, the logical low level on Vpp pin forces an asynchronous harware reset when RSTIN is asserted. The external pullup RO will then charge the capac- itor CO. Note that an internal pulldown device on Vpp pin is turned on when RSTIN pin is low, and 4] causes the external capacitor (CO) to begin dis- charging at a typical rate of 100A to 200nA. With this mechanism, after power-up reset, short low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted longer than the time needed for CO to be discharged by the internal pulldown device, then the device is forced in an asynchronous reset. This mechanism insures recovery from very catastrophic failure. Figure 12 : Minimum External Reset Circuitry RSTOUT -___ External Hardware RSTIN 7 Ct @_ a) Hardware L Reset 1 5 eo RO b) For Power-up Reset (and Interruptible Vpp Power-down mode) Voc co ST10F168 SHE 39/75ST10F168 XVII - SYSTEM RESET (continued) Figure 13 : Internal (simplified) Reset Circuitry EINIT Instruction . Clr Reset State Machine Clock | V Clr Reset Sequence Q ): 7 RSTOUT Set we, . SRST instruction Trigger watchdog overflow TY RSTIN BDRSTEN (512 CPU Clock Cydes) From/o Exit Powerdown Circuit Asynchronous Reset { YP Vpp (Flash device) =) ) Vpp Weak Pulldown (~200,1A) fo The minimum reset circuit of Figure 14 is not ade- quate when the RSTIN pin is driven from the ST10F 168 itself during software or watchdog trig- gered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above Vj, after the end of the internal reset sequence, and thus will triggered an asynchronous reset sequence. Figure 14 shows an example of a reset circuit. In this example, R1C1 external circuit is only used to 40/75 generate power-up or manual reset, and ROCO circuit On Vpp is used for power-up reset and to exit from powerdown mode. Diode D1 creates a wired-OR gate connection to the reset pin and may be replaced by open-collector schmitt trigger buffer. Diode D2 provides a faster cycle time for repetitive power-on resets. R2 is an optional pullup for faster recovery and correct biasing of TTL Open Collector drivers. 4]ST10F168 XVII - SYSTEM RESET (continued) Figure 14 : System Reset Circuit RSTOUT Vpp ST10F168 Voc R2 External Hardware External Reset Source 4] 41/75ST10F168 XVIII - POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. In Power Down mode both the CPU and the peripherals are stopped. Power Down mode can be configured by software in order to be termi- nated only by a hardware reset or by an external interrupt source on fast external interrupt pins. There are two different operating Power Down modes: Protected power down mode: selected by set- ting bit PWDCFG in the SYSCON register to 0. This mode can be used in conjunction with_an external power failure signal which pulls the NMI pin low when a power failure is imminent. The microcontroller enters the NMI trap routine and saves the internal state into RAM. The trap rou- tine then sets a flag or writes a bit pattern into specific RAM locations, and executes the PWRDN instruction. If the NMI pin is still low at this time, Power Down mode will be entered, if not program execution continues. During power 42/75 down the voltage at the Vcc pins can be lowered to 2.5 V and the contents of the internal RAM will stillbe preserved. Interruptible power down mode: this mode is selected by setting bit PWDCFG in the SYSCON register. The CPU and peripheral clocks are frozen, and the oscillator and PLL are stopped. To exit power down mode with an ex- ternal interrupt, an EXxIN (x = 7...0) pin has to be asserted for at least 40ns. This signal ena- bles the internal oscillator and PLL circuitry, and turns on the weak pulldown. If the Interrupt was enabled before entering power down mode, the device executes the interrupt service routine, and then resumes execution after the PWRDN instruction. If the interrupt was disabled, the de- vice executes the instruction following PWRDN instruction, and the Interrupt Request Flag re- mains set until it is cleared by software. All external bus actions are completed before Idle or Power Down mode is entered. However, Idle or Power Down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access. 4]ST10F168 XIX - SPECIAL FUNCTION REGISTER OVERVIEW Table 22 lists all SFRs which are implemented An SFR can be specified by its individual mnemonic in the ST10F 168 in alphabetical order. name. Depending on the selected addressing Bit-addressable SFRs are marked with the letter mode, an SFR can be accessed via its physical b in column Name. SFRs within the Extended address (using the Data Page Pointers), or via its SFR-Space (ESFRs) are marked with the letter short 8-bit address (without using the Data Page E in column Physical Address. Pointers). Table 22 : Special Function Registers listed by name Name | adress | address Description value ADCIC b |FF98h CCh_ {A/D Converter End Of Conversion Interrupt Control Register 0000h ADCON b |FFAOh DOh_ {A/D Converter Control Register 0000h ADDAT FEAOh 50h A/D Converter Result Register 0000h ADDAT2 FOAOh E 50h A/D Converter 2 Result Register 0000h ADDRSEL1 FE18h OCh_ |Address Select Register 1 0000h ADDRSEL2 FE1Ah ODh_ | Address Select Register 2 0000h ADDRSEL3 FE1Ch OEh_ |Address Select Register 3 0000h ADDRSEL4 FE1Eh OFh |Address Select Register 4 0000h ADEIC b |FF9Ah CDh_ {A/D converter Overrun Error Interrupt Control Register 0000h BUSCONO b_ |FFOCh 86h Bus Configuration Register 0 OXXOh BUSCON1 b= |FF14h 8Ah Bus Configuration Register 1 0000h BUSCON2 b_ |FF16h 8Bh Bus Configuration Register 2 0000h BUSCON3 b |FF18h 8Ch Bus Configuration Register 3 0000h BUSCON4 b_ |FF1Ah 8Dh Bus Configuration Register 4 0000h CAPREL FE4Ah 25h GPT2 Capture / Reload Register 0000h cco FE80h 40h |CAPCOM Register 0 0000h ccolc b |FF78h BCh |CAPCOM Register 0 Interrupt Control Register 0000h CcC1 FE82h 41h |CAPCOM Register 1 0000h CC1IC b |FF7Ah BDh |CAPCOM Register 1 Interrupt Control Register 0000h CC2 FE84h 42h |CAPCOM Register 2 0000h cc2ic b |FF7Ch BEh |CAPCOM Register 2 Interrupt Control Register 0000h CC3 FE86h 43h |CAPCOM Register 3 0000h CC3IC b |FF7Eh BFh |CAPCOM Register 3 Interrupt Control Register 0000h Cc4 FE88h 44h |CAPCOM Register 4 0000h Ccc4ic b |FF80h COh |CAPCOM Register 4 Interrupt Control Register 0000h CC5 FE8Ah 45h |CAPCOM Register 5 0000h CCc5IC b |FF82h Cih |CAPCOM Register 5 Interrupt Control Register 0000h CC6 FE8Ch 46h |CAPCOM Register 6 0000h Ccc6|lc b |FF84h C2h |CAPCOM Register 6 Interrupt Control Register 0000h CC7 FE8Eh 47h |CAPCOM Register 7 0000h Ccc7IC b |FF86h C3h |CAPCOM Register 7 Interrupt Control Register 0000h Ccc8 FE90h 48h |CAPCOM Register 8 0000h Ccsic b |FF88h C4h_ |CAPCOM Register 8 Interrupt Control Register 0000h iy 43/75ST10F168 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 22 : Special Function Registers listed by name Name Physical 8-bit Description Reset address address value ccg FE92h 49h CAPCOM Register 9 0000h ccgic FF8Ah C5h_ |CAPCOM Register 9 Interrupt Control Register 0000h CC10 FE94h 4Ah |CAPCOM Register 10 0000h CC10IC FF8Ch C6h |CAPCOM Register 10 Interrupt Control Register 0000h CC11 FE96h 4Bh |CAPCOM Register 11 0000h CC11IC FF8Eh C7h |CAPCOM Register 11 Interrupt Control Register 0000h CC12 FE98h 4Ch |CAPCOM Register 12 0000h cC12IC FF90h C8h |CAPCOM Register 12 Interrupt Control Register 0000h CC13 FE9Ah 4Dh |CAPCOM Register 13 0000h CC13IC FF92h C9h_ |CAPCOM Register 13 Interrupt Control Register 0000h cc14 FE9Ch 4Eh |CAPCOM Register 14 0000h CC14IC FF94h CAh |CAPCOM Register 14 Interrupt Control Register 0000h CC15 FE9Eh 4Fh |CAPCOM Register 15 0000h CC15IC FF96h CBh |CAPCOM Register 15 Interrupt Control Register 0000h CC16 FE60h 30h CAPCOM Register 16 0000h CC16IC F160h E Boh CAPCOM Register 16 Interrupt Control Register 0000h CC17 FE62h 31h CAPCOM Register 17 0000h CC17IC F162h E Bih CAPCOM Register 17 Interrupt Control Register 0000h CC18 FE64h 32h CAPCOM Register 18 0000h CC18IC F164h E B2h CAPCOM Register 18 Interrupt Control Register 0000h CC19 FE66h 33h CAPCOM Register 19 0000h CC19IC F166h E B3h CAPCOM Register 19 Interrupt Control Register 0000h CC20 FE68h 34h CAPCOM Register 20 0000h CC20IC F168h E B4h CAPCOM Register 20 Interrupt Control Register 0000h cc21 FE6Ah 35h CAPCOM Register 21 0000h CC21IC F16Ah E B5h CAPCOM Register 21 Interrupt Control Register 0000h CC22 FE6Ch 36h CAPCOM Register 22 0000h CC221IC F16Ch E B6h CAPCOM Register 22 Interrupt Control Register 0000h CC23 FE6Eh 37h CAPCOM Register 23 0000h CC23IC F16Eh E B7h CAPCOM Register 23 Interrupt Control Register 0000h CC24 FE70h 38h CAPCOM Register 24 0000h CC24IC F170h E B8h CAPCOM Register 24 Interrupt Control Register 0000h CC25 FE72h 39h CAPCOM Register 25 0000h CC25IC F172h E B9h CAPCOM Register 25 Interrupt Control Register 0000h CC26 FE74h 38Ah |CAPCOM Register 26 0000h CC261IC F174h E BAh |CAPCOM Register 26 Interrupt Control Register 0000h CC27 FE76h 38Bh |CAPCOM Register 27 0000h CC27IC F176h E BBh |CAPCOM Register 27 Interrupt Control Register 0000h 44/75 iyST10F168 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 22 : Special Function Registers listed by name Name Physical 8-bit Description Reset address address value CC28 FE78h 3Ch |CAPCOM Register 28 0000h CC28IC b |F178h E BCh |CAPCOM Register 28 Interrupt Control Register 0000h CC29 FE7Ah 3Dh |CAPCOM Register 29 0000h Ccc2gic b |F184h E C2h |CAPCOM Register 29 Interrupt Control Register 0000h CC30 FE7Ch 38Eh |CAPCOM Register 30 0000h CC30IC b |F18Ch E C6h |CAPCOM Register 30 Interrupt Control Register 0000h CC31 FE7Eh 3Fh |CAPCOM Register 31 0000h CC31IC b |F194h E CAh |CAPCOM Register 31 Interrupt Control Register 0000h CCMO b |FF52h AQh CAPCOM Mode Control Register 0 0000h CCM1 b |FF54h AAh |CAPCOM Mode Control Register 1 0000h CCM2 b |FF56h ABh |CAPCOM Mode Control Register 2 0000h CCM3 b |FF58h ACh |CAPCOM Mode Control Register 3 0000h CCM4 b |FF22h 9ih CAPCOM Mode Control Register 4 0000h CCM5 b |FF24h 92h CAPCOM Mode Control Register 5 0000h CCM6 b |FF26h 93h CAPCOM Mode Control Register 6 0000h CCM7 b |FF28h 94h CAPCOM Mode Control Register 7 0000h cP FE10h 08h CPU Context Pointer Register FCoOoh CRIC b |FF6Ah B5h GPT2 CAPREL Interrupt Control Register 0000h CSP FEO8h 04h CPU Code Segment Pointer Register (read only) 0000h DPOL b |F100h E 80h POL Direction Control Register 00h DPOH b |F102h E 81h POh Direction Control Register 00h DP1L b |F104h E 82h P1L Direction Control Register 00h DP1H b |F106h E 83h Ph Direction Control Register 00h DP2 b |FFC2h Eth Port 2 Direction Control Register 0000h DP3 b |FFC6h E8h Port 3 Direction Control Register 0000h DP4 b |FFCAh E5h Port 4 Direction Control Register 00h DP6 b |FFCEh E7h Port 6 Direction Control Register 00h DP7 b |FFD2h E9h Port 7 Direction Control Register 00h DP8 b |FFD6h EBh_ |Port 8 Direction Control Register 00h DPPO FEOOh 00h CPU Data Page Pointer 0 Register (10-bit) 0000h DPP1 FE02h Oth CPU Data Page Pointer 1 Register (10-bit) 0001h DPP2 FE04h 02h CPU Data Page Pointer 2 Register (10-bit) 0002h DPP3 FEO6h 03h CPU Data Page Pointer 3 Register (10-bit) 0003h EXICON b |F1COh E E0h External Interrupt Control Register 0000h IDCHIP FO7Ch E 3Eh | Device Identifier Register OA8Xh!1 IDMANUF FO7Eh E 3Fh Manufacturer Identifier Register 0400h IDMEM FO7Ah E 3Dh = |On-chip Memory Identifier Register 3040h IDPROG FO78h E 3Ch Programming Voltage Identifier Register 9A40h iy 45/75ST10F168 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 22 : Special Function Registers listed by name Name Physical 8-bit Description Reset address address value MDC b |FFOEh 87h CPU Multiply Divide Control Register 0000h MDH FEOCh 06h CPU Multiply Divide Register High Word 0000h MDL FEOEh 07h CPU Multiply Divide Register - Low Word 0000h ODP2 b |F1C2h E Eth Port 2 Open Drain Control Register 0000h ODP3 b |F1iC6h E E8h Port 3 Open Drain Control Register 0000h ODP6 b |F1CEh E E7h Port 6 Open Drain Control Register 00h ODP7 b |F1D2h E E9h Port 7 Open Drain Control Register 00h ODP8 b |F1D6h E EBh_ |Port 8 Open Drain Control Register 00h ONES FF1Eh 8Fh Constant Value 1s Register (read only) FFFFh POL b |FFOOh 80h Port 0 Low Register (Lower half of PortO) 00h POH b |FFO2h 81h Port 0 High Register (Upper half of Port) 00h PIL b |FFO4h 82h Port 1 Low Register (Lower half of Port1) 00h P1H b |FFO6h 83h Port 1 High Register (Upper half of Port1) 00h P2 b |FFCOh E0h Port 2 Register 0000h P3 b |FFC4h E2h Port 3 Register 0000h P4 b |FFC8h E4h_ | Port 4 Register (8-bit) 00h P5 b | FFA2h Dih Port 5 Register (read only) XXXXh P6 b |FFCCh E6h_ | Port 6 Register (8-bit) 00h P7 b |FFDOh E8h_ |Port 7 Register (8-bit) 00h P8 b |FFD4h EAh_ |Port 8 Register (8-bit) 00h PECCO FECOh 60h PEC Channel 0 Control Register 0000h PECC1 FEC2h 6th PEC Channel 1 Control Register 0000h PECCG2 FEC4h 62h PEC Channel 2 Control Register 0000h PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h PECCS5 FECAh 65h PEC Channel 5 Control Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECCG7 FECEh 67h PEC Channel 7 Control Register 0000h PICON F1C4h E E2h Port Input Threshold Control Register 0000h PPO FO38h E 1Ch PWM Module Period Register 0 0000h PP1 FO3Ah E 1Dh PWM Module Period Register 1 0000h PP2 FO3Ch E 1Eh PWM Module Period Register 2 0000h PP3 FO3Eh E 1Fh PWM Module Period Register 3 0000h PSW b |FF10h 88h CPU Program Status Word 0000h PTO FO30h E 18h PWM Module Up / Down Counter 0 0000h PT1 FO32h E 19h PWM Module Up / Down Counter 1 0000h PT2 FO34h E 1Ah PWM Module Up / Down Counter 2 0000h PT3 FO36h E 1Bh PWM Module Up / Down Counter 3 0000h 46/75 iyST10F168 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 22 : Special Function Registers listed by name Name Physical 8-bit Description Reset address address value PWO FE30h 18h PWM Module Pulse Width Register 0 0000h PW1 FE32h 19h PWM Module Pulse Width Register 1 0000h PWe2 FE34h 1Ah PWM Module Pulse Width Register 2 0000h PWS3 FE36h 1Bh PWM Module Pulse Width Register 3 0000h PWMCONO b_ |FF30h 98h PWM Module Control Register 0 0000h PWMCON1 b= |FF32h 99h PWM Module Control Register 1 0000h PWMIG b |F17Eh E BFh PWM Module Interrupt Control Register 0000h RPOH b |F108h E 84h System Start-up Configuration Register (read only) XXh SOBG FEB4h 5Ah _ |Serial Channel 0 Baud Rate Generator Reload Register 0000h SOCON b |FFBOh D8h_ |Serial Channel 0 Control Register 0000h SOEIC b |FF70h B8h_ | Serial Channel 0 Error Interrupt Control Register 0000h SORBUF FEB2h 59h Serial Channel 0 Receive Buffer Register (read only) XXh SORIC b |FF6Eh B7h_ |Serial Channel 0 Receive Interrupt Control Register 0000h SOTBIC b |F1i9Ch E CEh_ {Serial Channel 0 Transmit Buffer Interrupt Control Register 0000h SOTBUF FEBOoh 58h Serial Channel 0 Transmit Buffer Register (write only) 00h SOTIC b |FF6Ch B6h_ {Serial Channel 0 Transmit Interrupt Control Register 0000h SP FE12h 09h CPU System Stack Pointer Register FCoOoh SSCBR FOB4h E 5Ah |SSC Baud Rate Register 0000h SSCCON b |FFB2h D9h |SSC Control Register 0000h SSCEIC b |FF76h BBh_ |SSC Error Interrupt Control Register 0000h SSCRB FOB2h E 59h SSC Receive Buffer (read only) XXXXh SSCRIC b |FF74h BAh_ |SSC Receive Interrupt Control Register 0000h SSCTB FOBOh E 58h SSC Transmit Buffer (write only) 0000h SSCTIC b |FF72h B9h |SSC Transmit Interrupt Control Register 0000h STKOV FE14h OAh CPU Stack Overflow Pointer Register FAOOh STKUN FE16h OBh CPU Stack Underflow Pointer Register FCoOoh SYSCON b |FFI2h 89h CPU System Configuration Register Oxx0h2 TO FE50h 28h CAPCOM Timer 0 Register 0000h T01CON b |FF50h A8h CAPCOM Timer 0 and Timer 1 Control Register 0000h TOIC b |FF9Ch CEh |CAPCOM Timer 0 Interrupt Control Register 0000h TOREL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h T1 FE52h 29h CAPCOM Timer 1 Register 0000h TAIC b |FF9Eh CFh |CAPCOM Timer 1 Interrupt Control Register 0000h TIREL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h T2 FE40h 20h GPT1 Timer 2 Register 0000h T2CON b |FF40h AOh GPT1 Timer 2 Control Register 0000h T2IC b |FF60h Boh GPT1 Timer 2 Interrupt Control Register 0000h T3 FE42h 21h GPT1 Timer 3 Register 0000h iy 47/75ST10F168 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 22 : Special Function Registers listed by name Name Physical 8-bit Description Reset address address value T3CON b |FF42h Ath GPT1 Timer 3 Control Register 0000h T3IC FF62h Bih GPT1 Timer 3 Interrupt Control Register 0000h T4 FE44h 22h GPT1 Timer 4 Register 0000h T4CON FF 44h A2h GPT1 Timer 4 Control Register 0000h T4IC FF 64h B2h GPT1 Timer 4 Interrupt Control Register 0000h T5 FE46h 23h GPT2 Timer 5 Register 0000h T5CON FF 46h A3h GPT2 Timer 5 Control Register 0000h T5IC FF66h B3h GPT2 Timer 5 Interrupt Control Register 0000h T6 FE48h 24h GPT2 Timer 6 Register 0000h T6CON FF48h A4h GPT2 Timer 6 Control Register 0000h T6IC FF68h B4h GPT2 Timer 6 Interrupt Control Register 0000h T7 FO50h E 28h CAPCOM Timer 7 Register 0000h T78CON FF20h 90h CAPCOM Timer 7 and 8 Control Register 0000h T7IC F17Ah E BEh |CAPCOM Timer 7 Interrupt Control Register 0000h T7REL FO54h E 2Ah CAPCOM Timer 7 Reload Register 0000h T8 FO52h E 29h CAPCOM Timer 8 Register 0000h T8IC b |F17Ch E BFh |CAPCOM Timer 8 Interrupt Control Register 0000h T8REL FO56h E 2Bh CAPCOM Timer 8 Reload Register 0000h TFR b |FFACh D6h_ | Trap Flag Register 0000h WDT FEAEh 57h Watchdog Timer Register (read only) 0000h WDTCON FFAEh D7h |Watchdog Timer Control Register 000xh? XPOIC b |F186h E C3h | CAN Module Interrupt Control Register 0000h4 XP1IC b |F18Eh E C7h | X-Peripheral 1 Interrupt Control Register o000h+ XP2IC b |F196h E CBh_ | X-Peripheral 2 Interrupt Control Register o0000h4 XP3IC b |F19Eh E CFh |PLL unlock Interrupt Control Register 0000h4 ZEROS b |FFICh 8Eh Constant Value 0s Register (read only) 0000h Notes 1. The value depends on the silicon revision and is described in the chapter XIX.1. 2. The system configuration is selected during reset. 3. Bit WDTR indicates a watchdog timer triggered reset. 4. The XPniC Interrupt Control! Registers contro! the interrupt requests from integrated X-Bus peripherals. Nodes where no X-Peripherals are connected may be used to generate software controlled interrupt requests by setting the respective XPniIR bit. 48/75 4]ST10F168 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) XIX.1 - Identification Registers The ST10F168 has four Identification registers, mapped in ESFR space. These register contain: a manufacturer identifier, a chip identifier, with its revision, a internal memory and size identifier, programming voltage description. IDMANUF (FO7Eh / 3Fh) ESFR 15 14 #13 #12 11 10 9 8 7 6 5 4 3 2 1 0 MANUF Pet ft ft -f-] R Description MANUF : Manufacturer Identifier - 020h: STmicroelectronics Manufacturer (JTAG worldwide normalisation). IDCHIP (FO7Ch / 3Eh) ESFR 15 14 13 12 14 10 9 8 7 6 5 4 3 2 1 0 | CHIPID | REVID | R R Description REVID : Device Revision Identifier - 1h for the first step, 2h for the second step.... CHIPID: Device Identifier - OA8h is the identifier of ST10F168. IDMEM (F07Ah / 3Dh) ESFR 15 14 138 12 11 10 9 8 7 6 5 4 3 2 1 0 | MEMTYP | MEMSIZE R R Description MEMSIZE : Internal Memory Size - 040h for ST10F168 (256K Bytes). Internal Memory size is 4 * <MEMSIZE> (in K Byte). MEMTYP_ : Internal Memory Type - 3h for ST10F 168 (Flash memory). IDPROG (F078h / 3Ch) ESFR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | PROGVPP | PROGVDD R R Description PROGVDD: Programming Vpp Voltage Vpp voltage when programming EPROM or Flash devices is calculated using the following formula: Vpp = 20 * <PROGVDD> / 256 [V] - 40h for ST10F 168 (5V). PROGVPP : Programming Vpp Voltage Vpp voltage when programming EPROM or Flash devices is calculated using the following formula: Vpp = 20 * <PROGVDDs> / 256 [V] - 9Ah for ST10F168 (12). iy 49/75ST10F168 XX - ELECTRICAL CHARACTERISTICS XX.1 - Absolute maximum ratings Symbol Parameter Value Unit Vpp Voltage on Vpp pins with respect to ground -0.5, +6.5 Vv Vio Voltage on any pin with respect to ground -0.5, (Vpp +0.5) Vv lov Input Current on any pin during overload condition -10, +10 mA Tov Absolute Sum of all input currents during overload condition [100 mA| mA Prot Power Dissipation 1.5 W Tr Ambient Temperature under bias for - ae! -40, +85 C Ambient Temperature under bias for - Q2" -40, +125 C Tsig Storage Temperature -65, +150 C Note 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (Vij>Vpp or Vin<Vss) the voltage on pins with respect to ground (Vsg) must not exceed the values defined by the Absolute Maximum Ratings. XX.2 - Parameter interpretation The parameters listed in the following tables represent the characteristics of the ST10F168 and its demands on the system. Where the ST10F168 logic provides signals with their respective timing characteristics, the symbol XX.3 - DC characteristics CC for Controller Characteristics is included in the Symbol column. Where the external system must provide signals with their respective timing characteristics to the ST10F168, the symbol SR for System Requirement is included in the Symbol column. Vpp = DV + 10%, Vsg = OV, Reset active, for Q6 version : T, = -40, +85C and for Q2 version TA = -40, +125C, unless otherwise specified. (all except RSTIN and XTAL1) Symbol Parameter Test Conditions Min. Max. Unit Vi__ SR Input low voltage - 0.5 0.2 Vpp-9.1] Vv Vics SR | Input low voltage (special threshold) - - 0.5 2.0 Vv Vig SR |[nput high voltage - 0.2Vpp +0.9| Vpp+05 | v Vini SR [Input high voltage RSTIN - 0.6 Vpp Vpp + 0.5 V Vin2 SR |Input high voltage XTAL1 - 0.7 Vpp Vpp + 0.5 Vv Vins SR | Input high voltage (special threshold) - 0.8 Vpp-0.2] Vpp+0.5 V HYS Input Hysteresis (special threshold) - 300 - mV Voit CC |Output low voltage! (all other outputs) lo1 = 1.6mA - 0.45 Vv 50/75 4]ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min Max. Unit Vou cc [Output hi gh voltage! (PortO, Port1, Port4, ALE, |!oH = S00HA 0.9 Vop - V RD, WR, BHE, CLKOUT, RSTOUT) lon = -2.4mA 24 - . lou = 250A 0.9 Vpop - V Vou1 CC |Output high voltage ' 2 (all other outputs) low = 1.6mA 2A _ Vv loz CC |Input leakage current (Port 5) OV < Vin < Vpp - +0.5 LA loz2 CC |Input leakage current (all other) OV <Vin<Vpp _ + WA lov SR |Overload current 34 - +5 mA Rrst CC |RSTIN pull-up resistor 3 OV <Vin < Vitmax 50 250 KQ lawH Read / Write inactive current Vout = 2.4V - -40 BA IRWL Read / Write active current Vout = Votmax -500 - BA lALEL ALE inactive current Vout = Votmax 40 - BA lALEH ALE active current Vout = 2.4V - 500 nA lp6H Port 6 inactive current Vout = 2.4V - -40 BA lpg Port 6 active current Vout = Vottmax -500 - LA IPOH Vin = Vikmin - -10 WA Port 0 configuration current IPoL Vin = Vitmax -100 - WA I= CC |XTAL1 input current OV < Vin <Vpp - +20 pA f = 1MHz, Ty, = Cig CC |Pin capacitance (digital inputs / outputs) 25C A - 10 pF RSTIN = Vin4 | - 20+6xf cc Power supply current fopy in [MHz] 8 cpu] mA RSTIN =V lip Idle mode supply current . int 9 - 20+3Xxfopy] mA fepu In [MHz] Ipp Power-down mode supply current Vpp = 5.5V 10 - 100 HA IppR Vpp Read Current Vpp < Vpp - 200 HA | Vpp P ing / Erasing Current 3 Vep = 12. A PPW pp Programming / Erasing Curren fopy = 25MHz - 20 m Vpp" Vpp during Programming / Erasing Operations 11,4 12.6 V ky 51/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Notes 1. ST10F168 pins are equipped with low-noise output drivers which significantly improve the devices EMI performance. These low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in column Test Conditions is delivered in all cases. 2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 3. Partially tested, guaranteed by design characterization. 4. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. Voy > Vpp+0.5V or Voy <-0.5V). The absolute sum of input overload currents onall port pins may not exceed 50mA. The supply voltage must remain within the specified limits. 5. The maximum current may be drawn while the respective signal line remains inactive. 6. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for CS output and the open drain function is not enabled. 7. The minimum current must be drawn in order to drive the respective signal line active. 8. The power supply current is a function of the operating frequency. This dependency is illustrated in the Figure 15. These parameters are tested at Vppmax and 25MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during reset. After reset, Port 0 is driven with the value OOCCh that produces infinite execution of NOP instruction with 15 wait-state, R/W delay, memory tristate wait state, normal ALE. Peripherals are not activated. 9. |dle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 15. These parameters are tested at Vppmax and 25MHz CPU clock with all outputs disconnected and all inputs at Vj, or Vj. 10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at O V to 0.1V or at Vpp 0.1V to Vpp, Vrer = OV, all outputs (including pins configured as outputs) disconnected. 711. Apply 12V on Vpp 10ms after Vpp is stable at power up. Vpp pin must be switched to OV before to switch off Vpp (5V). Figure 15 : Supply / idle current as a function of operation frequency I[mA] 2007 1007 95 |" 10+ . _ 5 10 15 20 25 fopu [MHz] 4] 52/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) XX.4 - A/D converter characteristics Vopp = BV +10%, Vgg = OV, 4.0V < Varner < Vpp + 0.1V, Vgg - 0.1V < Vaenp < Vsg + 0.2V, Q6 version : Ta = -40, +85C and for Q2 version TA = -40C, +125C, unless otherwise specified Symbol Parameter Test Conditions | Min. Max. Unit Vain SR {Analog input voltage range 1 VAGND VAREF Vv ts CC|Sample time? 34 - 2tsc tc | CC |Conversion time* 54 - [14 tee +tg + 4TCL TUE CC Total unadjusted error 6 - +2 LSB Rarer SR |Internal resistance of reference voltage source tec in [ns] 78 - tec / 165 - 0.25 kQ, Rasrc SR |Internal resistance of analog source tg in [ns]? - tg / 330 - 0.25 kQ Cain CCY]ADC input capacitance 8 - 33 pF Notes 7. Vain may exceed Vacnp OF Varer up to the absolute maximum ratings. However, the conversion result in these cases will be ADC X000 ,, or X3FF,, respectively. 2. Sample and conversion time are programmable, use table below to calculate values. 3. During the sample time the input capacitance C; can be charged/ discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts. After the end of the sample time ts, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tg depend on programming and can be taken from the table below. 4. This parameter is fixed by ADC control logic. 5. This parameter includes the sample time ts, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tog depend on programming and can be taken from the table below. 6. TUE is tested at Varner =5.0V, Vaanp =9V, Voc = 4.9V. It is guaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see |OV specification) occurs on maximum of 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA. During the reset calibration sequence the maximum TUE may be +4 LSB. 7. During the conversion the ADCs capacitance must be repeatedly charged or discharged. The internal resistance of the reference vollage source must allow the capacitance to reach its respective voltage level within tcc. The maximum internal resistance results from the programmed conversion timing. 8. Partially tested, guaranteed by design characterization. Sample time and conversion time are programmable. The table below should be used to calculate the above timings. Conversion Time Sample Time ADCON.15/14 (ADCTC) Conversion clock teg ADCON.13/12 (ADSTC) Sample clock tg 00 TCL x 24 00 tcc 01 Reserved, do not use 01 tec x2 10 TCL x 96 10 tec x 4 11 TCL x 48 11 tec x 8 4] 53/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) XX.5 - AC characteristics XX.5.1 - Test waveforms Figure 16 : Input / output waveforms 2.4V 0.2Vpp+0.9 0.2Vppt0.9 > Test Points < 0.45V 0.2Vpp-0.1 0.2Vpp-0.1 AC inputs during testing are driven at 2.4V for a logic 1 and 0.4V for a logic 0. Timing measurements are made at Vj, min for a logic 1 and V,_ max for a logic 0. Figure 17 : Float waveforms Vou Vioad +0.1V Timing Reference Points V Load > VoL +0.1V VoL For timing purposes a port pin is no longer floating when V, gap changes of +100mV. It begins to float when a 100mV change from the loaded Voy/Vo, level occurs (IoH/lo, = 20MA). XX.5.2 - Definition of internal timing The internal operation of the ST10F168 is controlled by the internal CPU clock fepy. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called TCL (see Figure 18). 54/75 The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fopu- This influence must be regarded when calculating the timings for the ST10F168. The example for PLL operation shown in the Figure 18 refers to a PLL factor of 4. 4]ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0Q.15-13 (POH.7-5). Figure 18 : Generation Mechanisms for the CPU Clock Phase locked loop operation fxrat.| feu | | LE LI LI LILI LILI LJ Tourcu Direct Clock Drive tre LE LE LE LI LE LILI LE LE] teu LJ LI LI LI LILI LI LI LJ TCLITCL! Prescaler Operation kaa LJ LE LE LI LE LILI LILI] fcpu | TCL TCL XX.5.3 - Clock generation modes The Table 23 associates the combinations of these three bit with the respective clock generation mode. Table 23 : CPU Frequency Generation POH.7 POH.6 POH.5 CPU Frequency fepy = fytaL X F External Clock Input Range Notes 1 1 1 Fytat X 4 2.5 to 6.25MHz Default configuration 1 1 0 FxtaLX 3 3.33 to 8.33MHz 1 0 1 FytaL X 2 5 to 12.5MHz 1 0 0 Fyta Xx 5 2 to SMHz 0 1 1 Fxtat X 4 1 to 25MHz Direct drive 0 1 0 Fytay X 1.5 6.66 to 16.6MHz Q Q 1 Fyta /2 2 to 50MHz CPU clock via prescaler? 0 0 0 Fytay X 2.5 4 to 10MHz Notes 1. The external clock input range refers to a CPU clock range of 1...25MHz. 2. The maximum depends on the duty cycle of the external clock signal. 3. The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal serial resistance of the crystal is less than 40Q.. However, higher frequencies can be applied with an external clock source, but in this case, the input clock signal must reach the defined levels Vi, and Vizio. 4] 55/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) XX.5.4 - Prescaler operation When pins P0.15-13 (POH.7-5) equal 001 during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fopy is half the frequency of fytaL and the high and low time of fepy (i.e. the duration of an individual TCL) is defined by the period of the input clock fy. The timings listed in the AC Characteristics that refer to TCL therefore can be calculated using the period of fy;a, for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. XX.5.5 - Direct drive When pins P0.15-13 (POH.7-5) equal 011 during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fcpy directly follows the frequency of fyrza_ so the high and low time of fopy (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fytay. The timings listed below that refer to TCL therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated by the following formula: TCL min= 1/tytaLOCmin DC= duty cycle For two consecutive TCLs the deviation caused by the duty cycle of fyta_ is compensated so the duration of 2TCL is always 1/fyta,. The minimum value TCL, therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: 2TCL= 1/fy ray Note The address float timings in Multiplexed bus mode (t,, and tgs) use the maximum duration of TCL (TCLiaa, = I/yxtaL x DCmax) instead of TCL nin. If bit OWDDIS in the SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator 56/75 Watchdog. If bit OWDDIS is set, then the PLL is switched off. XX.5.6 - Oscillator Watchdog (OWD) When the clock option selected is direct drive or direct drive with prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the PLL circuitry. This oscillator watchdog operates as follows : After a reset, the Oscillator Watchdog is enabled by default. To disable the OWD, the bit OWDDIS (bit 4 of SYSCON register) must be set. When the OWD is enabled, the PLL runs on its free-running frequency, and increments the Oscillator Watchdog counter. On each transition of XTAL1 pin, the Oscillator Watchdog is cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the Oscillator Watchdog Interrupt Request (XP8INT) is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current. XX.5.7 - Phase locked loop For all other combinations of pins P0.15-13 (POH.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock (see Table 23). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fopy = fyTAL x F). With every Fth transition of fyzq, the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fcpy is constantly adjusted so it is locked to fyta,. The slight variation causes a jitter of fopy which also effects the duration of individual TCL. The timings listed in the AC Characteristics that refer to TCL therefore must be calculated using the minimum TCL that is possible under the respective circumstances. iyST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) The real minimum value for TCL depends on the where N = number of consecutive TCL periods jitter of the PLL. The PLL tunes fopy to keep it and 1 <N < 40. So fora period of 3 TCL periods locked on fyza,. The relative deviation of TCLis = (N=): the maximum when it is refered to one TCL D3 period. It decreases according to the formula and 3TCLinin to the Figure 19 given below. For N periods of TCL the minimum value is computed using the 3TCLinin 4 -3/15 =3.8% 3TCLyow X (1 - 3.8/100) 3TCLNom x 0.962 (57.72ns at fopy = 25MHz) corresponding deviation Dy: This is especially important for bus cycles using wait [P | states and e.g. for the operation of timers, serial TCLhayin = TL Gy x ; _ | interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower Baud rates, etc.) the deviation caused by the Dy= +(4-N/15)[% N= *( I PLL jitter is negligible (see Figure 19). Figure 19 : Approximated maximum PLL jitter Max. jitter [7%] This approximated formula is valid for + 1<N<40and 10M < fepy < 25MHz. 4 +2. H a : oo XX.5.8 - External clock drive XTAL1 Vpp = 5V + 10%, Vsg = OV, for Q6 version : Ty = -40, +85C and for Q2 version TA = -40, +125C, unless otherwise specified. f =f xN fopu=fytat | fepu = fxtaL/ 2 PU a Symbol Parameter N=1.5/2/2.5/3/4/5) Unit Min. Max. Min. Max. Min. Max. tosc SR [Oscillator period 40! 1000 20 500 40 xN 100 xN ns ty SR |High time 182 - 62 - 102 - ns t2 SR |Lowtime 182 _ 62 _ 102 = ne tg SR |Rise time - 102 - 62 - 102 ns t4 SR _ | Fall time - 102 - 62 - 102 ns Notes 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 2. The input clock signal must reach the defined levels Vy and Vjy0. Figure 20 : External clock drive XTAL1 ty tg -, ta Vine Vit \ - tp > tosc > ky 57/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) XX.5.9 - Memory cycle variables The tables below use three variables which are derived from the BUSCONx registers and which represent the special characteristics of the programmed memory cycle. The following table describes how these variables are computed. Symbol Description Values ta ALE Extension TCL x <ALECTL> tc Memory Cycle Time wait states 2TCL x (15 - <MCTC>) tr Memory Tristate Time 2TCL x (1 - <MTTC>) XX.5.10 - Multiplexed bus Vpp = SV 10%, Vgg = OV, for Q6 version : Ta =-40, +85C and for Q2 version TA = -40, +125C, C, = 100pF, ALE cycle time = 6 TCL + 2t, + te + te (120ns at 25MHz CPU clock without wait states), unless otherwise specified. Table 24 : Multiplexed bus characteristics Max. CPU Clock Variable CPU Clock 25MHz 1/2 TCL = 1 to 25MHz . Symbol Parameter Unit Min. Max. Min. Max. ts CC [ALE high time 10 + ta - TCL - 10 + ty - ns tg CC |Address setup to ALE 4+ta - TCL - 16+ ta - ns tz CC |Address hold after ALE 10 + ty - TCL-10+t,g - ns tg CC |ALE falling edge to RD, WR 10 + ta - TCL-10+tg - ns (with RW-delay) tg CC |ALE falling edge to RD, WR 10+ ty - 10+t, - ns (no RW-delay) tig CC |Address float after RD, WR 1 - 6 - 6 ns (with RW-delay) t44 CC | Address float after RD, WR * - 26 - TCL +6 ns (no RW-delay) ty2 CC |RD, WR low time (with RW-delay) 30 +tc - 2TCL-10+tc - ns ty3 CC |RD, WR low time (no RW-delay) 50 + tc - 3TCL-10+tc - ns ty4 SR [RD to valid data in (with RW-delay) - 20+tc - 2TCL - 20+tc | ns t145 SR |RD to valid data in (no RW-delay) - 40 +tc - 3TCL - 20+ tc | ns tig SR |ALE low to valid data in - 40 +ta tte - 3TCL - 20 ns tta ttc t47 SR |Address / Unlatched CS to valid data in 150 +2ta+tc - 4TCL - 30 ns +2tat+ic tig SR |Data hold after RD rising edge 0 - 0 - ns tig SR |Data float after RD ' - 26 + tr - 27CL-14+tF | ns 4] 58/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Table 24 : Multiplexed bus characteristics (continued) Max. CPU Clock Variable CPU Clock 25MHz 1/2 TCL = 1 to 25MHz . Symbol Parameter Unit Min. Max. Min. Max. top CC |Data valid to WR 20+tc - 2TCL - 20+te - ns to3 CC |Data hold after WR 26 + te - 2TCL - 14+ tp - ns to5 CC |ALE rising edge after RD, WR 26 +t - 2TCL - 14+ te - ns to7 CC |Address / Unlatched CS hold 26 + te - 2TCL - 14+ tp - ns after RD, WR tgg CC |ALE falling edge to Latched CS -4-ta 10-ta -4-ta 10-ta ns t3g SR |Latched CS low to Valid Data In - [40 +t + 2ty - 3TCL - 20 ns tig + 2ta t4g CC |Latched CS hold after RD, WR 46 + te - 3TCL - 14+ te - ns tga CC |ALE fall. edge to RdCS, WrCS 16+t, - TCL-4+ta - ns (with RW delay) tag CC |ALE fall. edge to RdCS, WrCS 4+ta - 4A+ty - ns (no RW delay) tag CC | Address float after RCS, WrCS ' - 0 - 0 ns (with RW delay) t45 CC | Address float after RCS, WrCS ' - 20 - TCL ns (no RW delay) t4g SR |RdCS to Valid Data In (with RW delay) - 16 +tc - 2TCL-24+tc] ns t4z SR |RdCS to Valid Data In (no RW delay) - 36 +tc - 3TCL- 24+t] ns tag CC |RdCS, WrCS Low Time (with RWdelay) | 30+tc - 2TCL-10+t - ns tag CC }RdCS, WrCS Low Time (no RW delay) 50+t - 3TCL-10+t - ns t59 CC |Data valid to WrCS 26+tc - 2TCL-14+tc - ns t5, SR |Data hold after RdCS 0 - 0 - ns ts2 SR |Data float after RdCS " - 20 + tr - 2TCL -20+tF] ns t54 CC |Address hold after RdCS, WrCS 20+tp - 2TCL - 20+ te - ns t5g CC |Data hold after WrCS 20 + tf - 2TCL - 20+ tr - ns Note 1. Partially tested, guaranteed by design characterization. 4] 59/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 21 : External Memory Cycle : multiplexed bus, with / without read/write delay, normal ALE oxouT ZN NSF NY NY SN oo bg > f, ALE N t, m} ate fag t bo a < 17 . sg - r<f,, } , = yo CSx . \ o] | at > A23-A16 hz > i = (A15-A8) Address BHE he > Read Cycle pt 5 t, let, > BUS (PO) x Address -<} Data In >> Address <1, > alo, he __ fg <t,, > * a RD PN / tt, * hs - i ~\< t4 i <__ ft, + Write Cycle | tos ] BUS (PO) x Address Data Out x j_ |, > bo WR dt ON y WAL AP oT WRH _ < 13 - 60/75 kyST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 22 : External Memory Cycle: multiplexed bus, with / without read/write delay, extended ALE CLKOUT ALE CSsx A23-A16 (A15-A8) BHE Read Cycle BUS (PO) Write Cycle BUS (PO) 3 =| 23) = wu r b or be > ef M pt I. _ if, PT B i 7 < ty > 40 *J \ bsg tf, w}," " "OF ee ee + fe by; > Address <, > b > Addre$s Data In >> <t. | <<|- ft, eet t -) <{, mye , ; ha fT }--- L__/| his ~ ff, __| t ti > >< Address Data Out ___/,, > ls wtf <{, hy too A 4] 61/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 23 : External Memory Cycle: multiplexed bus, with / without read/write delay, normal ALE, read/write chip select won ZN \_/ NL NN <_ f., tT } | / a+ oO Y ALE t Z A23-A16 hz > < {,, (A15-A8) Address is xX Xx be > Read Cycle rb gt, ef. BUS (PO) x Address -< Data In >> Address i he t 5 > elite L.__ fs plis > ~ \ V RdCSx kee NN f) hs al lis - lig Le ls Write Cycle bz - : be _t,, sf BUS (PO) x Address Datd Out 5 feo -_m WrCSx ax H tag Lf, _> lig a 62/75 4]ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 24 : External Memory Cycle: multiplexed bus, with / without read/write delay, extended ALE, read/write chip select ALE A23-A16 (A15-A8) BHE Read Cycle BUS (PO) RdCSx Write Cycle BUS (PO) wrCsx CLKOUT Ne A PNY NN b be + |<. ~ _ hy > Address ~< |, t_ /., > t, > Addre$s tata In *K tele l, ><1L,, elj, _ : fo a | : N\ / ae his > > att lig > K Address > Data Out ti, 4] 63/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) XX.5.11 - Demultiplexed bus Vpp = 5V 10%, Vgg = OV, for Q6 version : Ty, = -40, +85C and for Q2 version TA= -40, +125C, C, = 100pF, ALE cycle time = 4 TCL + 2t, + tc + te (80ns at 25MHz CPU clock without wait states), unless otherwise specified. Table 25 : Demultiplexed bus characteristics Max. CPU Clock Variable CPU Clock 25MHz 1/2 TCL = 1 to 25MHz : Symbol Parameter Unit Min. Max. Min. Max. ts CC |ALE high time 10+ ta - TCL - 10+ ta - ns tg CC |Address setup to ALE 4+ty - TCL - 16+ tg - ns tgq CC | Address / Unlatched CS setup to RD, WR | 30 + 2t, - 2TCL - 10 + 2ty - ns (with RW-delay) tg; CC |Address / Unlatched CS setup to RD, WR} 10 + 2ta - TCL -10 +2t, - ns (no RW-delay) t12 CC |RD, WR low time (with RW-delay) 30 +tc - 2TCL-10+tc - ns ty3 CC |RD, WR low time (no RW-delay) 50 +tc - 3TCL-10+tc - ns t44 SR [RD to valid data in (with RW-delay) - 20 +tc - 2TCL- 20+tc| ns ty5 SR |RD to valid data in (no RW-delay) - 40 +tc - 3TCL-20+tc| ns tig SR ALE low to valid data in - 40 +ta tte - 3TCL - 20 ns +ta tic ty7 SR |Address / Unlatched CS to valid data in [50 +2t, +t - 4TCL - 30 ns +2tar+te tig SR |Data hold after RD rising edge 0 - 0 - ns to9 SR | Data float after RD rising edge - 26 +tF - 2TCL-14 ns (with RW-delay)* 2 + te + 2ta' toy SR | Data float after RD rising edge - 10 +te - TCL- 10 ns (no RW-delay)' 2 + te + 2tg! too CC |Data valid to WR 20 +tc - 2TCL- 20 +tc - ns tog CC |Data hold after WR 10+ tp - TCL - 10+ te - ns tog CC |ALE rising edge after RD, WR 10+ tp - -10 + tp - ns tog CC | Address / Unlatched CS hold after RD, WR 3} (no te) - 0 (no tr) - ns -5+tp -5 + te (te > 0) (t= > 0) togh CC |Address / Unlatched CS hold after WRH | -5 + te - -5 + te - ns t3g CC |ALE falling edge to Latched CS -4-ty 10-ta -4-ty 10-ta ns 64/75 kyST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Table 25 : Demultiplexed bus characteristics (continued) Max. CPU Clock Variable CPU Clock Symbol Parameter 25MHz 1/2 TCL = 1 to 25MHz Unit Min. Max. Min. Max. tgg SR |Latched CS low to Valid Data In - 40 + tct at, - 8TCL - 20 ns +tg + 2ta tg, CC |Latched CS hold after RD, WR 6 +tp - TCL-14+tp - ns tgo CC |Address setup to RdCS, WrCS 26 + 2ty - 2TCL - 14 + 2ty - ns (with RW-delay) tgg CC |Address setup to RdCS, WrCS 6 + 2ty - TCL -14 +2t, - ns (no RW-delay) t4g SR RdC to Valid Data In (with RW-delay) - 16+tc - 2TCL- 24+1t] ns t47 SR RdCS to Valid Data In (no RW-delay) - 36 +tc - 8TCL- 24+tc] ns t4g CC |RdCS, WrCS Low Time (with RW-delay) | 30+t - 2TCL-10+tc - ns tag CC |RdCS, WrCS Low Time (no RW-delay) | 50+t - 3TCL-10+tc - ns t59 CC | Data valid to WrCS 26 +tc - 2TCL-144+tc - ns ts4 SR |Data hold after RdCS 0 - 0 - ns ts53 SR | Data float after RACS (with RW-delay) 2 - 20 +t - 2TCL -20+tr | ns tes SR |Data float after RACS (no RW-delay) 2 - O+te - TCL-20+tp | ns t55 CC | Address hold after RACS, WrCS A0+t - -10 + te - ns tsz7 CC |Data hold after WrCS 6 +tp - TCL-14+tp - ns Notes 1. RW-delay and t, refer to the following bus cycle. 2. Partially tested, guaranteed by design characterization. 3. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 4] 65/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 25 : External Memory Cycle: demultiplexed bus, with / without read/write delay, normal ALE KeouT KN NY NYA NY SN 5 the >- ol obec ALE \ Lae fs - >< {3g pe Ey ty _ ; tsg > ence CSx *1 N t TE ~< hy wm atl A23-A16 (A15-A8) xX Address BHE [tie Read Cycle Data Bus (PO) 5 Data In ; +f. a-ef,, pX$ f 4) Hef, ht ty << f, >} RD | N f_ ee <_f,, >| Write Cycle | Data Bus (PO) > ee DatalOut <1. > je f55 toy ptf am ________ WR T \ Y WRL sss WRH <$t,, > <1,, > 66/75 kyST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 26 : External Memory Cycle: demultiplexed bus, with / without read/write delay, extended ALE CLKOUT ALE CSsx A23-A16 (A15-A8) BHE Read Cycle Data Bus (PO) Write Cycle Data Bus (PO) 3 =| 23) = wu r {,$-_ ' |> be 16 | \ < {, hss * <f ty > } ts > wenn PN ji <_,, | ~ ts aly, or mM Address K Htts \ f > < Data In lao i tg tay aa tal ti; + _+-+*_L, _ : YY 55 ut ie Log 4] 67/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 27 : External Memory Cycle: demultiplexed bus, with / without read/write delay, normal ALE, read/write chip select tb +<___1,, _ 4 be ALE FY vat hy > bs A23-A16 (A15-A8) Address BHE fb: Read Cycle Data Bus (PO) > Data In RdCsx ;..-.Y Write Cycle Data Bus (PO) >_< DatajOut a Hef ef, <-[,., 4 WrcSx j . | ay, -<f,, 4] 68/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 28 : External Memory Cycle: demultiplexed bus, no read/write delay, extended ALE, read/write chip select NAN YF NAINA \_ CLKOUT {_, : > be ALE Y 6 > | 26 \ <_{, hi; ~ 5 A23-A16 (A15-A8) f Address | Read Cycle Data Bus (PO) < bata In ~ bso = bs > bbs <. tas aja ty; - oe hs RdCsx Jee a, Write Cycle ut > Data Bus (PQ) ef wrCsx 4] 69/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) XX.5.12 - CLKOUT and READY Vopp = 5V 410%, Vsg = OV, for Q6 version : Ty = -40, +85C and for Q2 version TA= -40, +125C, C, = 100pF, unless otherwise specified Table 26 : CLKOUT and READY characteristics Max. CPU Clock Variable CPU Clock Symbol Parameter 25MHz 1/2 TCL = 1 to 25MHz Unit Min. Max. Min. Max. tag CC |CLKOUT cycle time 40 40 2TCL 2TCL ns tg9 CC |CLKOUT high time 14 - TCL-6 - ns tg, CC |CLKOUT low time 10 - TCL 10 - ns tga CC |CLKOUT rise time - 4 - 4 ns t33 CC |CLKOUT fall time - 4 - 4 ns tg4 CC |CLKOUT rising edge to ALE falling edge 3+ta +7 +tpa 3 +ta +7 +ta ns tg5 SR | Synchronous READY setup time to CLKOUT 14 - 14 - ns t3g SR | Synchronous READY hold time after CLKOUT 4 - 4 - ns tg7 SR |Asynchronous READY low time 54 - 2TCL + 14 - ns tsg SR | Asynchronous READY setup time 14 - 14 - ns tsg SR | Asynchronous READY hold time ' 4 - 4 - ns tgo SR |Async. READY hold time after RD, WR high 0 0 + 2ta 0 TCL - 20 ns (Demultiplexed Bus) @ ttc + te? + 2tq tic +t? Notes 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 70/75 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2t, and to refer to the next following bus cycle, te refers to the current bus cycle 4]ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 29 : CLKOUT and READY READY | Running cycle 1) | wait state MUX / Tristate 6) I Tr Eel OE CLKOUT NEA NEY oN . J 30 ALE LZ) WR SOU N / D. WR 2) / Synchronous os ibe tes bag Remy UA | NR Asynchronous _,'53, sg bsg bs cot) FEY YA) RA LILLY ana Notes 7. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR ). 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfillt 37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here. For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this delay is zero. 7. The next external bus cycle may start here. 4] 71/75ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) XX.5.13 - External bus arbitration Vopp =5V+10%, Vss = OV, for Q6 version : Ty 100pF, unless otherwise specified. -40, +85C and for Q2 version TA = -40, +125C, C, = Max. CPU Clock Variable CPU Clock 25MHz 1/2 TCL =1 to 25MHz . Symbol Parameter Unit Min. Max. Min. Max. tg, SR |HOLD input setup time to CLKOUT 20 - 20 - ns tg2 CC }CLKOUT to HLDA high or BREQ low delay - 20 - 20 ns tgg CC |CLKOUT to HLDA low or BREQ high delay - 20 - 20 ns tea CC ICSx release - 20 - 20 ns tg5 CC |CSx drive -4 24 -4 24 ns tes CC |Other signals release ' - 20 - 20 ns tgz CC |Other signals drive -4 24 -4 24 ns Note 1. Partially tested, guaranted by design characterization. Figure 30 : External bus arbitration, releasing the bus CLKOUT i I | | | HLDA | 1) | | | | tea . N BREQ \ 2) deg (P6.x) | | Sf | | 288, 1) _ Others | I > Notes 1. The ST10F168 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pullup) after Iga. 72/75 4]ST10F168 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 31 : External bus arbitration, (regaining the bus) ores SYNANYANNXVLA NY Csx (P6.x) Others . us nun nun nun Notes 1. This is the last opportunity for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F 168 requesting the bus. 2. The next ST10F168 driven bus cycle may start here. 4] 73/75ST10F168 XXI - PACKAGE MECHANICAL DATA Figure 32 : Package Outline PQFP144 (28 x 28mm) Millimeters ' Inches (approx) Dimensions Typ. . in. Typ. A Al D1 D3 e E 31.45 1.219 Et 28.10 1.098 L 0.95 0.026 Li K 0 (Min.), 7 (Max.) Note 1. Package dimensions arein mm. The dimensions quoted in inches are rounded. XXII - ORDERING INFORMATION Sales type Temperature range Package ST10F168-Q6 -40%T to 85% PQFP144 (28 x 28mm) ST10F168-Q2 -40C to 125C PQFP144 (28 x 28mm) 74/75 iy