SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES * * * * * * * * * * DESCRIPTION 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212 Chipset (Serializer/Deserializer) Power Consumption <350 mW (Typ) at 40 MHz Synchronization Mode for Faster Lock Lock Indicator No External Components Required for PLL Low-Cost 28-Pin SSOP Package Industrial Temperature Qualified, TA = -40C to 85C Programmable Edge Trigger on Clock (Rising or Falling Edge) Flow-Through Pinout for Easy PCB Layout The SN65LV1021 serializer and SN65LV1212 deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 40 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 480-Mbps payload-encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1021 and characterized for operation temperature of -40C to 85C. SN65LV1212 Deserializer SN65LV1021 Serializer SYNC1 SYNC2 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 TCLK_R/F TCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SN65LV1212 are over ambient air 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DVCC DVCC AVCC AGND PWRDN AGND DO+ DO- AGND DEN AGND AVCC DGND DGND AGND RCLK_R/F REFCLK AVCC RI+ RI- PWRDN REN RCLK LOCK AVCC AGND AGND DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 DVCC DGND DVCC DGND ROUT5 ROUT6 ROUT7 ROUT8 ROUT9 ORDERING INFORMATION DEVICE PART NUMBER Serializer SN65LV1021DB Deserializer SN65LV1212DB Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2005, Texas Instruments Incorporated SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. BLOCK DIAGRAMS SN65LVDS1021 SN65LVDS1212 TCLK (10 MHz to 40 MHz) PLL Timing / Control Y+ A- Y- DEN PLL Clock Recovery SYNC1 SYNC2 10 Output Latch A+ Serial-to-Parallel TCLK_R/F Input Latch DIN Parallel-to-Serial LVDS 10 Timing / Control DOUT REFCLK REN LOCK RCLK_R/F RCLK (10 MHz to 40 MHz) FUNCTIONAL DESCRIPTION The SN65LV1021 and SN65LV1212 are a 10-bit serializer/deserializer chipset designed to transmit data over differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 40 MHz. The chipset has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down mode, and high-impedance mode. The following sections describe each state of operation. INITIALIZATION MODE Initialization of both devices must occur before data transmission can commence. Initialization refers to synchronization of the serializer and deserializer PLLs to local clocks. When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state, while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs remain in the high-impedance state, while the PLL locks to the TCLK. SYNCHRONIZATION MODE The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be accomplished in one of two ways: * RAPID SYNCHRONIZATION: The serializer has the capability to send specific SYNC patterns consisting of six ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid a SYNC1 or SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent. 2 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 FUNCTIONAL DESCRIPTION (continued) When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low. When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the deserializer LOCK output directly to SYNC1 or SYNC2. * RANDOM-LOCK SYNCHRONIZATION: The deserializer can attain lock to a data stream without requiring the serializer to send special SYNC patterns. This allows the SN65LV1212 to operate in open-loop applications. Equally important is the deserializer's ability to support hot insertion into a running backplane. In the open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, because lock time varies due to data stream characteristics, the exact lock time cannot be predicted. The primary constraint on the random lock time is the initial phase relation between the incoming data and the REFCLK when the deserializer powers up. The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer could enter false lock--falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive multitransition (RMT);see Figure 1 for RMT examples. RMT occurs when more than one low-high transition takes place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the data pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock exists. Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock pattern changes. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock, the RMT pattern does not affect the deserializer state as long as the same data boundary happens each cycle. The deserializer does not go into lock unitil it finds a unique four consecutive cycles of data boundary (stop/start bits) at the same position. The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive cycles. Then the desiralizer goes out of lock and hunts for the new data boundary (stop/start bits). In the event of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a high-impedance state. The user's system should monitor the LOCK pin in order to detect a loss of synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as previously noted. 3 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 FUNCTIONAL DESCRIPTION (continued) DIN0 Held Low and DIN1 Held High Stop Bit Start Bit DIN0 Stop Bit Start Bit Stop Bit Start Bit Stop Bit Start Bit DIN1 DIN4 Held Low and DIN5 Held High Stop Bit Start Bit DIN4 DIN5 DIN8 Held Low and DIN9 Held High Stop Bit Start Bit DIN8 DIN9 Figure 1. RMT Pattern Examples DATA TRANSMISSION MODE After initialization and synchronization, the serializer accepts parallel data from inputs DIN0-DIN9. The serializer uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to strobe incoming data. If either of the SYNC inputs is high for 6 TCLK cycles, the data at DIN0-DIN9 is ignored regardless of the clock edge selected and 1026 cycles of SYNC pattern are sent. After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO) at 12 times the TCLK frequency. For example, if TCLK is 10 MHz, the serial rate is 10 x 12 = 120 Mbps. Because only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 12 MHz, the useful data rate is 10 x 12 = 120 Mbps. The data source, which provides TCLK, must be in the range of 10 MHz to 40 MHz. The serializer outputs (DO) can drive point-to-point connections or limited multipoint or multidrop backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN is high, and SYNC1 and SYNC2 are low. When DEN is driven low, the serializer output pins enter the high-impedance state. 4 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 FUNCTIONAL DESCRIPTION (continued) Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to the embedded clock and uses it to recover the serialized data. ROUTx data is valid when LOCK is low, otherwise ROUT0-ROUT9 is invalid. The ROUT0-ROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be used is selected by the RCLK_R/F input. The ROUT0-ROUT9, LOCK and RCLK outputs can drive a maximum of three CMOS input gates (15-pF load, total for all three) with a 40-MHz clock. POWER DOWN When no data transfer is required, the power-down mode can be used. The serializer and deserializer use the power-down mode, a low-power sleep mode, to reduce power consumption. The deserializer enters power down when you drive PWRDN and REN low. The serializer enters power down when the PWRDN is driven low. In power down, the PLL stops and the outputs enter a high-impedance state, which disables load current and reduces supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high. Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize and resynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializer initializes and drives LOCK high until lock to the LVDS clock occurs. HIGH-IMPEDANCE MODE The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output pins (DO+ and DO-) into a high-impedance state. When you drive DEN high, the serializer returns to its previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When the REN pin is driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins (ROUT0-ROUT9) and RCLK are placed into the high-impedance state. The LOCK output remains active, reflecting the state of the PLL. Deserializer Truth Table INPUTS (1) (2) (3) OUTPUTS PWRDN REN ROUT[0:9] H H Z H H L X H L LOCK (1), (2) RCLK (3) H Z Active L Active Z Z Z Z Active Z LOCK output reflects the state of the deserializer with regard to the selected data stream. ROUT and RCLK are 3-stated when LOCK is asserted high. RCLK active indicates the RCLK is running if the deserializer is locked. The timing of RCLK with respect to ROUT is determined by RCLK_R/F. 5 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 TERMINAL FUNCTIONS PIN NAME DESCRIPTION SYNC1, SYNC2 LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of the two pins is asserted high for 6 cycles of TCLK, the serializer initiates transmission of a minimum 1026 SYNC patterns. If after completion of transmission of 1026 patterns SYNC continues to be asserted, then the transmission continues until SYNC is driven low and if the time SYNC holds > 6 cycles, another 1026 SYNC pattern transmission initiates. SERIALIZER 1, 2 3-12 DIN0-DIN9 13 TCLK_R/F Parallel LVTTL data inputs 14 TCLK LVTTL-level reference clock input. The SN65LV1021 accepts a 10-MHz to 40-MHz clock. TCLK strobes parallel data into the input latch and provides a reference frequency to the PLL. LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge data strobe. 15, 16 DGND Digital circuit ground 18, 20, 23, 25 AGND Analog circuit ground (PLL and analog circuits) 17, 26 AVCC Analog circuit power supply (PLL and analog circuits) 19 DEN LVTTL logic input. Low puts the LVDS serial output into the high-impedance state. High enables serial data output. 21 DO- Inverting LVDS differential output Noninverting LVDS differential output 22 DO+ 27, 28 DVCC 24 PWRDN LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs into the high-impedance state, putting the device into a low-power mode. LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency. Digital circuit power supply DESERIALIZER 6 3 REFCLK 15-19, 24-28 ROUT0-ROUT9 2 RCLK_R/F 9 RCLK LVTTL-level output recovered clock. Use RCLK to strobe ROUTx. 14, 20, 22 DGND Digital circuit ground 1, 12, 13 AGND Analog circuit ground (PLL and analog circuits) 4, 11 AVCC Analog circuit power supply (PLL and analog circuits) 8 REN LVTTL logic input. Low places ROUT0-ROUT9, LOCK, and RCLK in the high-impedance state. 5 RI+ Serial data input. Noninverting LVDS differential input 6 RI- Serial data input. Inverting LVDS differential input 10 LOCK LVTTL-level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge. 21, 23 DVCC Digital circuit power supply 7 PWRDN Parallel LVTTL data outputs LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge data strobe. LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedance state, putting the device into a low-power mode. SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC to GND -0.3 V to 4 V LVTTL input voltage -0.3 V to (VCC + 0.3 V) LVTTL output voltage -0.3 V to (VCC + 0.3 V) LVDS receiver input voltage -0.3 V to 3.9 V LVDS driver output voltage -0.3 V to 3.9 V LVDS output short circuit duration Continuous Electrostatic discharge: TA = 25C HBM up to 6 kV MM up to 200 V Junction temperature 150C Storage temperature -65C to 150C Lead temperature (soldering, 4 seconds) 260C Maximum package power dissipation 1.27 W Package derating (1) 10.3 mW/C above 25C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS VCC (1) Supply voltage Receiver input voltage range VCM MIN NOM MAX 3 3.3 3.6 V 0 2.4 V V V ID 2 Receiver input common mode range 2.4 Supply noise voltage TA (1) Operating free-air temperature -40 25 UNIT ID 2 V 100 mVP-P 85 C By design, DVCC and AVCC are separated internally and does not matter what the difference is for XDVCC-AVCCX, as long as both are within 3 V to 3.6 V. ELECTRICAL CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise noted) PARAMETER TEST CONDITIONS SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (see Note MIN TYP MAX UNIT (1)) VIH High-level input voltage 2 VCC V VIL Low-level input voltage GND 0.8 V VCL Input clamp voltage IIN Input current (see Note ICL = -18 mA (2)) VIN = 0 V or 3.6 V DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (see Note -200 100 -1.5 V 200 A (3)) VIH High-level input voltage 2 VCC V VIL Low-level input voltage GND 0.8 V VCL Input clamp voltage ICL = -18 mA IIN Input current VIN = 0 V or 3.6 V VOH High-level output voltage IOH = -5 mA 2.2 VOL Low-level output voltage IOL = 5 mA GND IOS Output short-circuit current VOUT = 0 V -15 -47 (1) (2) (3) -0.62 -1.5 V 200 A 3 VCC V 0.25 0.5 V -85 mA -200 Apply to DIN0-DIN9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN High IIN values are due to pull-up and pull-down resistors on the inputs. Apply to input pins PWRDN, RCLK_R/F, REN, REFCLK; apply to output pins ROUTx, RCLK, LOCK 7 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) over recommended operating supply and temperature ranges (unless otherwise noted) PARAMETER IOZ High-impedance output current TEST CONDITIONS PWRDN or REN = 0.8 V, VOUT = 0 V or VCC MIN TYP MAX -10 1 10 350 400 1.1 1.2 UNIT A SERIALIZER LVDS DC SPECIFICATIONS (apply to pins DO+ and DO-) VOD Output differential voltage (DO+)-(DO-) VOD Output differential voltage unbalance VOS Offset voltage VOS Offset voltage unbalance IOS Output short circuit current D0 = 0 V, DINx = high, PWRDN and DEN = 2.4 V IOZ High-impedance output current PWRDN or DEN = 0.8 V, DO = 0 V or VCC -10 IOX Power-off output current VCC = 0 V, DO = 0 V or VCC -20 mV 35 RL = 27 , See Figure 18 mV 1.3 V 35 mV -10 -90 mA 1 10 A 1 20 A 50 mV DESERIALIZER LVDS DC SPECIFICATIONS (apply to pins RI+ and RI-) VTH Differential threshold high voltage VTL Differential threshold low voltage IIN Input current VCM = 1.1 V -50 mV VIN = 2.4 V, VCC = 3.6 V or 0 V -10 1 15 VIN = 0 V, VCC = 3.6 V or 0 V -10 0.05 10 f = 40 MHz 40 50 f = 10 MHz 20 25 200 500 f = 40 MHz 63 75 f = 10 MHz 15 35 0.36 1 A SERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC) ICCD Serializer supply current, worst case RL = 27 , See Figure 2 ICCXD Serializer supply current, power down PWRDN = 0.8 V mA A DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC) ICCR Deserializer supply current, worst case CL = 15 pF, See Figure 3 ICCXR Deserializer supply current, power down PWRDN = 0.8 V, REN = 0.8 V mA mA SERIALIZER TIMING REQUIREMENTS FOR TCLK over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER MIN TYP MAX UNIT 25 T 100 ns Transmit clock high time 0.4T 0.5T 0.6T ns Transmit clock low time 0.4T 0.5T 0.6T ns 3 6 tTCP Transmit clock period tTCIH tTCIL tt(CLK) TCLK input transition time tJIT TCLK input jitter 8 TEST CONDITIONS See Figure 6 150 ns ps (RMS) SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 SERIALIZER SWITCHING CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER tTLH(L) LVDS low-to-high transition time tTHL(L) LVDS high-to-low transition time tsu(DI) DIN0-DIN9 setup to TCLK th(D) DIN0-DIN9 hold from TCLK td(HZ) DO high-to-high impedance state delay TEST CONDITIONS RL = 27 , CL = 10 pF to GND, See Figure 4 RL = 27 , CL = 10 pF to GND, See Figure 7 td(ZH) DO low-to-high impedance state delay RL = 27 , CL = 10 pF to GND, See Figure 8 DO high-impedance state-to-high delay td(ZL) DO high-impedance state-to-low delay tw(SP) SYNC pulse duration tPLD Serializer PLL lock time RL = 27 , See Figure 9 andFigure 10 td(S) Serializer delay RL = 27 , See Figure 11 t(BIT) Bus LVDS bit width RL = 27 , CL = 10 pF to GND td(LZ) MIN TYP MAX 0.2 1 0.25 1 1 0 6.5 4.5 2.5 5 2.5 5 2.5 10 2.7 10 UNIT ns 6xtTCP 1026xtTCP t TCP 3 2 tCLK/12 DESERIALIZER TIMING REQUIREMENTS FOR REFCLK over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER tRFCP REFCLK period tRFDC REFCLK duty cycle tt(RF) REFCLK transition time TEST CONDITIONS MIN TYP MAX UNIT 25 T 100 ns 40% 50% 60% 3 Frequency tolerance -100 6 ns +100 ppm DESERIALIZER SWITCHING CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER tRCP Receiver out clock period tTLH(C) CMOS/TTL low-to-high transition time tTHL(C) CMOS/TTL high-to-low transition time td(D) Deserializer delay, See Figure 12 tsu(ROS) ROUT0-ROUT9 setup data to RCLK t(ROH) ROUT0-ROUT9 hold data to RCLK t(RDC) RCLK duty cycle td(HZ) High-to-high impedance state delay td(LZ) Low-to-high impedance state delay td(ZH) High-impedance state-to-high delay td(ZL) High-impedance state-to-low delay TEST CONDITIONS PIN/FREQ t(RCP) = t(TCP) See Figure 11 RCLK CL =15 pF, See Figure 5 ROUT0ROUT9,LOC K, RCLK Room temperature, 10 MHz 3.3 V 40 MHz MIN 25 RCLK ROUT0ROUT9, LOCK UNIT 100 0.7 2.5 1.1 2.5 2xtRCP + 9 2.833xtRCP + 14 2xtRCP + 6 2.833xtRCP + 10 0.5xtRCP ns -0.4xtRCP -0.5xtRCP 40% See Figure 14 MAX ns 0.4xtRCP See Figure 13 TYP 50% 60% 6.7 8 4.6 8 5.5 8 4.8 8 ns 9 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 DESERIALIZER SWITCHING CHARACTERISTICS (continued) over recommended operating supply and temperature ranges (unless otherwise specified) TEST CONDITIONS PARAMETER t(DSR1) Deserializer PLL lock time from PWRDN(with SYNCPAT) t(DSR2) Deserializer PLL lock time from SYNCPAT td(ZHL) High-impedance state-to-high delay (power up) t(RNM) Deserializer noise margin (1) (2) See Figure 15,Figure 1 6, and Note (1) PIN/FREQ MIN TYP 10 MHz (1024+26)tRFCP 40 MHz (1024+26)tRFCP 10 MHz 0.7 40 MHz 0.2 LOCK See Figure 17 and Note (2) 3 10 MHz 3680 40 MHz 1100 UNIT s ns ps t(DSR1) represents the time required for the deserializer to register that a lock has occurred upon power up or when leaving the power-down mode. t(DSR2) represents the time required to register that a lock has occurred for the powered up and enabled deserializer when the input (RI) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify deserializer PLL performance tDSR1 and tDSR2 are specified with REFCLK active and stable and specific conditions of SYNCPATs. tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur. TIMING DIAGRAMS AND TEST CIRCUITS RCLK ODD ROUT EVEN ROUT Figure 2. Worst-Case Serializer ICC Test Pattern TCLK ODD DIN EVEN DIN Figure 3. Worst-Case Deserializer ICC Test Pattern 10 MAX SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 10 pF tTLH(L) DO+ tTHL(L) RL 80% Vdiff 80% 20% 20% DO- 10 pF Vdiff = (DO+) - (DO-) Figure 4. Serializer LVDS Output Load and Transition Times Deserializer CMOS/TTL Output tTLH(C) tTHL(L) 80% 15 pF 80% 20% 20% Figure 5. Deserializer CMOS/TTL Output Load and Transition Times tt(CLK) TCLK tt(CLK) 90% 10% 3V 90% 10% 0V Figure 6. Serializer Input Clock Transition Time tTCP 1.5 V TCLK 1.5 V For TCLK_R/F = Low 1.5 V th(DI) tsu(DI) DIN [9:0] 1.5 V Setup Hold 1.5 V Figure 7. Serializer Setup/Hold Times 11 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 Parasitic Package and Trace Capacitance 3V DEN 1.5 V 1.5 V 0V td(ZH) td(HZ) 13.5 DO+ VOH 50% 50% 1.1 V 1.1 V DO- DO 13.5 DEN td(ZL) td(LZ) 1.1 V 50% 50% VOL Figure 8. Serializer High-Impedance-State Test Circuit and Timing PWRDN 2V 0.8 V td(HZ) or td(LZ) 1026 Cycles TCLK td(ZH) or td(ZL) t(PLD) DO 3-State 1026 Cycles Output Active 3-State SYNC Pattern DEN = High tw(SP) SYNC 1.5 V 1.5 V Figure 9. Serializer PLL Lock Time and PWRDN High-Impedance-State Delays 12 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 REN PWRDN TCLK tw(SP) SYNC1 or SYNC2 DO DATA SYNC Pattern TCLK SYNC1 or SYNC2 tw(SP) Min. Timing Met DO DATA SYNC Pattern Figure 10. SYNC Timing Delays DIN DIN0 - DIN9 SYMBOL N DIN0 - DIN9 SYMBOL N+1 td(S) TCLK Timing for TCLK_R/F = High Start Stop Start Bit D00 - D09 SYMBOL N-1 Bit Bit D00 - D09 SYMBOL N Stop Bit DO Figure 11. Serializer Delay 13 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 Start Bit D00 - D09 SYMBOL N Stop Start Bit Bit D00 - D09 SYMBOL N+1 Stop Start Bit Bit D00 - D09 SYMBOL N+2 Stop Bit RI 1.2 V 1V tDD RCLK Timing for TCLK_R/F = High ROUT ROUT0 - ROUT9 SYMBOL N-1 ROUT0 - ROUT9 SYMBOL N ROUT0 - ROUT9 SYMBOL N+1 Figure 12. Deserializer Delay tLow tHigh RCLK RCLK_R/F = Low tHigh tLow RCLK RCLK_R/F = High tROH tROS ROUT [9:0] 1.5 V Data Valid Before RCLK Data Valid After RCLK 1.5 V Figure 13. Deserializer Setup and Hold Times 7 V(LZ/ZL), Open (HZ/ZH) VOH 500 450 REN Scope 1.5 V 1.5 V VOL td(LZ) 50 VOL + 0.5 V td(ZL) VOL + 0.5 V VOL ROUT[9:0] td(HZ) td(ZH) VOH VOH - 0.5 V Figure 14. Deserializer High-Impedance-State Test Circuit and Timing 14 VOH - 0.5 V SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 PWRDN 2V 0.8 V REFCLK 1.5 V tDSR1 DATA RI Not Important td(ZHL) LOCK SYNC Patterns 3-State 3-State td(ZH) or td(ZL) ROUT[9:0] td(HZ) or td(LZ) 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State RCLK_R/F = Low REN Figure 15. Receiver LVDS Input Skew Margin 15 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 3.6 V 3V VCC 0V PWRDN 0.8 V REFCLK tDSR2 DATA 1.2 V RI Not Important 1V SYNC Patterns LOCK 3-State td(ZH) or td(ZL) ROUT[9:0] td(HZ) or td(LZ) 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State REN Figure 16. Deserilaizer PLL Lock Time From SyncPAT 1.2 V VTH RI VTL 1V tDJIT tDJIT tRNM tRNM tSW Ideal Sampling Position tSW: Setup and Hold Time (Internal Data Sampling Window) tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK tRNM: Receiver Noise Margin Time Figure 17. Receiver LVDS Input Skew Margin 16 SN65LV1021 SN65LV1212 www.ti.com SLLS526G - FEBRUARY 2002 - REVISED DECEMBER 2005 DO+ RL 10 DIN Parallel-to-Serial DO- > TCLK VOD = (DO+) - (DO-) Differential Output Signal Is Shown as (DO+) - (DO-) Figure 18. VOD Diagram 17 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LV1021DB ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1021DBG4 ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1021DBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1021DBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1212DB NRND SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1212DBG4 NRND SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1212DBR NRND SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1212DBRG4 NRND SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LV1021DBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1 SN65LV1212DBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LV1021DBR SSOP DB 28 2000 346.0 346.0 33.0 SN65LV1212DBR SSOP DB 28 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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