GENERALDESCRIPTIONFEATURES
TYPICALAPPLICATION
FUNCTIONALBLOCK DIAGRAM
This coreisaCMOSquad-channel10bit
75MSPS D/Aconverterforgeneral&video
applications.The dac1350x coreis
implemented inthe Samsung 0.18um3.3V
CMOSprocess.Digital inputsarecoded as
straightbinary.Each dac channel includes
dependentpowerdowncontroland the
abilitytosense outputload.An
external(optional)orinternal0.7Vreference
voltage (VREFOUT)and a single external
resisterdefine the full-scale outputcurrent
together.Itusesthe two architecture of
current-segmentand binary-weighted.
•Maximumconversion rateis 75MSPS
•+3.3VCMOSmonolithic construction
• ±1LSBdifferential linearity(max)
• ±2LSBintegral linearity(max)
•Externalorinternalvoltagereference
(Including Band GapReference Block)
•10-Bitparalleldigital input
•DAC auto-load detection circuitry
•Temperature:0~70°C
•EachchannelPower_Down
•PowerDumpMode
•High Definition Television(HDTV)
•High Resolution ColorGraphics
•ImageProcessing
Ver 1.5(Apr.2002)
NoresponsibilityisassumedbySECforitsusenor forany infringementsof
patentsorother rightsofthird partiesthatmayresult fromitsuse.The
contentofthisdatasheet is subject tochangewithoutany notice.
10BIT75MSPSQuad-DAC DAC1350X
SAMSUNG ELECTRONICSCo.LTD1/15
DLDSEL[1:0]
AVDD33A
AVSS33A
AVDD33D
AVSS33D
AVDD18D
Band gap reference
generator
Auto-load
Detect
digital
decode
binary
LSBs
segmented
MSBs
digital
decode
binary
LSBs
segmented
MSBs
digital
decode
binary
LSBs
segmented
MSBs
digital
decode
binary
LSBs
segmented
MSBs
CCOMP
VREFOUT
VBIAS
CLK
DTOUT
DACPRE
DATA0[9:0]
PDDAC[0]
DATA1[9:0]
PDDAC[1] DATA2[9:0]
PDDAC[2]
DATA3[9:0]
PDDAC[3]
IOUT0 IOUT1 IOUT2 IOUT3
BGPD
DACLP[0]
DACLP[1] DACLP[2]
DACLP[3]
IRSET
SEC ASIC
DAC1350X
10BIT75MSPSQuadDAC
ANALOG
NAMEI/
OI/OPAD PIN DESCRIPTION
INPUTS
PDDAC[3:0]DIpicc_abb IndividualDACpowerdowncontrol.
Whenactivated(high),the corresponding DACisdisabled.
DACLP[3:0]DIpicc_abb Lowpowercurrentdumping mode controlforeachDAC.Whenselected
(high enableslowpowermode)the corresponding DACwill run at
reduced powerwithaslight loss in performance.
CLKDIpicc_abb DACmasterclock.Inputdatais sampledwiththerising edgeofCLK.
DACPREDIpicc_abb
ControlstrobefortheDACauto-load detection comparator.When
DACPREtransitionshigh-to-low,the auto-load detectcircuit evaluatesits
selectedinput.Appropriatesettling timemustbe allowed beforethe
comparatoroutput(DTOUT)isused.When notused,DACPREshould
belefthigh.
DATA0[9:0]
DATA1[9:0]
DATA2[9:0]
DATA3[9:0]DIpicc_abb 10-bit straightbinary digital inputforeachDACchannel.
BGPDDIpicc_abb PowerdowncontrolforBandgapand all quadDACs.Ahigh level
disablesall quadDACsplusthebandgapreference regardless ofthe
statesofPDDAC0,PDDAC1,PDDAC2,PDDAC3
DLDSEL[1:0]DIpicc_abb Selection controlforexternalDACauto-load detection.Enableofload
for IOUT0is selectedLDSEL[1:0]="00",IOUT2isDLDSEL[1:0]="01",
IOUT1isDLDSEL[1:0]="10",IOUT3isDLDSEL[1:0]="11"
OUTPUT
DTOUTDO pot8_abb Comparatoroutputfordetection of resistiveloadatDACoutput.Alow
at thedetectoutput indicatesthat theoutputvoltageoftheselected
channel isabove0.53Vand thereforethatno loadisattached.
IOUT0
IOUT1
IOUT2
IOUT3
AO phoa_abb Analog CurrentOutputforeach ofthefourDACs
REFERENCES
CCOMPABphoa_abb Connectexternal0.1uFcaptoAVDD33A.
IRSET ABphoa_abb Externalresistor fromthisnodetoAVSS33Adefinesthefull scale
outputcurrentfortheDACs.
VBIASABphoa_abb Connectexternal0.1uFcapand 100ohmresistortoAVDD33A.
VREFOUTABphoa_abb internal/externalvoltagereference output
PIN CONFIGURATION
2/15
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DAC1350X
10BIT75MSPSQuadDAC
ANALOG
NAMEI/OI/OPAD PIN DESCRIPTION
POWER
AVDD33AAPvdd3t_abb Analog Power(NEEDS3PIN)
AVSS33AAG vss3t_abb Analog Ground (NEEDS3PIN)
AVDD33DDPvdd3t_abb DigitalPower
AVSS33DDG vss3t_abb DigitalGround
I/OTYPE ABBR.
•AI:Analog Input
•DI:DigitalInput
•AO :Analog Output
•DO :DigitalOutput
•AB:Analog Bidirectional
•DB:DigitalBidirectional
•AP:Analog Power
•AG :Analog Ground
•DP:DigitalPower
•DG :DigitalGround
3/15
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DAC1350X
10BIT75MSPSQuadDAC
ANALOG
CORECONFIGURATION
DATA0[9:0]
DATA2[9:0]
DAC1350X
CCOMP
VREFOUT
IRSET
DATA1[9:0]
AVDD33A
DATA3[9:0]
AVSS33A
AVDD33A
AVSS33A
AVDD33A
AVSS33A
AVDD33D
AVSS33D
IOUT0
IOUT1
IOUT3
IOUT2
VBIAS
PDDAC[3:0]
DACLP[3:0]
CLK
DACPRE
BGPD
DLDSEL[1:0]
DTOUT
AVDD33A
AVDD18D
4/15
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DAC1350X
10BIT75MSPSQuadDAC
ANALOG
ABSOLUTEMAXIMUMRATINGS
CHARACTERISTICSYMBOLVALUEUNIT
SupplyVoltageAVDD33A-AVSS33A
AVDD33D-AVSS33D-0.5~4.5V
Voltageon Any DigitalPinCLKAVSS33D-0.3to
AVDD33D+0.3V
StorageTemperatureRangeTstg-45 ~125 ºC
NOTES
1.ABSOLUTEMAXIMUMRATINGspecifiesthe valuesbeyond whichthe devicemaybe
damaged permanently.ExposuretoABSOLUTEMAXIMUMRATINGconditionsfor
extended periodsmayaffectreliability.Eachcondition value isapplied withthe other
values keptwithinthe following operating conditionsand function operation under
anyof theseconditionsisnotimplied.
2.All voltagesaremeasured withrespect toGND unless otherwisespecified
3.Applied voltage mustbe limited tospecified range.
RECOMMENDEDOPERATINGCONDITIONS
CHARACTERISTICS SYMBOLMINTYPMAX UNIT
Operating SupplyVoltageAVDD33D,AVDD33A3.1 3.3 3.5V
DigitalInputVoltageHigh VIH0.7*VDD 2.5-V
DigitalInputVoltageLow VIL-0.0 0.3*VDD V
Operating TemperatureRangeTopr0 25 70 ºC
OutputLoad(effective)RL-37.5-Ω
Reference Load(effective)ResistorRset-570 -Ω
InternalReference VoltageVrefout0.63 0.7 0.77 V
DataInputSetup TimeTS4- - ns
DataInputHoldTimeTH1- - ns
Zero_levelVoltageVOZ-5 0 +5mV
IRSET CurrentIREF1.0 1.22 1.5mA
NOTES
It is stronglyrecommended thatall the supplypins(AVDD33A,AVDD33D)be powered from
the samesource and all the ground pins(AVSS33A,AVSS33D)avoid powerlatch-up.
5/15
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10BIT75MSPSQuadDAC
ANALOG
DC ELECTRICALCHARACTERISTICS
NOTES
1.ConverterSpecifications(unless otherwisespecified):AVDD33A=AVDD33D=3.3V
AVSS33A=AVSS33D=GND,0°C<Temperaturerange <70°C,Rset=570 [ohm],
Rload1=Rload2=Rload3=Rload4 37.5 ohmresistorareconnected to analog ground (AVSS33A).
CCOMP=0.1uFcapacitoris connected to analog power(AVDD33A).
VBIAS =0.1uFcapacitorinseries100ohmresistoris connected to analog power(AVDD33A).
AC ELECTRICALCHARACTERISTICS
NOTE
-The above parametersare not tested through the temperaturerange,but these are guaranteed overthe
full temperaturerange.
-DACtoDAC Cross-talkismeasured byholding one DAChigh whilethe otherthree aremaking lowto
high and high tolowtransitions.
CharacteristicsSymbolMinTypMax Unit
Resolution - - - 10 Bits
Full ScaleCurrentperChannelIfs33 34.8 36.5mA
DifferentialLinearityErrorDLE -1.0+0.4+1.0LSB
IntegralLinearityError ILE -2.0+1.5 ±2.0LSB
Monotonicity-Guaranteed-
OutputCompliance VOC0-+1.4V
PowerDissipation PDISS -50 100 uA
CharacteristicsSymbolMinTypMax Unit
MinimumdelayfromSEL[1:0]transition to
PREtransition lowTselL100 - - ns
MinimumdelayfromDACPREtransition
lowto validDTOUToutputTDET_VAL100 - - ns
MinimumPulsewidthlowforPRE TSPWL200 - - ns
DACtoDACMismatchmm -2.5-2.5%
DACtoDACMismatchforany PDcase.mm -2.5-2.5%
Cross Talk1XTALK- -15 -10 dB
PowerSupplyRejection RatioPSRR -40 -45 -dB
Conversion RateFCON 75 30 -MHz
Analog OutputDelayTd-10 -ns
Analog OutputRiseTimeTr - 1-ns
Analog OutputFall TimeTf - 1-ns
Analog OutputSettling TimeTset-33 -ns
Clock&DataFeed-through FDTHR25 30 -dB
Signal-to-NoiseRatioSNDR40 47 -dB
TotalHarmonicDistortion THD 45 50 -dB
GlitchImpulseGl-±100 ±200 pv*sec
PipelineDelayTop -0.5-CLK
SupplyCurrentIs-150 200 mA
6/15
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10BIT75MSPSQuadDAC
ANALOG
FUNCTION DESCRIPTION
Thisisquad 10bit 75MSPS digital toanalog
data converterand usescurrent-segment
architecturefor4-bitsinMSBsidesand
binary-weightedarchitecturefor6-bitsinLSB
sides.Itcontainsof1'st latch block,decoder
block,2'nd latch block,OPAblock,CM
(currentmirror) block,BGR(Band Gap
Reference)block,Auto-load detectblockand
analog switch block,etc.Thiscoreusesreference
currentwhich decidethe1LSBcurrentby
dividing thereference currentby 32times.Sothe
reference currentmustbe constantand it can be
constantby using OPAblockwith high DCgain.
Themostsignificantblock ofthiscoreisanalog
switch blockand it mustmaintaintheuniformity
ateachswitch,solayoutdesignermustcareof
it.And morethan 90%ofsupplycurrent is
dissipatedatanalog outputside.And it uses
samsung standardcell asall digitalcell oflatch,
decoderand buffer,etc.And toadjustfull
currentoutputrange,you mustdecidetheRset
value(connectedtoIRSET pin)and.Itsvoltage
outputca n beobtained by connect ing
RL1(connectedtoIOUT0 pin)and RL2(connected
toIOUT1 pin),RL3(connectedtoIOUT2 pin)
and RL4(connectedtoIOUT3 pin) Itsmaximum
outputvoltagelimit isCompliance voltage.So
you mustdecidetheRL[4:1],VREFOUTand
Rsetcarefully not toexceedtheoutputvoltage
limit.ItcontainsPDDAC[3:0]pinsfor
power-saveofeachchanneland BGPDfor
power-downmodeofall blocks.Eventhough
oneortwo outof4channelsenterpower-save
mode,thereference block(OPAblock,CMblock,
BGRblock)is still alive,but ifBGPDis
activated(high),thenall blocksofthiscoreis
disableregardless ofPDDAC[3:0],soat thiscase
supplycurrent isalmost justabout thesumof
leakage.You cantchecktheBGR'soutput
voltageby checking theVREFOUTpin.
Theusercan detect thepresence ofanexpected
loadoneachDACoutputby configuring the
DACdigital inputs suchthat thedetection
comparatorthreshold(0.53V)isauseful
thresholdforpresence ofloadresistance.Set
DLDSEL[1:0]toselect the appropriateDAC
output.Transition PREtolow,wait for
settling DTOUTvalue and returnPREbackto
high.
TheIRSET pincreatesa+0.7[V]DCreference
thatcan beforcedwithanexternalreference
voltagepinVREFOUT.Thisvoltagewhen
combinedwiththe externalresistorattachedto
theIRSET pinsetstheoutputcurrentrange
forall quadDACs.Thefollowing example
showshowtocreatea1Vpk-pk outputfora
100 IRENTSCsignal.Any other required
variationscaneasily be calculatedfromthe
suppliedequations.Pleaserememberthat these
areidealequations,themismatchtolerances
fromthedatasheetshould betakeninto
accountforany calculations.
The<figure1>diagramshowsatypical
relationship betweenDACinputand voltage
output.
The<figure2>diagramshowsthebasic
bias-generatorand analog currentswitch.
FromthisdiagramthenumberofDACcodes
fora1Vdeltaoutput is:
C100 =808 -10 =798
1V
808
10
DAC code
Input
An example 10-bit DAC relationship
input code verse output level
<figure 1>
7/15
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DAC1350X
10BIT75MSPSQuadDAC
ANALOG
<figure 2>
If astandard doublyterminated75Ohmlineis
assumed:
V100 1
I100 =-------- =--------- =26.666mA
RLOAD 37.5
Therelationship betweentheIRreference current
and DACoutputcurrent is shown below.
IR=32 LSB
Fromthepreviousequation wehave:
IRSET 0.7V
RSET =--------- =------------- =654Ω
IR1.069mA
Summation ofall equationsgives:
IRSET *C100 *RLOAD
RSET =------------------------------
32*V100
Formostvideoapplicationsanexternalresistor
of649Ω(+/−1%)would beselectedwhen
driving doublyterminatedloads(37.5Ω),and
anexternalresistorof1.3KΩ(+/−1%)would
beselectedwhen driving loadsof75Ω,in
orderto have798 DACcodescorrespond toa
1Vdeltaoutputvoltageswing.ThentheDAC
output levelsand the associatedcodesare as
shown below.
Table1:Summary ofDACVoltage and Codes
SignalLevelCVBS/LUMA
DAC CodeIREValueDAC Voltage
Max output1023 137.2 1.282V
100%White810 100 1.015V
Black 282 7.37 353mV
Sync12 -40 15mV
White-Black 570 100 714mVdelta
White-Sync798 140 1Vdelta
Colorburst228 40 285mVdelta
DACvoltagesassumethestandard 140 IRE=
1V.Numbers shownareforNTSCtypevideo
withapedestal.
Reference
Generator
CCOMP
IREF
Current for
1 LSB
External
resistor
IR
8/15
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DAC1350X
10BIT75MSPSQuadDAC
ANALOG
TIMINGDIAGRAM
NOTES
1.The BehavioralModeling isprovided byVerilog
2.Outputdelay(Td)measured fromthe 50%pointof the rising edge ofCLKtothe full scaletrasition
3.Settling time(Tset)measured fromthe 50%pointof full scaletransition tothe outputremaining
within±1LSB iteration.
4.Outputrising(Tr)/falling(Tf)timemeasured between the 10%and 90%pointsof full scaletransition.
5.Anypower_down doesn'tneed clock signal.
6.PDDAC#makesthe channeldownrespectivelywhen itishigh.
7.PDDAC# have absolutelyno relationsamong them.
8.BGPDmakesall of the blocks disableregardless ofPDDAC#.
9.The minimumPulseWidth LowofBGPDshouldbelongerthan 500us.
10.The minimumPulseWidth LowofPDDAC#shouldbelongerthan 50us.
11.The minimumPulseWidth LowofBGPDand PDDAC#shouldbelongerthan 20ns.
9/15
Analog
Output
CLK
Digital
Input D (1)
td
DI (2) DI (3) DI (4)
1/2 CLK PIPELINE DELAY
DI (5)
AO (1) AO (2) AO (3)
TselLTSPWL
Tdet_val
DLDSEL[1:0]
PRE
DETECT
DAC0
DAC0'sload detect
DATA#[9:0]
IOUT(voltagemeasure)
PDDAC#
data#(1111111111)
Tpn Tpf
0V
Vout(pp)
Analog outputDelay
Load detectiontiming
Power Downtiming
SEC ASIC
DAC1350X
10BIT75MSPSQuadDAC
ANALOG
CORE EVALUATIONGUIDE
LOCATION DESCRIPTION
Cc0.1µF
Ct10µF
RSET 570Ω
RL1/RL2/RL3/RL437.5Ω
*You mustusemorethantwo 3PADsforAVDD33Abcauseit'scurrent ismorethanabout150mA.
SELECT
TESTPATH
HOST
DSP
CORE
10
10
10
10
MUX
IOUT0
RL1RL2
dac1350x
DATA0[9:0]
VREFOUT
RSET
Cc
CCOMP
AVDD33A
CLK
CLK(75MHz)
AVDD33D
AVSS33D
3.3V
L2
Ct
+
AVDD33A
AVSS33A
3.3V
L1
Ct
+
CcCc
10
10
10 10 10 10
IOUT2
IOUT3
RL4RL5
DTOUT
10 /15
DATA0[9:0]
DATA0[9:0]
DATA0[9:0]
IOUT1
IRSET
0.7V
DACLP[3:0]
AVDD33A
AVSS33A
3.3V
L1
Ct
+
Cc
AVDD33A
AVSS33A
3.3V
L1
Ct
+
Cc
PDDAC[3:0]
BGPD("0"normaloperation)
DACPRE
DLDSEL[1:0]
Cc
VBIAS
AVDD33A
AVDD33A
100Ω
SEC ASIC
DAC1350X
10BIT75MSPSQuadDAC
ANALOG
1.ABOUT TESTABILITY
If you want totestitover full specificationsvia all channel inmainchip(that is,whenit isused
asablock ofmainchip)you mustadd many pins(for60pinsofdigital inputs,6pinsof
analog outputs,etc)at themainchiptotest thisDACblock.Butusuallyit isnearlyimpossible
'causethetotalnumberofpinsatmainchipislimited.Somore efficientmethod fortesting
thisDACblockisneeded.Weoffertwowaysoftesting efficiently here asareference.
Butrememberthisisnot thebest thing.You cantestitby yourowntesting method.
2.FIRSTMETHOD OFTESTABILITY
Thefirstwayisadding onlyextra10PADsfor10bit paralleldigital inputsand 3PADsfor
channelselecting and pathselecting.You cancheck quadchannelsoneby one,that isyou
cantestonly one channelatonetime.Thereforeyou cantestall three channelsby turn
butcannotcheckall channelatonetime.And thismethod needsextraMUX and
switch blocksfortesting.Furthermorewe canassure all channelsby testing only one channel
because all thequadchannelshavesame architecture and sharethesame analog reference
block(OPAMP,CM,BGR).Thischaracteristicmakesit simpletotest thisDACblock(whenit is
embeddedinmainchip)by adding another10PADsforparalleldigital inputsand 3PADsfor
selecting one channelanalog switch block ofDACoutofthree channels.
3.SECOND METHOD OFTESTABILITY
If above extra13PADsareburden on you,then you cantest it by this second method to
reduce the extraPADsfortesting.What isdifferentfromabovemethod isthat thisway needs
only2extraPADs(onefor1bit serialdigital inputand theother forclocksignal),butyou must
insertextraserial to parallelconverterblockforconverting 1bit 10timeshigh speed digital input
to 10bit paralleldigital inputs.And thisblockmay needconsiderable area.And thismethod also
needsextra3PADsforchannelselecting and pathselecting.
4ANALYSIS
Thevoltage appliedtoVREFOUTismeasuredatIRSET node.And thevoltagevalue
isproportionedtothereference currentvalueof resistorwhichisconnectedto
IRSET node.So you canestimatethefull scale currentvalueby measuring the
voltage,and checktheDCcharacteristicsoftheOPAMP.For reference,as
VBIASvoltage appliedtoVREFOUTpinisgivenatIRSET node,the currentflowing through
RSET resistor(connectedtoIRSET pin)isgivenasVREF/RSET.
If thevoltage appliedtoVREFOUTpinisnotsamewithIRSET node,you cansay
"ThisDACchip doesnotwork properly",becausetheinternalOPAMPblock
makesthetwo nodevoltage(IRSET pin,VREFOUTpin)equal.And you haveto
checktheCCOMPnodetosee thedesired voltageon it.If thedesired
voltageisnotmeasured,you canchecktheDACoutputby appling a
desired voltagetotheCCOMPpininstead ofcompensation capacitordirectly.
If you useinternalreference voltage(BGR'soutputvoltage)instead ofexternal
Vbiasby setting theBGRSWlow,you canchecktheBGR'soutputby checking
theVBIASpin voltage.
11 /15
SEC ASIC
DAC1350X
10BIT75MSPSQuadDAC
ANALOG
PHANTOMCELL INFORMATION
PinNamePinUsagePinLayoutGuide
AVDD33AExternal-Maintainthelargewidth oflines
asfarasthepads.
-place theportpositionsto
minimize thelength ofpower
lines.
-Do notmergethe analog powers
withanotherpower fromother
blocks.
-Usegood powerand ground
source on board.
AVSS33AExternal
AVSS33DExternal
AVDD33DExternal
IRSET External
-Maintainthelargerwidthand the
shorterlengthasfarasthepads.
-Separatefromall otherdigital
lines.
VREFOUT External
VBIASExternal
CCOMPExternal
IOUT0External
IOUT3External
IOUT2External
IOUT1External
DTOUT External/Internal
-Separatedfromthe analog clean
signalsifpossible.
-Do notexceedthelength by
1,000um.
DLDSEL
[1:0]External/Internal
BGPDExternal/Internal
CLKExternal/Internal
DACPRE External/Internal
DACLP[3:0]External/Internal
PDDAC[3:0]External/Internal
DATA3[9:0]External/Internal
DATA2[9:0]External/Internal
DATA1[9:0]External/Internal
DATA0[9:0]External/Internal
dac1350x
10bit75MSPSQuad-DAC
DACPRE
BGPD
-Pinsofthe core can be assignedexternally(Packagepins)orinternally(internalports)depending
on design methods.
Theterm"External"impliesthat thepins should be assignedexternallylikepowerpins.
Theterm"External/internal"impliesthat the applicationsofthesepinsdepend on theuser.
DTOUT
DLDSEL[0]
CLK
AVDD18D
DATA1[9]
DATA1[0]
PDDAC[1]
DACLP[1]
DACLP[0]
PDDAC[0]
DATA0[1]
DATA0[9]
DLDSEL[1]
DATA2[9]
DATA2[0]
PDDAC[2]
DACLP[2]
DACLP[3]
PDDAC[3]
DATA3[0]
DATA3[9]
VREFOUT
AVSS33D
IRSET
AVDD33D
AVSS33A
VBIAS
CCOMP
IOUT0
IOUT1
AVDD33A
AVSS33A
AVDD33A
IOUT2
IOUT3
AVSS33A
12 /15
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DAC1350X
10BIT75MSPSQuadDAC
ANALOG
PC BOARD LAYOUTCONSIDERATIONS
♦PCBoardConsiderations
Tominimize noiseon thepowerlinesand theground lines,thedigital inputs
needto beshieldedand de-coupled.Thistrace length between groupsofvdd
(AVDD33A,AVDD33A)pins shortaspossiblesoastominimize inductiveringing.
♦SupplyDe-coupling and Planes
Forthede-coupling capacitorbetweenthepowerline and theground line,
0.1µFceramic capacitorisusedin parallelwitha10µFtantalumcapacitor.
Thedigitalpowerplane(AVDD33A)and analog powerplane(AVDD33A)are
connectedthrough aferritebead,and alsothedigitalground plane(AVSS33A)
and the analog ground plane(AVSS33A).Thisferritebeadshould belocated
within 3inchesofthedac1350x The analog powerplanesuppliespowerto
thedac1350x ofthe analog outputpinand related devices.
♦Analog SignalInterconnect
Tominimized noisepickup and reflectionsduetoimpedance mismatch,thedac1350x
should belocatedasclose aspossibletotheoutputconnector.
ThelinebetweenDACoutputand monitorinputshouldalso beregardedasa
transmission line.Duetothefact,it cancauseproblemsintransmission line
mismatch.Asasolution totheseproblems,thedouble-termination methodsused.
By using this,bothendsofthetermination linesarematched,providing anideal,
non-reflectivesystem.
CORELAYOUTGUIDE(OPTIONAL)
LayoutDAC core replacement
•It isrecommendedthatyou usethickanalog powermetal.whenconnecting toPAD,thepathshould
bekeptas shortaspossible,and usebranchmetal toconnect tothe centerofanalog switch block.
•It isrecommendedthatyou usethickanalog outputmetal(at leastmorethan 25µm)whenconnecting
toPAD,and alsothepathlengthshould bekeptas shortaspossible.
•Digitalpowerand analog powerareseparately used.
•Whenit isconnectedto otherblocks,it mustbedoubleshielded using N-well and P+activeto
removethesubstrate and coupling noise.Inthatcase,thepowermetalshould be connectedtoPAD directly.
•Bulk powerisusedtoreduce theinfluence ofsubstratenoise.
•You mustusemorethantwo pinsforAVDD33Abecauseit requiremuchcurrentdissipation(about93mA)
•It isrecommendedthatanalog metal line(including IRSET,VREFOUT,IOUT0,IOUT1,IOUT2,IOUT3)and analog
powermetal lineshould belayoutalone and should notmixedwith othernoisy digitalmetal lines.
•If thiscoreisusedasafunction blockinlargermainchip,you canjoin digitalpowermetalofthiscore
withthemain digitalpowerinstead ofusing newdigitalpowerpadforthiscore.Butyou mustusenew
analog powerpadforthe analog powerofthiscore.
13 /15
SEC ASIC
DAC1350X
10BIT75MSPSQuadDAC
ANALOG
FEEDBACK REQUEST
We appreciateyourinterest in outproducts.If you havefurtherquestions,pleasespecifyin
the attachedform.Thank you verymuch.
DC /AC ELECTRICALCHARACTERISTIC
CharacteristicsMinTypMax UnitRemarks
SupplyVoltageV
Powerdissipation mW
Resolution Bits
Analog OutputVoltageV
Operating Temperature°C
OutputLoadCapacitorµF
OutputLoadResistorΩ
IntegralNon-LinearityErrorLSB
DifferentialNon-LinearityErrorLSB
MaximumConversion RateMHz
VOLTAGEOUTPUTDAC
Reference VoltageTOP
BOTTOMV
Analog OutputVoltageRangeV
DigitalInputFormatBinaryCodeor2'sComplementCode
CURRENTOUTPUTDAC
Analog OutputMaximumCurrentmA
Analog OutputMaximumSignalFrequencyMHz
Reference VoltageV
ExternalResistor forCurrentSetting(RSET)Ω
PipelineDelaysec
14 /15
-Do you want toInteralReference Voltage(BGR)?
-Which do you want toSerialInputTYPEorparallelInputTYPE?
-Do you need 3.3v and 5v powersupplyin yoursystem?
-Howmany channelsdo you need?
SEC ASIC
DAC1350X
10BIT75MSPSQuadDAC
ANALOG
HISTORY CARD
VersionDateModifiedItemsComments
Ver1.0Newlyregisteredbycircuit designerKwang-Hee Lee
Ver1.1'01.08.05 pinmap,absolutemaximumpower,operating power range.
Ver1.2'01.08.28 Typo correction.
Ver1.3'01.10.20
- IOUT1,IOUT2,IOUT3,IOUT4-->IOUT0,IOUT1,IOUT2,IOUT3
-DACLP0,1,2,3-->DACLP[3:0]
-PDDAC0,1,2,3-->PDDAC[3:0]
- removeAVBB pin
-Connect0.1uFcap betweenVBIASand AVDD33AinCORE
APPLICATION GUIDE
-PowerportAVDD33A(3EA) -->4EA
Ver1.4'02.03.01
-Load detectselection sequence
DLDSEL(00)⇒IOUT0
DLDSEL(01)⇒IOUT2
DLDSEL(10)⇒IOUT1
DLDSEL(11)⇒IOUT3
page2
Ver1.5'02.04.19
-Add Newitem
-DACtoDAC Cross talk
-DACtoDACmismatching (±2.5%)
-DACtoDACmismatchforany powerdownsignal(±2.5%)
-Recommend connectresistor(100ohm)toVBIASpinto
AVDD33Ainseriescapacitor(0.1uF)
-Recommend resistor(Rset=570ohm) for IFS =34.8mA
-PSRR =-40dB(min)
-voltagereference variance 0.7V±10%
Ver1.6'02.04.30 -Add NewItem
SNDR
THD
15 /15
