JE-1501-8664-9 - 3M - Datasheet.Live

 2005 Microchip Technology Inc. DS30492B-page 1

PIC16F7X7

This document includes the programming specifications

for the follow ing devices:

1.0 PROGRAMMING PIC16F7X7

DEVICES

The PIC16F7X7 devices are programmed using a

serial m ethod. The Seri al mode allow s these devic es to

be progra mmed wh ile in the users’ syst em, allowi ng for

increased design flexibility. This programming

specification applies to PIC16F7X7 devices in all

packages.

1.1 Hardware Requirements

The PIC16F7X7 requires two programmable power

supplies, one for VDD (2.0V to 5.5V) and the other for

VPP of 12.75V to 13.25V. Both supplies should have a

minimum resolution of 0.25V.

1.2 Programming Mode

The Programming mode for the PIC16F7X7 allows

programming of user program memory, special

locations used for ID, and the Configuration Word.

Pin Diagra ms

•PIC16F737 •PIC16F767

•PIC16F747 •PIC16F777

T ABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F7X7

Pin Name During Programming

Function Pin Type Pin Description

RB6/KBI2/PGC Clock I Clock Input

RB7/KBI3/PGD Data I/O Data Input/Output

MCLR/VPP/RE3 Mode Control P Program Mode Select

VDD VDD P Power Supply

VSS VSS P Ground

Legend: I = Input, O = Output, P = Power

PIC16F737/767

14 15

MCLR/V

/RE3

RA0/AN0

RA1/AN1

RA2/AN2/V

REF

-/CV

REF

RA3/AN3/V

REF

RA4/T0CKI/C1OUT

RA5/AN4/LVDIN/SS/C2OUT

OSC2/CLKO/RA6

OSC1/CLKI/RA7

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/AN13/CCP3

RB4/KBI0/AN11

RB3/CCP2/AN9

RB2/AN8

RB1/AN10

RB0/INT/AN12

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

PDIP, SOIC, SSOP (28-pin)

Flash Memory Programming Specification

PIC16F7X7

DS30492B-page 2  2005 Microchip Technology Inc.

Pin Diagrams (Continued)

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/AN13/CCP3

RB4/KBI0/AN11

RB3/CCP2/AN9

RB2/AN8

RB1/AN10

RB0/INT/AN12

VDD

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/LVDIN/SS/C2OUT

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

VDD

VSS

OSC2/CLKO/RA6

OSC1/CLKI/RA7

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0

RD1/PSP1

PIC16F747/777

PDIP (40-pin)

PIC16F747/777

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF-

RA1/AN1

RA0/AN0

MCLR/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/AN13/CCP3

RB4/KBI0/AN11

NC RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

RC0/T1OSO/T1CKI

OSC1/CLKI/RA7

OSC2/CLKO/RA6

AVSS

AVDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4/LVDIN/SS/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

VSS

VDD

RB0/INT/AN12

RB1/AN10

RB2/AN8

RB3/CCP2*/AN9

* Alternate pinout for CCP2 is enabled by a fuse.

RD7/PSP7 5

QFN (44-pin)

AVDD

AVSS

 2005 Microchip Technology Inc. DS30492B-page 3

PIC16F7X7

Pin Diagrams (Continued)

PIC16F747/777

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF-

RA1/AN1

RA0/AN0

MCLR/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/AN13/CCP3

RB4/KBI0/AN11

NC RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

RC0/T1OSO/T1CKI

OSC2/CLKO/RA6

OSC1/CLKI/RA7

AVSS

AVDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4/LVDIN/SS/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

VSS

VDD

RB0/INT/AN12

RB1/AN10

RB2/AN8

RB3/CCP2*/AN9

TQFP (44-pin)

* Alternate pinout for CCP2 is enabled by a fuse.

RD7/PSP7 5

PIC16F7X7

DS30492B-page 4  2005 Microchip Technology Inc.

2.0 PROGRAM MODE ENTRY

2.1 User Program Memory Map

The user memory space extends from 0x0000 to

0x1FFF (8K), or 0x0000 to 0x0FFF (4K). Table 2-1

shows the actual implementation of program memory

in the PIC 16F7X7 family. Config uration memory be gins

at 0x2000, and continues to 0x3FFF. The PC will

increm ent from 0x0000 to 0x1FF F and wrap to 0x000 0,

0x2000 to 0x3FFF and wrap around to 0x2000 (not to

0x0000).

Once in c onfiguration m emory , t he highest bit of th e PC

stays a ‘1’, thus always pointing to the configuration

memory. The only way to point to program memory is

to reset the part and re-enter Program/Verify mode, as

des cribed in Section 2.3 “Program/Verify Mode”.

For PIC16F7X7 devices, configuration memory is

selected when the PC points to any address in the

range of 0x2000-0203F; however, only locations

0x2000 through 0x2008 are implemented. Addressing

locations beyond 0x203F will access program memory

(see Figure 2-1).

TABLE 2-1: IMPLEMENTATION OF

PROGRAM MEMORY IN THE

PIC16F7X7 FAMILY

2.2 ID Locations

A user may store identification information (ID) in four

ID locations mapped to [0x2000:0x2003]. It is

recommended that each ID location word is written as

‘11 1111 1000 bbbb’, where ‘bbbb’ is ID

information. The ID locations can be read after code

protection is enabled.

To understand the program memory read mechanism

after code protection is enabled, refer to Section 4.0

“Code Protection”. Table 4-1 shows specific

calculations and behavior for each of the PIC16F7X7

devices.

Device Program Memory Size

PIC16F737/747 0x0000-0x0FFF (4K)

PIC16F767/777 0x0000-0x1FFF (8K)

 2005 Microchip Technology Inc. DS30492B-page 5

PIC16F7X7

FIGURE 2-1: PROGRAM MEMORY MAPPING FOR PIC16F7X7 DEVICES

PIC16F7X7

4K words 8K words

Implemented Implemented

Reserved

Implemented

Reserved Reserved

Accesses

0x0040

0X0FFF

Accesses

0x0040

0X1FFF

ID Location

Reserved

Device ID

Configuration Word 1

Configuration Word 2

2000h

2001h

2002h

2003h

2004h

2005h

2006h

2007h

1FFh

3FFh

400h

7FFh

800h

BFFh

C00h

FFFh

1000h

1FFFh

2009h

2040h

3FFFh

13FFh

1400h

17FFh

1800h

1BFFh

1C00h

203Fh

2008h

PIC16F7X7

DS30492B-page 6  2005 Microchip Technology Inc.

2.3 Program/Verify Mode

The Program/Verify mode is entered by holding pins

RB6 and R B7 l ow, while rai si ng t he M C LR p in f rom VIL

to VPP. Once in this mode, the user program memory

and the configuration memory can be accessed and

programmed in serial fashion. (RB6 and RB7 are

Schmitt Trigger inputs in this mode.)

The seque nce that enters the de vice in to the Program -

ming/Verify mode, places all other logic into the Reset

state. All I/O pins are in the Reset state (high-

impedance inputs).

A device Reset will clear the PC and point to address

0x0000. The Increment Address command will incre-

ment t he PC. The Load Configura tion com mand will set

the PC to 0 x2000 . The avai lable comm ands are show n

in Table 2-2.

The normal sequence for programming two program

memory words at a time is as follows:

1. Issue t he Loa d Dat a c ommand to loa d a w ord at

the current (even) program memory address.

2. Issue an Increment Address command.

3. Load a word at the current (odd) program

memory address using the ‘Load Data’

command.

4. Issue a Begin Programming command to begin

programming.

5. Wait tprog (about 1 ms).

6. Issue an End Programming command.

7. Increment to the next address.

8. Repeat this sequence as required to write

program and configuration memory.

The alternative sequence for programming one

program memory word at a time is as follows:

1. Set a word for the current memory location using

the Load Data command.

2. Issue a Begin Programming command to begin

programming.

3. Wait tprog (about 1 ms).

4. Issue an End Programming command.

5. Increment to the next address.

6. Repeat this alternative sequence as required to

write program and configuration memory.

The address and program counter is reset to 0x0000

by resetting the device (taking MCLR below VIL) and

re-entering Programming mode. Program and config-

uration memory may then be read or verified using

the Read Data and Increment Address commands.

2.3.1 SERIAL PROGRAM/VERIFY

OPERATION

RB6 is us ed as a clock inp ut pin, and RB7 is us ed for

entering command bits and data input/output. To enter

a command, the clock pin (RB6) is pulsed six times.

Each comm and bi t i s la tch ed on t he fa ll ing edge of th e

clock (R B6), wit h the Le ast Signi ficant bi t (LSb) of the

command being input first. The data on pin RB7 needs

a minimum setup (tset1) and hold time (thold1) with

respect to the falling edge of the clock. The Read and

Load commands are specified to have a minimum delay

(tdly1) between the command and data. After this delay ,

the clock pin is cycled 16 times, with the first cycle being

a Start bit (0) and the last cycle being a Stop bit (0).

Dat a is tran s fe rre d LSb first (see Fig ur e 5-1 ).

During a read operation, the LSb will be output on pin

RB7 on the rising edge of the second clock pulse and

during a load operation, the LSb will be latched on the

falling edge of the second clock pulse. A minimum

delay (tdly2) is required between consecutive

commands (see Figure 5-2).

To allow for decoding of commands and reversal of

data pin configuration, a time separation of at least

(tdly1) is required between a command and a data

word, or another command (see Figure 5-3).

The available commands are listed below:

• Load Configuration

• Load Data for Memory

• Read Data from Memory

• Increment Address

•Begin Programming

• Bulk Erase Program Memory

• End Programming

Note: The MCLR pin should be raised from

below VIL to above the minimum VIHH

(VPP) within 100 µs of VDD rise. This

ensures that the device always enters

Programming mode before any

instructions that may be in program

memory can be executed. Otherwise,

unintended instruction execution could

occur when the INTRC clock source is

configured as the primary cloc k.

 2005 Microchip Technology Inc. DS30492B-page 7

PIC16F7X7

TABLE 2-2: COMMAND MAPPING FOR PIC16F7X7

2.3.1.1 Load Configuration

After receiving the Load Configuration command, the

PC will be set to 0x2000 and the data sent with the

command is discarded. The four ID locations and the

Config uration Wo rd can then be pro grammed using th e

normal programming sequence, as described in

Section 2.3 “Program/Verify Mode”. A description of

the me mory mapping sc hemes of the progra m memory

for norma l operation an d Configurat ion mode oper ation

is shown in Figure 2-1. After the configuration memory

is entered, the only way to get back to the user program

memory is to exit the Program/Verify Test mode by

taking MCLR low.

2.3.1.2 Load Data for Memory

The device will load in a 14-bit “data word” (LSb first)

when 16 cycl es are ap plied , as des cribed previo usly. A

timing di agram for the Loa d Data command is shown in

Figure 5-1.

2.3.1.3 Read Data from Memory

The device will transmit data bits out of the memory

(program or configuration) currently addressed by the

PC, starting with the second rising edge of the clock

input. RB7 will go into Output mode on the second

rising clock edge and will revert back to Input mode

(high-impedance) after the 16th rising edge. Data is

sent out LSb first. A timing diagram for this command is

shown in Fi gure 5-2.

If the device is code-protected, user program memory

will read all ‘0’s. Configuration memory can still be

read.

2.3.1.4 Increment Address

The PC is incremented by one. A timing diagram for

this command is shown in Figure 5-3.

2.3.1.5 Begin Progr amming

A Load Data command must be issued before

every Begin Programming command. Programming

of memory (configuration or program) will begin after

this command is received and decoded. Programming

requires (tprog) time and is terminated using an End

Programming command.

2.3.1.6 Chip Erase (Program Memory)

Erasure of configuration and program memory begins

after this command is received and decoded. The

erase sequence is self-timed and it is not necessary to

issue an End Programming command, only to wait for

the appropriate time interval (tera) for the entire erase

sequenc e, before iss ui ng ano the r comm an d.

This procedure will disable code protection (code-

protect bit = 1); however, all data within the program

memory will be erased when this command is executed

and thus, the security of the data or code is not

compromised.

2.4 Programming Algorit hm Requires

Variable VDD

The PIC16F7X7 devices use an intelligent algorithm.

The algorithm calls for program verification at VDDAPP.

The actual chip erase and programming must be done

with VDD in the VDDP range (see Table 5-1).

VDDP =VDD range required during programming

VDDAPP =VDD in the target application

Programmers must verify the PIC16F7X7 devices at

VDDAPP. Since Microchip may introduce future versions

of the PIC1 6F7X7 dev ices with a broader VDD range, it

is best that these levels are user selectable (defaults

are acceptable).

Command Mapping (LSb … MSb) Data (LSb first)

Load Configuration (Set PC = 2000h) 0000xx0, data (14), 0

Load Data for Memory 0100xx0, data (14), 0

Read Data from Memory 0010xx0, data (14), 0

Increment Address 0110xx

Begin Programming 0001xx

Bulk Erase Program Memory (Chip Erase) 1001xx

End Programming 0111xx

Note: All chip erase operations must take place

with VDD between 4.75V and 5.25V (i.e.,

VDDP).

Note: Any programmer not meeting this

requirement may only be classified as a

“prototyp e” or “develop ment” program mer ,

but not a “ prod uction quali ty” prog ramme r.

PIC16F7X7

DS30492B-page 8  2005 Microchip Technology Inc.

FIGURE 2-2: PROGRAMMING METHOD FLOWCHART (SHEET 1 OF 3)

Start

Chip Erase

pass? No

Yes

Program T wo

Locations

VPP = 12.75 to 13.25V

VDD = VDDP

All

locations

done?

Report Possible

Erase Failure.

Continue

Programming

at User ’s Option.

pass?

Load

Configuration

Report Verify

Failure

at VDDAPP

Program Tw o

ID Locations

VDD = VDDP

All

ID loc a ti o n s

done?

Yes

VPP = 12.75 to 13.25V

Yes

Verify all

Locations at

VDD = VDDAPP

Program Memo ry

(PC = 2000h)

 2005 Microchip Technology Inc. DS30492B-page 9

PIC16F7X7

FIGURE 2-3: PROGRAMMING METHOD FLOWCHART (SHEET 2 OF 3)

Done

pass? No

Yes

Load Data

fo r Memory

Report Verify

Error

Increment

Address to

Configuration

Word

Verify all

Memory Locations

AT VDD = VDDAPP

Configuration

Begin

Programming

End

Programming

Wait tprog

PIC16F7X7

DS30492B-page 10  2005 Microchip Technology Inc.

FIGURE 2-4: PROGRAMMING METHOD FLOWCHART (SHEET 3 OF 3)

Start

Load Data for

Increment

Address

Load

Configuration

Fail

All

locations

verified?

Yes

Start

Res et Devi ce,

Memory

(Even Addr ess)

Load Data for

Memory

(Odd Addr ess)

Begin

Programming

Increment

Address

End

Programming

Wai t tprog

Return

PROGRAM TWO LOCATIONS

Return

Pass

Increment

Address

Retun

match?

Does data

Yes

verified?

program

Return to

Programming

Mode memory been

Has

Read Data from

Memory

Compare Data

to Exp ec ted

Data

VERIFY ALL LOCATIONS

(VDD = VDDAPP)

 2005 Microchip Technology Inc. DS30492B-page 11

PIC16F7X7

3.0 CONFIGURATION WORD

The PIC16F7X7 devices have configuration bits in

configuration words located at 0x2007 and 0x2008.

These bi ts can be c leared (reads ‘ 0’), or left uncha nged

(reads ‘1’), to select various device configurations.

3.1 Device ID W ord

The device ID word for the PIC16F7X7 devices is

located at 2006h. The nine M ost Signi ficant bit s are th e

device ID number, while the five Least Significant bits

are the device revision number.

TABLE 3-1: DEVICE ID VALUE

Device Device ID Word (0x2006)

Dev Rev

PIC16F737 00 1011 101 n nnnn

PIC16F747 00 1011 111 n nnnn

PIC16F767 00 1110 101 n nnnn

PIC16F777 00 1101 111 n nnnn

CP CCPMX RESV –– BORV1 BORV0 BOREN MCLRE F0SC2 PWRTEN WDTEN F0SC1 F0SC0

bit 13 bit 0

bit 13 CP: Flash Program Memory Code Protect ion bits

1 = Code protection off

0 = 0000h to 1FFFh code-protected for 767, 777 and 0000h to 0FFFh for 737, 747 (all protected)

bit 12 CCPMX: CCP2 Multiplex bit

1 = CCP2 is on RC1

0 = CCP2 is on RB 3

bit 11 Reserved: Set to ‘1’ for Normal Operation

bit 10-9 Unimplemented: Read as ‘1’

bit 8-7 BORV<1:0>: Brown-out Reset Vo ltage bits

11 = VBOR set to 2.0 V

10 = VBOR set to 2.7 V

01 = VBOR set to 4.2 V

00 = VBOR set to 4.5 V

bit 6 BOREN: Brown-out Reset Enable bit

BOREN combines with BORSEN to control when BOR is enabled and how it is controlled

BOREN:BORSEN

11 = BOR enabled and always on

10 = BOR enabled during operation and disabled during Sleep by hardware

01 = BOR controlled by software bit SBOREN

00 = BOR disabled

bit 5 MCLRE: RE3/VPP/MCLR Pin Function Select bit

1 = RE3/VPP/MCLR pin function is MCLR

0 = RE3/VPP/MCLR pin function is digital input only, MCLR gated to ‘1’

bit 3 PWRTEN: Power-up T imer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 2 WDTEN: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 4, 1-0 FOSC2:FOSC0: Oscillator Selection bits

111 = EXTRC oscillator; CLKO function on OSC2/CLKO/RA6

110 = EXTRC oscillator; Port I/O function on OSC2/CLKO/RA6

101 = INTRC oscillator; CLKO function on OSC2/CLKO/RA6 and Port I/O function on OSC1/CLKI/RA7

100 = INTRC oscillator; Port I/O function on OSC1/CLKI/RA7 and OSC2/CLKO/RA6

011 = EXTCLK; Port I/O function on OSC2/CLKO/RA6

010 = HS oscillator

001 = XT oscillator

000 = LP oscillator

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F7X7

DS30492B-page 12  2005 Microchip Technology Inc.

– – – – – – – BORSEN – – – –IESOFCMEN

bit 13 bit 0

bit 13-7 Unimplemented: Read as ‘1’

bit 6 BORSEN: Brown-out Reset Software Enable bit

Refer to Configuration Word Register 1 (Register 3-1), bit 6 for the function of this bit

bit 5-2 Unimplemented: Read as ‘1’

bit 1 IESO: Internal External Switchover bit

1 = Internal External Switchover mode enabled

0 = Internal External Switchover mode disabled

bit 0 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor enabled

0 = Fail-Safe Clock Monitor disabled

Legend:

R = Readable bit W = Writa ble bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2005 Microchip Technology Inc. DS30492B-page 13

PIC16F7X7

4.0 CODE PROTECTION

Once code protection is enabled, all program memory

locations read all ‘0’s; further programming of program

memory is dis abled. ID l ocatio ns and t he Configur ation

Word may still be read and programmed (1’s to 0’s

only).

4.1 Disabling Code Protect ion

The following procedure should be performed before

any other programming is attempted. This procedure

also turns off code protection (code-protect bit = 1);

however, all program memory will be erased when

this procedure is executed an d thus, the security of

the code is not compromised.

Procedure to disable code protection:

a) Issue the Chip Erase comm and.

b) Wait for the erase cycle time (tera) to pass. The

program memory is erased, then the

configuration memory is erased.

4.2 Embedding Configurati on Word and ID Information in the HEX File

To allow po rtab ility of code, the program mer i s require d t o read the Co nfigura tion W ord and ID l ocations fr om the h ex

file , when lo ading the hex fi le. If Conf igurati on Wo rd inform ation was not pr esent in the hex file , then a simp le warning

message may be issued. Similarly, while saving a hex file, Configuration Word and ID information must be included.

An option to not include this information may be provided.

Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

PIC16F7X7

DS30492B-page 14  2005 Microchip Technology Inc.

4.3 Checksum Computation

The checksum is calculated by reading the contents of

the PIC16F7X7 memory locations and adding up the

opcodes, up to the maximum user addressable loca-

tion. Any carry bits exceeding 16 bits are neglected.

Finally, the Con figu rati on Word (appropri ate ly m as ked)

is added to the checksum. Checksum computation for

each m ember o f the PIC16F7X7 is sh own i n Table 4-1.

The checksum is calculated by summing the following:

• The contents of all program memory locations

• The Configuration Word, appropriately masked

• Masked ID locations (when applicable)

The Least Significant 16 bits of this sum are the

checksum.

Table 4-1 describes how to calculate the checksum for

each dev ice. Note th at the checks um calculation differ s

depending on the code protection setting. Since the

progra m memory locations read out dif ferently depen d-

ing on the code protection setting, the table describes

how to manipulate the actual program memory values

to simulate the values that would be read from a

protected device. When calculating a checksum of a

non-protected device, the entire program memory can

simply be read and summed. The Configuration Word

and ID locations can always be read.

TABLE 4-1: CHECKSUM COMPUTATION FOR PIC16F7X7 DEVICES

Device Code-protect Checksum Blank

Value

0x25E6 at

0x0000

and max

address

PIC16F737 OFF SUM(0000:0FFF) + (CONFIG0 & 39FF) + (CONFIG1 & 0043) 2A42 F610

ALL (CONFIG0 & 39FF) + (CONFIG1 & 0043) + SUM(IDs) 4484 1052

PIC16F747 OFF SUM(0000:0FFF) + (CONFIG0 & 39FF) + (CONFIG1 & 0043) 2A42 F610

ALL (CONFIG0 & 39FF) + (CONFIG1 & 0043) + SUM(IDs) 4484 1052

PIC16F767 OFF SUM(0000:1FFF) + (CONFIG0 & 39FF) + (CONFIG1 & 0043) 1A42 E610

ALL (CONFIG0 & 39FF) + (CONFIG1 & 0043) + SUM(IDs) 3484 0052

PIC16F777 OFF SUM(0000:1FFF) + (CONFIG0 & 39FF) + (CONFIG1 & 0043) 1A42 E610

ALL (CONFIG0 & 39FF) + (CONFIG1 & 0043) + SUM(IDs) 3484 0052

Legend: CFWD = Configuration Word

SUM[a:b] = [Sum of locations a to b inclusive]

SUM_ID = ID locations masked by 0x0F, then concatenated into a 16-bit value with ID0 as the Most

Significant nibble.

For example, ID0 = 0x01, ID2 = 0x02, ID3 = 0x03, ID4 = 0x04, then SUM_ID = 0x1234

Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]

+ = Addition

& = Bitwise AND

 2005 Microchip Technology Inc. DS30492B-page 15

PIC16F7X7

5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS

5.1 AC/DC Characterist ics

TABLE 5-1: TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE

S tandard Operating Conditions (unless othe rwis e stated)

Operati ng Temperature: +10°C ≤ TA ≤ +40°C

Operati ng Voltage: 4.5V ≤ VDD ≤ 5.5V

Characteristics Sym Min Typ Max Units Conditions/Comments

General

VDD level for read and verification VDD 2.0 —5.5 V

VDD level for programming and erasing VDDP 4.75 —5.25 V

High voltage on MCLR for chip erase

and program write operations VPP 12.75 — 13.25 V (Notes 1, 2)

MCLR rise time (VSS to VPP) for Test

mode entry tVHHR ——1.0µs

(RB6, RB7) input high level VIH10.8VDD — — V Schmitt Trigger input

(RB6, RB7) inpu t low level VIL1——0.2VDD V Schmitt Trigger input

Serial Program/Verify

Data in setup time before clock↓tset1 100 — — ns

Data in hold time after clock↓thld1 100 — — ns

Dat a i nput not driven t o next clock i npu t

(delay required between

command/data or command/command)

tdly1 1.0 — — µs

Delay between clock↓ to clock↑ of next

command or data tdly2 1.0 — — µs

Clock↑ to data out valid (during read

data) tdly3 200 — — ns

Erase cycle time tera 30 — — ms (Note 3)

Programmin g cycle time tprog 1 — 1 ms

Note 1: VPP should be current limited to about 100 mA.

2: VPP must remain above VDDP + 4.0V to remain in Programming mode, while not actually erasing or

programming.

3: The chip erase is self-timed.

PIC16F7X7

DS30492B-page 16  2005 Microchip Technology Inc.

FIGURE 5-1: LOAD DATA COMMAND MODE (PROGRAM/VERIFY)

FIGURE 5-2: READ DATA COMMAND MODE (PROGRAM/VERIFY)

FIGURE 5-3: INCREMENT ADDRESS COMMAND MODE (PROGRAM/VERIFY)

MCLR VPP

tset0

RB6

(Clock)

RB7

(Data)

Reset

tset1

thld1

tdly1

1 µs min.

Program/Verify Test Mode

tset1

thld1

100 ns min.

1 µs min.

tdly2

12 34 56

0100xx

12 34 5 15

Start Stop

100 ns min.

}

thld0

}

bit bit

MCLR VPP

tset0

RB6

(Clock)

RB7

(Data)

Reset

tdly1

1µs min.

Program/Verify Test Mode

tset1

thld1

1 µs min.

tdly2

12 34 56

0010xx

12 34 515

100 ns min.

}

tdly3

RB7 = Input RB7 = Output RB7

Inpu

thld0

Stop

bit

Start

bit

MCLR VPP

RB6

(Clock)

RB7

(Data)

Reset

tdly1

1µs min.

Program/Verify Test Mode

tset1

thld1

1µs min.

tdly2

12 3 4 56

011 xx

100 ns min.

}

Next Command

 2005 Microchip Technology Inc. DS30492B-page 17

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It i s your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIN D WHETHER EXPRESS OR IMPLIED ,

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RELATED TO THE INFORMATION, INCLUDING BUT NOT

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Microchip disclaims all liability arising from this information and

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Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

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Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving the c ode protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

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and manufacture of development systems is ISO 9001:2000 certified.

DS30492B-page 18  2005 Microchip Technology Inc.

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