19-2126; Rev 2; 11/04 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23 Features The MAX5712 is a small footprint, low-power, 12-bit digital-to-analog converter (DAC) that operates from a single +2.7V to +5.5V supply. The MAX5712 on-chip precision output amplifier provides rail-to-rail output swing. Drawing only 85A supply current at +3V, the MAX5712 is ideally suited for portable battery-operated equipment. The MAX5712 utilizes a 3-wire serial-interface that is compatible with SPITM/QSPITM/MICROWIRETM and DSP-interface standards. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers to allow direct interfacing to optocouplers. The MAX5712 incorporates a power-on reset (POR) circuit that ensures the DAC begins in a zero-volt-state upon power-up. A power-down mode that reduces current consumption to 0.3A may be initiated through a software command. Wide -40C to +125C Operating Temperature Range The MAX5712 is available in a small 6-pin SOT23 package. For dual and quad 12-bit versions, see the MAX5722 and MAX5742 data sheets. For single, dual, and quad 10-bit versions, see the MAX5711, MAX5721 and MAX5741 data sheets. The MAX5712 is specified over the automotive temperature range of -40C to +125C. Power-On Reset to 0V Applications Automatic Tuning Gain and Offset Adjustment Power Amplifier Control Process Control I/O Boards Battery-Powered Equipment VCO Control Low 85A Supply Current Ultra Low 0.3A Power-Down Supply Current Single +2.7V to +5.5V Supply Voltage Fast 20MHz 3-Wire SPI/QSPI/MICROWIRE and DSP-Compatible Serial Interface Schmitt-Triggered Inputs for Direct Interfacing to Optocouplers Rail-to-Rail Output Buffer Tiny 6-Pin SOT23 Package Three Software-Selectable Power-Down Output Impedances (100k, 1k, Hi-Z) Ordering Information PART TEMP RANGE PINPACKAGE TOP MARK MAX5712EUT-T -40C to +85C 6 SOT23-6 ABCQ MAX5712AUT-T -40C to +125C 6 SOT23-6 AAUD Pin Configuration appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. Functional Diagram VDD GND REF+ REFDAC REGISTER 12-BIT DAC MAX5712 OUTPUT BUFFER OUT 100k INPUT CONTROL LOGIC 1k POWER-DOWN CONTROL LOGIC POWER-ON RESET CS SCLK DIN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5712 General Description MAX5712 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23 ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V OUT, SCLK, DIN, CS to GND ......................-0.3V to (VDD+ 0.3V) Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 6-Pin SOT23 (derate 9.1mW/C above +70C)...........727mW Operating Temperature Range .........................-40C to +125C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.5V, GND = 0, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V. TA = +25C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 LSB STATIC ACCURACY (NOTE 1) Resolution N 12 Bits Differential Nonlinearity Error DNL Guaranteed monotonic (Note 2) Integral Nonlinearity Error INL (Note 2) 2 16 LSB Zero-Code Error OE Code = 000 0.4 1.5 % of FS Zero-Code Error Tempco Gain Error 2.3 GE Gain-Error Tempco Code = FFF hex ppm/C -3 Integral 0.26 % of FS ppm/C DAC OUTPUT Output Voltage Range No-load (Note 3) DC Output Impedance Code = 800 hex 0.8 Short Circuit Current Wake-Up Time Output Leakage Current 0 VDD VDD = +3V 15 VDD = +5V 48 VDD = +3V 8 VDD = +5V 8 Power-down mode = output high-impedance 18 V mA s 33 nA DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage VIH VDD = +3V, +5V Input Low Voltage VIL VDD = +3V, +5V 0.7 x VDD V Input Leakage Current IIN Digital Inputs = 0 or VDD Input Capacitance CIN 5 pF SR 0.5 V/s 0.1 0.3 x VDD V 1 A DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time 400 hex to C00 hex (Note 4) Digital Feedthrough Any digital inputs from 0 to VDD 0.2 nV-s Digital-Analog Glitch Impulse Major carry transition (code 7FF hex to code 800 hex) 12 nV-s 2 4 _______________________________________________________________________________________ 10 s 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23 (VDD = +2.7V to +5.5V, GND = 0, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V. TA = +25C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 V All digital inputs at 0 or VDD, VDD = +3.6V 85 150 All digital inputs at 0 or VDD, VDD = +5.5V 105 187 All digital inputs at 0 or VDD, VDD = +5.5V 0.29 1 A 20 MHz POWER REQUIREMENTS Supply Voltage Range VDD Supply Current with No-Load IDD Power-Down Supply Current IDDPD 2.7 A TIMING CHARACTERISTICS (FIGURE 2) (TIMING IS TESTED WITH NO-LOAD) SCLK Clock Frequency fSCLK 0 SCLK Pulse Width High tCH 20 ns SCLK Pulse Width Low tCL 20 ns CS Fall-to-SLCK Rise Setup tCSS 15 ns DIN Setup Time tDS 15 ns DIN Hold Time tDH 0 ns SCLK Falling Edge-to-CS Rising Edge tCSH 10 ns CS Pulse Width High tCSW 80 ns Note 1: Note 2: Note 3: Note 4: DC Specifications are tested without output loads. Linearity guaranteed from code 115 to code 3981. Offset and gain error limit the FSR. Guaranteed by design. Typical Operating Characteristics (TA = +25C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. CODE, TA = +25C 0.8 0.6 VDD = +5V DNL (LSB) 4 0 -4 VDD = +3V -8 -12 -16 512 1024 1536 2048 2560 3072 3584 4096 CODE 0.6 0.4 0.4 0.2 0.2 0.0 0.0 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 0.8 TUE (%) 8 1.0 MAX5712 toc02 12 INL (LSB) 1.0 MAX5712 toc01 16 TOTAL UNADJUSTED ERROR vs. CODE, TA = +25C MAX5712 toc03 INTEGRAL NONLINEARITY vs. CODE, TA = +25C VDD = +5V VDD = +3V -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 0 512 1024 1536 2048 2560 3072 3584 4096 CODE _______________________________________________________________________________________ 3 MAX5712 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. CODE, TA = -40C 0.8 0.6 DNL (LSB) 4 0 -4 VDD = +3V -8 0.4 0.4 0.2 0.2 0.0 0.0 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -12 -0.8 -0.8 -16 -1.0 -1.0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 CODE INTEGRAL NONLINEARITY vs. CODE, TA = +125C DIFFERENTIAL NONLINEARITY vs. CODE, TA = +125C TOTAL UNADJUSTED ERROR vs. CODE, TA = +125C 0.8 0.6 DNL (LSB) 4 0 -4 VDD = +3V -8 -12 0.8 0.6 0.4 0.4 0.2 0.2 TUE (%) VDD = +5V 1.0 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 512 1024 1536 2048 2560 3072 3584 4096 WORST CASE INL AND DNL vs. TEMPERATURE 3.0 MINIMUM INL CODE = C00 HEX, SOURCING CURRENT FROM OUT 1.5 CODE = 400 HEX, SINKING CURRENT INTO OUT 1.0 40 60 80 100 120 3.5 3.0 CODE = C00 HEX, SOURCING CURRENT FROM OUT 2.5 CODE = 400 HEX, SINKING CURRENT INTO OUT 1.5 CODE = 000 HEX, SINKING CURRENT INTO OUT CODE = 000 HEX, SINKING CURRENT INTO OUT 0.5 0.0 0.0 TEMPERATURE (C) 4.0 1.0 0.5 -16 CODE = FFF HEX, SOURCING CURRENT FROM OUT 4.5 2.0 -8 -12 5.0 VOUT (V) MAXIMUM DNL 0 VOUT (V) 2.0 4 SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +5V) CODE = FFF HEX, SOURCING CURRENT FROM OUT 2.5 MAXIMUM INL 20 512 1024 1536 2048 2560 3072 3584 4096 CODE MAX5712 toc11 12 0 0 SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +3V) MAX5712 toc10 16 MINIMUM DNL VDD = +3V CODE CODE -4 VDD = +5V -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 8 0.0 -0.2 -1.0 -16 MAX5712 toc09 1.0 MAX5712 toc07 8 -40 -20 VDD = +3V CODE 12 0 VDD = +5V CODE 16 INL (LSB) 0 512 1024 1536 2048 2560 3072 3584 4096 MAX5712 toc08 0 4 0.6 MAX5712 toc12 VDD = +5V 0.8 TUE (%) 8 1.0 MAX5712 toc05 12 INL (LSB) 1.0 MAX5712 toc04 16 TOTAL UNADJUSTED ERROR vs. CODE, TA = -40C MAX5712 toc06 INTEGRAL NONLINEARITY vs. CODE, TA = -40C INL/DNL (LSB) MAX5712 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23 0 2 4 6 8 10 ISOURCE/SINK (mA) 12 14 16 0 5 10 15 20 25 ISOURCE/SINK (mA) _______________________________________________________________________________________ 30 35 40 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23 SUPPLY CURRENT vs. SUPPLY VOLTAGE 80 CODE = 000 60 40 20 0 200 150 100 3.2 3.7 4.2 4.7 5.2 800 700 VDD = +5V 600 500 400 300 VDD = +3V 200 50 100 0 2.7 SUPPLY VOLTAGE (V) 3.7 4.2 4.7 SUPPLY VOLTAGE (V) FULL-SCALE SETTLING TIME (VDD = +5V) FULL-SCALE SETTLING TIME (VDD = +5V) 3.2 0 5.2 1 2 3 4 5 CS INPUT VOLTAGE (V) HALF-SCALE SETTLING TIME (VDD = +3V) MAX5712 toc18 MAX5712 toc17 MAX5712 toc16 MAX5712 toc15 250 0 2.7 900 SUPPLY CURRENT (A) 100 300 MAX5712 toc14 CODE = FFF HEX POWER-DOWN SUPPLY CURRENT (nA) MAX5712 toc13 120 SUPPLY CURRENT (A) SUPPLY CURRENT vs. CS INPUT VOLTAGE POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX5712 Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) VSCLK 5V/div VSCLK 5V/div VSCLK 5V/div VOUT 1V/div VOUT VOUT 1V/div 1V/div CODE 000 TO FFF HEX RL = 5k CL = 200pF CODE 400 HEX TO C00 HEX RL = 5k CL = 200pF CODE FFF HEX TO 000 RL = 5k CL = 200pF 1s/div 2s/div 1s/div HALF-SCALE SETTLING TIME (VDD = +3V) EXITING POWER-DOWN (VDD = +5V) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V) MAX5712 toc19 MAX5712 toc21 MAX5712 toc20 VSCLK 5V/div VSCLK 5V/div VOUT CODE 800 HEX VOUT 1V/div 10mV/div VOUT CODE C00 HEX TO 400 HEX RL = 5k CL = 200pF 1s/div CODE 800 HEX TO 7FF HEX RL = 5k CL = 200pF 1V/div RL = 5k CL = 200pF 5s/div 500ns/div _______________________________________________________________________________________ 5 MAX5712 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23 Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V) CLOCK FEEDTHROUGH (VDD = +5V) MAX5712 toc22 MAX5712 toc23 VSCLK 2V/div VOUT 10mV/div VOUT 1mV/div CODE 7FF HEX TO 800 HEX RL = 5k CL = 200pF RL = 5k CL = 200pF 500ns/div 500ns/div Pin Description 6 PIN NAME 1 VDD Power-Supply Input FUNCTION 2 GND Ground 3 DIN Serial-Data Input 4 SCLK Serial-Clock Input 5 CS 6 OUT Active Low Chip-Select Input DAC Output Voltage _______________________________________________________________________________________ 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23 The MAX5712 voltage output, 12-bit DAC, offers a full 12-bit performance in a small 6-pin SOT23 package. The SOT23 footprint is less than 9mm2. The MAX5712 has less than 1LSB differential nonlinearity error, ensuring monotonic performance. The device uses a simple 3-wire, SPI/QSPI/MICROWIRE and DSP-compatible serial interface that operates up to 20MHz. The MAX5712 incorporates three shutdown modes, making it ideal for low-power. Analog Section The MAX5712 consists of a resistor string, an output buffer, and a POR circuit. Monotonic digital to analog conversion is achieved using a resistor string architecture. Since VDD is the reference for the MAX5712, the accuracy of the DAC depends on the accuracy of VDD. The low bias current of the MAX5712 allows its power to be supplied by a voltage reference such as the MAX6030. The 12-bit DAC code is binary-unipolar with 1LSB = VDD/4096. Output Buffer The DAC output buffer has a rail-to-rail output and is capable of driving a 5k resistive load in parallel with a 200pF capacitive load. With a capacitive load of 200pF, the output buffer slews 0.5V/s. With a 1/4FS to 3/4FS output transition, the amplifier output settles to 1/2LSB in less than 10s when loaded with 5k in parallel with 200pF. The buffer amplifier is stable with any combination of resistive loads greater than 5k and capacitive loads less than 200pF. Program the input register bits to power-down the device. The DAC registers are preserved during power- down and upon wake-up, the DAC output is restored to its pre-power-down voltage. Power-On Reset The MAX5712 has a POR circuit to set the DACs output to zero when VDD is first applied. This ensures that unwanted DAC output voltages will not occur immediately following a system start-up, such as after a loss of power. Upon initial power-up, an internal power-onreset circuit ensures that all DAC registers are cleared, the DAC is powered-down, and its output is terminated to GND by a 100k resistor. An 8s recovery time after issuing a wake-up command is needed before writing to the DAC registers. Digital Section 3-Wire Serial Interface The MAX5712 digital interface is a standard 3-wire connection compatible with SPI/QSPI/MICROWIRE/DSP interfaces. The chip-select input (CS) frames the serial data loading at DIN. Immediately following CS high-tolow transition, the data is shifted synchronously and latched into the input register on the falling edge of the serial clock input (SCLK). After 16 bits have been loaded into the serial input register, it transfers its contents to the DAC latch. CS may then either be held low or brought high. CS must be brought high for a minimum of 80ns before the next write sequence, since a write sequence is initiated on a falling edge of CS. Not keeping CS low during the first 15 SCLK cycles discards input data. The serial clock (SCLK) can idle either high or low between transitions. Figure 1 shows the complete 3-wire serial interface transmission. Table 1 lists serial-interface mapping. tCH tCL tCSW tCSS tDH tCSH tDS C3 SO Figure 1. Timing Diagram _______________________________________________________________________________________ 7 MAX5712 Detailed Description MAX5712 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23 Table 1. Serial Interface Mapping 16-BIT SERIAL WORD MSB LSB MODE OUTPUT Set and update DAC VOUT = VDD x CODE/4096 0 Wake-Up Current DAC setting (initially 0) 0 1 Power-Down Floating 1 0 Power-Down 1k to GND 1 1 Power-Down 100k to GND C3 C2 C1 C0 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 0 0 0 0 12-Bit DAC Code 1 1 1 1 X X X X X X X X X X 0 1 1 1 1 X X X X X X X X X X 1 1 1 1 X X X X X X X X X X 1 1 1 1 X X X X X X X X X X Shutdown Modes Digital Inputs and Interface Logic The MAX5712 includes three software-controlled shutdown modes that reduce the supply current to below 1A. In two of the three shutdown modes, OUT is connected to GND through a resistor. Table 1 lists the three shutdown modes of operation. The 3-wire digital interface for the MAX5712 is compatible with SPI, QSPI, MICROWIRE, and DSP. The three digital inputs (CS, DIN, and SCLK) load the digital input serially into the DAC. All of the digital inputs include Schmitt-trigger buffers to accept slow-transition interfaces. This allows optocouplers to interface directly to the MAX5712 without additional external logic. The digital inputs are compatible with CMOS-logic levels. Applications Information Device Powered by an External Reference The MAX5712 generates an output voltage proportional to VDD, coupling power supply noise to the output. The circuit in Figure 2 rejects this power-supply noise by powering the device directly with a precision voltage reference, improving overall system accuracy. The MAX6030 (+3V, 75ppm) or the MAX6050 (+5V, 75ppm) precision voltage references are ideal choices due to the low-power requirements of the MAX5712. This solution is also useful when the required full-scale output voltage is less than the available supply voltages. Power-Supply Bypassing and Layout Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the supply ground is short and low impedance. Bypass VDD with a 0.1F capacitor to ground as close as possible to the device. Pin Configuration TOP VIEW IN VDD 1 OUT VDD MAX6050 MAX6030 MAX5712 GND GND GND 2 MAX5712 6 OUT 5 CS 4 SCLK OUT DIN 3 SOT23 Chip Information Figure 2. MAX5712 Powered By Reference 8 TRANSISTOR COUNT: 3856 PROCESS: BiCMOS _______________________________________________________________________________________ 12-Bit, Low-Power, Rail-to-Rail Voltage-Output Serial DAC in SOT23 6LSOT.EPS PACKAGE OUTLINE, SOT-23, 6L 21-0058 F 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5712 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)