SPICE Device Model SUD25N15-52 Vishay Siliconix N-Channel 150-V (D-S) 175 MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Model Subcircuit) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit mode is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70553 03-Feb-02 www.vishay.com 1 SPICE Device Model SUD25N15-52 Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Condition Simulated Data Measured Data VGS(th) VDS = VGS, ID = 250A 3 ID(on) VDS = 5V, VGS = 10V 124 VGS = 10V, ID = 5A 0.040 VGS = 10V, ID = 5A, TJ = 125C 0.070 VGS = 10V, ID = 5A, TJ = 175C 0.086 VGS = 6V, ID = 5A 0.047 0.047 IS = 15A, VGS = 0 V 0.89 0.90 1695 1725 Unit Static Gate Threshold Voltage b On-State Drain Current b Drain-Source On-State Resistance b Forward Voltage Dynamic rDS(on) VSD V A 0.042 V a Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Chargec Qg Gate-Source Chargec Qgs Gate-Drain Chargec Turn-On Delay Timec Rise Timec Turn-Off Delay Timec c VGS = 0V, VDS = 25V, f = 1MHz 216 101 100 34 33 9 9 Qgd 12 12 td(on) 33 15 tr 40 70 55 25 60 60 69 95 td(off) Fall Time tf Source-Drain Reverse Recovery Time trr VDS = 75V, VGS = 10V, ID = 25A 231 VDD = 50V, RL = 3 ID 25A, VGEN = 10V, RG = 2.5 IF = 25A, di/dt = 100 A/s pF nC ns Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width 300 s, duty cycle 2%. c. Independent of operating temperature. www.vishay.com 2 Document Number: 70553 03-Feb-02 SPICE Device Model SUD25N15-52 Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70053 03-Feb-02 www.vishay.com 3