SPICE Device Model SUD25N15-52
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 7055 3 www.vishay.com
03-Feb-02 1
N-Channel 150-V (D-S) 175°
°°
° MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Model Subcirc uit)
• Level 3 MOS
• Apply for both Linear and Switc hi ng Application
• Accurate over the −55 to 125°C Temperat ure Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
mode is extracted and optimized over the −55 to 125°C temperature
ranges under the pulsed 0-to-10V gate drive. The saturated output
impedance is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched C
g
d model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMA TIC
SPICE Device Model SUD25N15-52
Vishay Siliconix
www.vishay.com Docu ment Number: 70553
203-Feb-02
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Condition Simulated
Data Measured
Data Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA 3 V
On-State Drain CurrentbID(on) VDS = 5V, VGS = 10V 124 A
VGS = 10V, ID = 5A 0.040 0.042
VGS = 10V, ID = 5A, TJ = 125°C 0.070
VGS = 10V, ID = 5A, TJ = 175°C0.086
Drain-Source On-State ResistancebrDS(on)
VGS = 6V, ID = 5A 0.047 0.047
Ω
Forward VoltagebVSD IS = 15A, VGS = 0 V 0.89 0.90 V
Dynamica
Input Capacitance Ciss 1695 1725
Output Capacitance Coss 231 216
Reverse Transfer Capacitance Crss
VGS = 0V, VDS = 25V, f = 1MHz
101 100
pF
Total Gate ChargecQg34 33
Gate-Source ChargecQgs 99
Gate-Drain ChargecQgd
VDS = 75V, VGS = 10V, ID = 25A
12 12
nC
Turn-On Delay Timectd(on) 33 15
Rise Timectr40 70
Turn-Off Delay Timectd(off) 55 25
Fall Timectf
VDD = 50V, RL = 3Ω
ID ≅ 25A, VGEN = 10V, RG = 2.5Ω
60 60
Sou rce-Drain Reverse Recovery Time trr IF = 25A, di/dt = 100 A/µs69 95
ns
Notes
a. Guarante ed b y desi gn, no t subjec t to prod ucti on testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
c. Independent of operating temperature.
SPICE Device Model SUD25N15-52
Vishay Siliconix
Document Number: 7005 3 www.vishay.com
03-Feb-02 3
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERW ISE NOTED)
