Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2000
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4340
24-Bit, 96 kHz Stereo DAC for Audio
Features
lComplete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
l101 dB Dynamic Range
l91 dB THD+N
lLow Clock Jitter Sensitivity
l+3 V to +5 V Power Supply
lFiltered Line Level Outp uts
lOn-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
l30 mW with 3 V supply
lPopguard® Technology for Control of Clicks
and Pops
Description
The CS4340 i s a comple te stereo digita l-to-analog sy s-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis
and switched capacitor analog filtering. The advantages
of this archite ctur e include: id eal differe ntial li nearity , no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
The CS4340 accepts data at audio sample rates from
2 kHz to 100 kHz, consumes very little power, and oper-
ates over a wide power supply range. The features of the
CS4340 are ideal for DVD players, CD players, set-top
box and automotive systems.
ORDERING INFORMATION
CS4340-KS 16-pin SOIC, -10 to 70 °C
CS4340-BS 16-pin SOIC, -40 to 85 °C
CDB4340 Evaluation Board
I
∆Σ
DAC Analog Filter
Serial
Input
Interface
Interpolation
Filter Analog Filter
MUTEC
AOUTL
AOUTR
RST
LRCK
SDATA
MCLK
∆Σ
External
Mute Control
SCLK/DEM1
DAC
Interpolation
Filter
De-emphasis
DEM0
DIF0
DIF1
NOV ‘00
DS297PP3
CS4340
2DS297PP3
TABLE OF CONTENT
1. CHARACTERISTICS AND SPECIFICATIONS ............... ...... ....... ...... ....... ..... 5
ANALOG CHARACTERISTICS...................................................................5
ANALOG CHARACTERISTICS...................................................................6
ANALOG CHARACTERISTICS...................................................................7
POWER AND THERMAL CHARACTE RIS TICS ............................. ............8
DIGITAL CHARACTERISTICS....................................................................8
RECOMMENDED OPERATING CONDITIONS..........................................9
SWITCHING CHAR ACTE RISTI CS....................... ....... ...... ....... ...... ....... ...10
2. TYPICAL CONNECTION DIAGRAM ............................................................12
3. PIN DESCRIPTION ...... ....... ...... .......................... ...... .......................... ..........1 3
4. APPLICATIONS ............................................................................................ 16
4.1 Grounding and Power Supply Decoupling .........................................16
4.2 Oversampling Modes .........................................................................16
4.3 Recommended Power-up Sequence .................................................16
4.4 Popguard® Transient Control ............................................................16
5. INTERPOLATION FILTER RESPONSE PLOTS ..............................17
6. DIGITAL INTERFACE FORMATS .............................................19
7. ANALOG PERFORMANCE PLOTS ............. ...... ...... ....... ...... ....... ................21
8. PARAMETER DEFINITIONS ........................................................................ 26
Total Harmonic Distortion + Noise (THD+N) .............................................26
Dynamic Range.........................................................................................26
Interchannel Isolation.................................................................................26
Interchannel Gain Mismatch......................................................................26
Gain Error..................................................................................................26
Gain Drift....................................................................................................26
9. REFERENCES ..............................................................................................26
10. PACKAGE DIMENSIONS ...........................................................................27
Contacting Cirrus Logi c Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Prelimi nar y product info rmation descr i bes pr oduct s whi c h are i n p r od uct i on, but for whi ch f ul l char act erization da ta i s not yet available. Advance produ ct i nfor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained i n this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or ot h er ri g ht s
of third parties. Thi s document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of
this publicati o n may be copied , reproduced, stored in a retr ieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) wi t hou t the prior written consent of Cirrus Logi c, Inc. It e ms f rom any Ci rrus L ogi c websi t e or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
CS4340
DS297PP3 3
LIST OF FIGURES
Figure 1. External Serial Mode Input Timing............................................................. 11
Figure 2. Internal Serial Mod e Input Timing . ......................... .......................... .......... 11
Figure 3. Internal Serial Clo ck Gene ratio n ......... ....... ...... ...... .......................... .......... 11
Figure 4. Typical Connec tio n Diagram .. ....... ...... ....... ...... ...... ....... ...... ....... ................ 1 2
Figure 5. Base-Rate Stopband Rejection.................................................................. 17
Figure 6. Base-Rate Transition Band ........................................................................ 17
Figure 7. Base-Rate Transition Band (Detail)............................................................ 17
Figure 8. Base-Rate Passband Ripple ...................................................................... 17
Figure 9. High-Rate Stopband Rejection................................................................... 17
Figure 10. High-Rate Transition Band....................................................................... 17
Figure 11. High-Rate Transition Band (Detail) .......................................................... 18
Figure 12. High-Rate Passband Ripple..................................................................... 18
Figure 13. Output Test Load...................................................................................... 18
Figure 14. Maximum Loading.................................................................................... 18
Figure 15. Power vs. Sample Rate (VA = 5V)........................................................... 18
Figure 16. CS4340 Format 0 (I2S)............................................................................. 19
Figure 17. CS4340 Format 1..................................................................................... 19
Figure 18. CS4340 Format 2..................................................................................... 20
Figure 19. CS4340 Format 3..................................................................................... 20
Figure 20. De-Emphasis Curve................................................................................. 21
Figure 21. FFT 0 dB input, BRM, VA = 3V ................................................................ 22
Figure 22. FFT -60 dB input, BRM, VA = 3V............................................................. 22
Figure 23. FFT Idle Noise, BRM, VA = 3V................................................................. 22
Figure 24. Fade-to-Noise Linearity, BRM, VA = 3V................................................... 22
Figure 25. THDN vs Ampl, BRM, VA = 3V ................................................................ 22
Figure 26. THDN vs Freq, BRM, VA = 3V................................................................. 22
Figure 27. FFT 0 dB input, BRM, VA = 5V ................................................................ 23
Figure 28. FFT -60 dB input, BRM, VA = 5V............................................................. 23
Figure 29. FFT Idle Noise, BRM, VA = 5V................................................................. 23
Figure 30. Fade-to-Noise Linearity, BRM, VA = 5V................................................... 23
Figure 31. THDN vs Ampl, BRM, VA = 5V ................................................................ 23
Figure 32. THDN vs Freq, BRM, VA = 5V................................................................. 23
Figure 33. FFT 0 dB input, HRM, VA = 3V................................................................ 24
Figure 34. FFT -60 dB input, HRM, VA = 3V............................................................. 24
Figure 35. FFT Idle Noise, HRM, VA = 3V ................................................................ 24
Figure 36. Fade-to-Noise Linearity, HRM, VA = 3V................................................... 24
Figure 37. THDN vs Ampl, HRM, VA = 3V................................................................ 24
Figure 38. THDN vs Freq, HRM, VA = 3V................................................................. 24
Figure 39. FFT 0 dB input, HRM, VA = 5V................................................................ 25
Figure 40. FFT -60 dB input, HRM, VA = 5V............................................................. 25
Figure 41. FFT Idle Noise, HRM, VA = 5V ................................................................ 25
Figure 42. Fade-to-Noise Linearity, HRM, VA = 5V................................................... 25
Figure 43. THDN vs Ampl, HRM, VA = 5V................................................................ 25
Figure 44. THDN vs Freq, HRM, VA = 5V................................................................. 25
CS4340
4DS297PP3
LIST OF TABLES
Table 1. Internal Serial Clock Mode .......................................................................... 14
Table 2. External Serial Clock Mode ......................................................................... 14
Table 3. Common Master Clock Frequencies ........................................................... 14
Table 4. Digital Interface Format - DIF1 and DIF0 ................................................... 15
CS4340
DS297PP3 5
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): TA = 25 °C; Logic "1" =
VA = 5 V; Logic "0" = AGND;Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode =
48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-
Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified.
Test load RL = 10 kΩ, CL = 10 pF (see Figure 13)
Notes: 1. CS434 0-K S pa r ts are t est e d at 25 °C an d Mi n/ Ma x pe rfo rm an ce nu mb e rs ar e guar an t eed across the
spec ifie d te mp erature r ange , TA.
2. One-half LSB of triangular PDF dither is added to data.
Parameter
Base-rate Mode High-Rate Mode
Symbol Min Typ Max Min Typ Max Unit
CS4340-KS Dynamic Performance for VA = 5 V (Note 1)
Spec ified Temperature Range TA-10 - 70 -10 - 70 °C
Dynamic Range (Note 2)
18 to 24-Bit unweighted
A-Weighted
16-Bit unweighted
A-Weighted
93
96
-
-
98
101
95
97
-
-
-
-
91
95
-
-
96
100
94
97
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 2)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N -
-
-
-
-
-
-91
-78
-38
-90
-75
-35
-86
-
-
-
-
-
-
-
-
-
-
-
-89
-76
-36
-89
-74
-34
-84
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 102 - - 102 - dB
CS4340-KS Dynamic Performance for VA = 3 V (Note 1)
Spec ified Temperature Range TA-10 - 70 -10 - 70 °C
Dynamic Range (Note 2)
18 to 24-Bit unweighted
A-Weighted
16-Bit unweighted
A-Weighted
89
92
-
-
94
97
93
96
-
-
-
-
87
91
-
-
92
96
92
96
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 2)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N -
-
-
-
-
-
-94
-74
-34
-93
-73
-33
-88
-
-
-
-
-
-
-
-
-
-
-
-92
-72
-32
-91
-72
-32
-87
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 102 - - 102 - dB
CS4340
6DS297PP3
ANALOG CHARACTERISTICS (Continued)
Notes: 3. CS4340-BS parts are tested at the extremes of the specified temperature range and Min/Max
performance numbers are guaranteed across the specified temperature range, TA. Typi cal nu mber s are
taken at 25 °C.
Parameter
Base-rate Mode High-Rate Mode
Symbol Min Typ Max Min Typ Max Unit
CS4340-BS Dynamic Performance for VA = 5 V (Note 3)
Spec ified Temperature Range TA-40 - 85 -40 - 85 °C
Dynamic Range (Note 2)
18 to 24-Bit unweighted
A-Weighted
16-Bit unweighted
A-Weighted
TBD
TBD
-
-
98
101
95
97
-
-
-
-
TBD
TBD
-
-
96
100
94
97
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 2)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N -
-
-
-
-
-
-91
-78
-38
-90
-75
-35
TBD
-
-
-
-
-
-
-
-
-
-
-
-89
-76
-36
-89
-74
-34
TBD
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 102 - - 102 - dB
CS4340-BS Dynamic Performance for VA = 3 V (Note 3)
Spec ified Temperature Range TA-40 - 85 -40 - 85 °C
Dynamic Range (Note 2)
18 to 24-Bit unweighted
A-Weighted
16-Bit unweighted
A-Weighted
TBD
TBD
-
-
94
97
93
96
-
-
-
-
TBD
TBD
-
-
92
96
92
96
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 2)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N -
-
-
-
-
-
-94
-74
-34
-93
-73
-33
TBD
-
-
-
-
-
-
-
-
-
-
-
-92
-72
-32
-91
-72
-32
TBD
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 102 - - 102 - dB
CS4340
DS297PP3 7
ANALOG CHARACTERISTICS (Continued)
Notes: 4. Refer to Figure 14.
5. Filt er r es po nse is gu ar ant e ed by de sig n.
6. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 5-12) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
7. For Base-Rate Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For High-Rate Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
8. De- em pha si s is not avai lab le in High - Rate Mod e.
Parameters Symbol Min Typ Max Units
Analog Output
Full Scale Output Voltage 0.63•VA 0.7•VA 0.77•VA Vpp
Quies c ent Voltage VQ-0.5•VA- VDC
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - p pm/°C
AC-Load Resistance (Note 4) RL3--kΩ
Load Capacitance (Note 4) CL--100pF
Parameter
Base-rate Mode High-Rate Mode
Symbol Min Typ Max Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response (Note 5)
Passband (Note 6)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
0
-
0
-
-
-
.4535
-
.4998
-
0
0
-
-
-
-
.4621
.4982
Fs
Fs
Fs
Frequency Response 10 Hz to 20 kHz -.02 - +.08 -0.06 - 0.2 dB
StopBand .5465 - - .577 - - Fs
StopBand Attenuation (Note 7) 50 - - 55 - - dB
Group Delay tgd - 9/Fs - - 4/Fs - s
Passband Group Delay Deviation 0 - 40 kHz
0 - 20 kHz -
--
±0.36/Fs -
--
-±1.39/Fs
±0.23/Fs -
-s
s
De-emphasis Error Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+.2/-.1
+.05/-.14
+0/-.22 (Note 8) dB
dB
dB
CS4340
8DS297PP3
POWER AND THERMAL CHARACTERISTIC S
Notes: 9. Refer to Figure 15.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 4. Increasing the
capacitance will also increase the PSRR.
DIGITAL CHARACTERISTICS (for -KS parts TA = -10 to 70°C; for -BS parts TA = -40 to 85°C;
VA = 2.7 V - 5.5 V)
CS4340-KS CS4340-BS
Parameters Symbol Min Typ Max Min Typ Max Units
Power Supplies
Power Supply Current normal operation
VA = 5 V power- down state IA
IA
-
-15
60 18
--
-15
60 TBD
-mA
µA
Power Diss ipation (Note 9)
VA = 5 V normal operation
power-down -
-75
0.3 90
--
-75
0.3 TBD
-mW
mW
Power Supply Current normal operation
VA = 3 V power- down state IA
IA
-
-10
30 14
--
-10
30 TBD
-mA
µA
Power Diss ipation (Note 9)
VA = 3 V normal operation
power-down -
-30
0.09 42
--
-30
0.09 TBD
-mW
mW
Package Thermal Resistance θJA - 110 - - 110 - °C/Watt
Power Supply Rejection Ratio (1 kHz) (Note 10)
(60 Hz) PSRR -
-60
40 -
--
-60
40 -
-dB
dB
Parameters Symbol Min Typ Max Units
High-Level Input Voltage VA = 5 V
VA = 3 V VIH 2.0
2.0 -
--
-V
V
Low-Level Input Voltage VA = 5 V
VA = 3 V VIL -
--
-0.8
0.8 V
V
Input Leakage Current Iin --±10µA
Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 3 - mA
CS4340
DS297PP3 9
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND = 0V ; al l vo lt ages w it h re spect to
ground.)
Parameters Symbol Min Max Units
DC Power Supply VA -0.3 6.0 V
Input Current, Any Pin Except Supplies Iin -±10 mA
Digital Input Voltage VIND -0.3 VA+0.4 V
Ambient Operating Temperature (power applied) TA-55 125 °C
Storage Temperature Tstg -65 150 °C
Parameters Symbol Min Typ Max Units
DC Power Supply VA 2.7 5.0 5.5 V
CS4340
10 DS297PP3
SWITCHING CHARACTERISTICS (VA = 2.7 V - 5.5 V; Inputs: Logic 0 = 0 V, Logic 1 = VA, CL =
20 pF; for -KS parts TA = -10 to 70°C; for -BS parts TA = -40 to 85°C)
Notes: 11. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Per i od.
12. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See figures 16-19)
Parameters Symbol Min Typ Max Units
Input Sample Rate Base-Rate Mode
High-Rate Mode Fs 2
50 -
-50
100 kHz
kHz
MCLK Pulse Width High MCLK/LRCK = 512 10 - 1000 ns
MCLK Pulse Width Low MCLK/LRCK = 512 10 - 1000 ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - 1000 ns
MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - 1000 ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - 1000 ns
MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - 1000 ns
External SCLK Mode
LRCK Duty Cycle (External SCLK only) 40 50 60 %
SCLK Pulse Width Low tsclkl 20 - - ns
SCLK Pulse Width High tsclkh 20 - - ns
SCLK Period MCLK / LRCK = 512, 256 or 384 tsclkw --ns
SCLK Period MCLK / LRCK = 128 or 192 tsclkw --ns
SCLK rising to LRCK edge delay tslrd 20 - - ns
SCLK rising to LRCK edge setup time tslrs 20 - - ns
SDATA valid to SCLK rising setup time tsdlrs 20 - - ns
SCLK rising to SDATA hold time tsdh 20 - - ns
Int ernal SCLK Mode
LRCK Duty Cycle (Internal SCLK only) (Note 11) - 50 - %
SCLK Period (Note 12) tsclkw --ns
SCLK rising to LRCK edge tsclkr --µs
SDATA valid to SCLK rising setup time tsdlrs --ns
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128 tsdh --ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192 tsdh --ns
1
128()Fs
----------------------
1
64()Fs
------------------
1
SCLK
----------------
tsclkw
2
------------------
1
512()Fs
----------------------10+
1
512()Fs
----------------------15+
1
384()Fs
----------------------15+
CS4340
DS297PP3 11
sclkh
t
slrs
t
slrd
t
sdlrs
tsdh
t
sclkl
t
SDATA
SCLK
LRCK
Figure 1. Extern al Serial Mode Input Timing
SDATA
*INTERNAL SCLK
LRCK
sclkw
t
sdlrs
t
sdh
t
sclkr
t
Figure 2. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS4340.
SDATA
LRCK
MCLK
*INTERNAL SCLK
1N
2N
Figure 3. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4340.
N equals MCLK divided by SCLK
CS4340
12 DS297PP3
2. TYPICAL CONNECTION DIAGRAM
13
Audio
Data
Processor
External Clock MCLK
AGND
AOUTR
CS4340
SDATA
LRCK
VA
AOUTL
3
4
5
14 0.1 µF +1µF
12
+5Vto+3V
3.3 µF
3.3 µF
10 k
Ω
C
C
560
Ω
560
Ω
+
+
Mode
Configuration 8
6
7
SCLK/DEM1
1
2
DIF1
DIF0
DEM0
RST
MUTEC 16 OPTIONAL
MUTE
CIRCUIT
15
1µF 0.1 µF
Audio
Output
Audio
Output
R
L
+ 560
C= 4
π
F
S
R
L
560
RL
RL
+
+
10 k
Ω
.1 µF 1µF
9
10
11
REF_GND
FILT+
VQ
Left
Right
Figure 4. Typical Connection Diagram
CS4340
DS297PP3 13
3. PIN DESCRIPTION
RST 1 Reset (
Input
) - The device e nters a low pow er mode and all in ternal state machines are res et to
the default se ttings when low. RST sh ould be held low duri ng pow er-up until the power supp ly,
master and left/right clocks are stable.
SDATA 2 Serial Audio Data (
Input
) - Two’s complement MSB-first serial data is input on this pin. The
data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right
clock. The required relationship between the Left/Right clock, serial clock and serial data is
defined by the DIF1-0 pins. The options are detailed in Figures 16-19.
SCLK 3 Serial Clock (
Input
) - Clocks the individual bits of the serial data into the SDATA pin. The
required rel atio ns hip bet w een the L eft/ Ri gh t cl oc k, s eri al cloc k and seri al dat a is defi ne d by the
DIF1-0 pins. The options are detailed in Figures 16-19.
The CS4340 supports both internal and external serial clock generation modes. Internal SCLK
mo de is used to gain access to extra de-emp hasis modes.
Internal Serial Clock Mode
- In the Internal Serial Clock Mode, the serial clock is internally
derived and sync hronous with the ma st er clock an d lef t/right c lock. The SCLK/LR CK freq uency
ratio is either 32, 48, or 64 depending upon the DIF1-0 pins as shown in Figures 16-19. Opera-
tion in this mode is identical to operation with an external seria l cloc k synchronized with LRCK.
External Serial Clock Mode
- The CS4340 will enter the External Serial Clock Mode whenever
16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period.
The devic e will rev ert to Inter nal Serial Clo ck Mode if no lo w to hi gh tra ns iti ons are d ete cte d on
the SCLK pin for 2 consecutive periods of LRCK.
152 143 134
161
116
107
98
125
Reset RST MUTEC Mute Control
Serial Data SDATA AOUTL Left Analog Output
Serial Clock / De-emphasis SCLK/DEM1 VA Analog Power
Left/Right Clock LRCK AGND Analog Ground
Master Clock MCLK AOUTR Right Analog Output
Digital Interface Format DIF1 REF_GND Reference Ground
Digital Interface Format DIF0 VQ Quiescent Voltage
De-emphasis DEM0 FILT+ Positive Voltage Reference
CS4340
14 DS297PP3
DEM1 and DEM0 3 & 8 De-emphasis Con t rol (
Input
) - Impleme nta tion of the sta nda rd 15µs/50µs dig ital de-emphasis
filter respon se, Figure 20 , requires reco nfiguratio n of the digital filt er to maintai n the proper filte r
response for 32, 44.1 or 48 kHz sample rates. When using Internal Serial Clock Mode, as
described above, Pin 3 is available for de-emphasis control, DEM1, and all de-emphasis filters
are available, Table 3. When using External Serial Clock Mode, as described above, Pin 3 is
not available for de-emphasis use and only the 44.1 kHz de-emphasis filter is available,
Table 4. NOTE: De-emphasis is not available in High-Rate Mode.
LRCK 4 Left/Right Clock (
Input
) - The Left/Right clock determines which channel is currently being
input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at
the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output
from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period
dif ference. Th e required re lationsh ip between th e Left/Right c lock, se rial cloc k and seri al data is
defined by the DIF1-0 pins. The options are detailed in Figures 16-19.
MCLK 5 Master C lock (
Input
) - The mas ter clo ck fre quenc y mus t be ei ther 256 x, 384 x or 512x the inp ut
sample rate in Base Rate Mode (BRM) and either 128x or 192x the input sample rate in High
Rate Mode (HRM). Table 3 illustrates several standard audio sample rates and the required
maste r cloc k f requ enc ies.
DEM1 DEMO DESCRIPTION
00Disabled
0144.1kHz
1048kHz
1132kHz
Table 1. Internal Serial Clock Mo de
DEMO DESCRIPTION
0 Disabled
1 44.1kHz
Table 2. External Serial Clock Mode
Sample
Rate
(kHz)
MCLK (MHz)
HRM BRM
128x 192x 256x 384x 512x
32 4.0960 6.1440 8.1920 12.2880 16.3840
44.1 5.6448 8.4672 11.2896 16.9344 22.5792
48 6.1440 9.2160 12.2880 18.4320 24.5760
64 8.1920 12.2880 - - -
88.2 11.2896 16.9344 - - -
96 12.2880 18.4320 - - -
Table 3. Common Master Clock Frequencies
CS4340
DS297PP3 15
DIF1 and DIF0 6 & 7 Digit a l Interfac e Format (I
nput
) - The required relat ionsh ip between the Lef t/Right cl ock, seria l
clock and serial data is defined by the Digital Interface Format and the options are detailed in
Figures 16-19
FILT+ 9 Positive Voltage Reference (
Output
) - Positive reference for internal sampling circuits. An
external capacitor is required from FILT+ to analog ground, as shown in Figure 4. The recom-
me nded value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz.
FILT+ is not intended to supply external current. FILT+ has a typical source impedance of
250 kΩ and any current drawn from this pin will alter device performance.
VQ 10 Quiesc ent Voltage (
Output
) - Filter connection for internal quiescent reference voltage, typi-
cally 50% of VA. Capacitors must be connected from VQ to analog ground, as shown in
Figure 4. VQ is not intended to supply external current. VQ has a typical source impedence of
250 kΩ and any current drawn from this pin will alter device performance.
REF_GND 11 Referen ce Ground (
Input
) - Ground reference for the internal sampling circuits. Must be con-
nected to analog ground.
AOUTR and AOUTL 12 & 15 Analog Out puts (
Output
) - The full s ca le a nal og o utp ut le vel is spe ci fie d in the Analog Chara c-
teristics specifications table.
AGND 13 Ground (
Input
) - Ground Reference.
VA 14 Analog Power (
Input
) - Analog power supply. Typically 3 to 5 VDC.
MUTEC 16 Mute Control (
Output
) - The Mute Control pin goes high during power-up initialization, reset,
muting, master clock to left/right clock frequency ratio is incorrect or power-down. This pin is
intended to be used as a control for an external mute circuit to prevent the clicks and pops that
can occu r in any si ngle supp ly syste m. Use of M ute Contro l is not mand atory b ut recommend ed
for designs requiring the absolute minimum in extraneous clicks and pops.
.
DIF1 DIF0 DESCRIPTION FORMAT FIGURE
00I
2
S, up to 24-bit data 0 16
0 1 Left Justified, up to 24-bit data 1 17
1 0 Right Justified, 24-bit Data 2 18
1 1 Right Justified, 16-bit Data 3 19
Table 4. Digital In terface Format - DIF1 and DIF0
CS4340
16 DS297PP3
4. APPLICATIONS
4.1 Grounding and Power Supply
Decoupling
As with any high resolution converter, the CS4340
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figure 4 shows the recommended power arrange-
ment with VA connected to a clean supply. Decou-
pling capacitors should be located as close to the
device package as possible.
4.2 Oversampling Modes
The CS4340 operates in one of two oversampling
modes. Base Rate Mode supports input sample
rates up to 50 kHz while High Rate Mode supports
input sample rates up to 100 kHz. The devices op-
erate in Base Rate Mode (BRM) when
MCLK/LRCK is 256, 384 or 512 and in High R ate
Mode (HRM) when MCLK/LRCK is 128 or 192.
4.3 Recommended Power-up Sequence
RST should be held low until the power supply,
master and left/right clocks are stable.
4.4 Popguard® Transient Control
The CS4340 uses Popguard® technology to mini-
mize the effects of output transients during power-
up and power-down. This technique, when used
with external DC-blocking capacitors in series with
the audio outputs, minimizes the audio transients
commonly produced by single-ended single-supply
converters.
When the device is initially powered-up, the audio
outputs, AOUTL and AOUTR, are clamped to
AGND. Following a delay of approximately 1000
sample periods, each output begins to ramp toward
the quiescent voltage. Approximately 10,000
left/right clock cycles later, the outputs reach VQ
and audio output begins. This gradual voltage
ramping allows time for the external DC-blocking
capacitor to charge to the quiesce nt voltage, mini-
mizing the power-up transient.
To prevent transients at power-down, the device
must first enter its power-down state by setting the
RST pin low. When this occurs, audio output ceas-
es and the internal output buffer s are disconnect ed
from AOUTL and AOUTR. In their place, a soft-
start current sink is substituted which allows the
DC-blocking capacitors to s lowly discharge. Once
this charge is dissipated, the power to the device
may be turned off and the system is ready for the
next power-on.
To prevent an audio transient at the next power-on,
it is necessary to ensure that the DC-blocking ca-
pacitors have fully discharged before turning off
the power or exiting the power-down state. If not, a
transient will occur when the audio outputs are ini-
tially clamped to AGND. The time that the device
must remain in the power-down state is related to
the value of the DC-blocking ca pacitance. For ex-
ample, with a 3.3 µF capacitor, the mini mum po w-
er-down time will be approximately 0.4 seconds.
Use of the Mute Control func tion is rec ommended
for designs requiring the absolute minimum in ex-
traneous clicks and pops. Also, use of the Mute
Control function can enable the system designer to
achieve idle channel noise/signal-to-noise ratios
which are only limite d by the external mute circ uit.
See the CDB4340/41 data sheet for a suggested
mute circuit.
CS4340
DS297PP3 17
5. INTERPOLATION FILTER RESPONSE PLOTS
Figure 5. Base-Rate Stopband Rejection Figure 6. Base-Rate Transition Band
Figure 7. Base-Rate Transition Band (Detail) Figure 8. Base-Rate Passband Ripple
Figure 9. High-Rate Stopband Rejection Figure 10. High-Rate Transition Band
CS4340
18 DS297PP3
Figu re 11. H igh-Rate Transition Band (Detail) Figu re 12. H igh-Rate Pass band Ripple
AOUTx
AGND
3.3 µF
Vout
RLCL
+
Figure 13. Output Test Load
100
50
75
25
2.5
51015
Safe Operating
Region
Capacitive Load -- C (pF)
L
Resis tive Load -- R (k
Ω
)
L
125
320
Figu re 14. Maximum L oading
75
5030
Power (mW)
Sample Rate (kHz)
BRM
HRM
70
65
60
55
40 50 60 70 80 90 100
Figure 15. Power vs. Sample Rate (VA = 5V)
CS4340
DS297PP3 19
6. DIGITAL INTERFACE FORMATS
LRCK
SCLK
Left Channel Right Channel
SDATA +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Internal SCLK Mode External SCLK Mode
I2S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I2S, up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
I2S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 16. CS4340 Format 0 (I2S)
LRCK
SCLK
Left Channel Right Channel
SDATA +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Internal SCLK Mode External SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 17. CS4340 Format 1
CS4340
20 DS297PP3
LRCK
SCLK
Left Ch ann el
SDATA 65432107
23 22 21 20 19 18 65432107
23 22 21 20 19 18
32 clocks
0
Right Channel
Internal SCLK Mode External SCLK Mode
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 18. CS4340 Format 2
LRCK
SCLK
Left Ch ann el Right Channel
SDATA 6543210987
15 14 13 12 11 10 6543210987
15 14 13 12 11 10
32 clocks
Internal SCLK Mode External SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 19. CS4340 Format 3
CS4340
DS297PP3 21
7. ANALOG PERFORMANCE PLOTS
The following CS4340 Analog Performance Plots
were taken from the CDB4340 evaluation board
using the Audio Precision Dual Domain System
Two Cascade. All Base Rate Mode (BRM) plots
were taken at a 48 kHz sample rate with a 20 Hz to
20 kHz ba ndwidth using a 20 kHz low-pass brick-
wall filter in the DSP Analyzer. All High Rate
Mode (HRM) plots were taken at a 96 kHz sample
rate with a 20 Hz to 40 kHz bandwith using a
40 kHz brickwall filter in the DSP Analyzer.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10. 61 kHz
Figure 20. De-Emphasis Curve
CS4340
22 DS297PP3
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
Figure 21. FFT 0 dB input, BRM, VA = 3V Figure 22. FFT -60 dB input, BRM, VA = 3V
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
-10
+20
-8
-6
-4
-2
+0
+2
+4
+6
+8
+10
+12
+14
+16
+18
d
B
r
A
-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
Figure 23. FFT Idle Noise, BRM, VA = 3V Figure 24. Fade-to-Noise Linearity, BRM, VA = 3V
-105
-85
-104
-103
-102
-101
-100
-99
-98
-97
-96
-95
-94
-93
-92
-91
-90
-89
-88
-87
-86
d
B
r
A
-60 +0-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
dBFS
-105
-85
-104
-103
-102
-101
-100
-99
-98
-97
-96
-95
-94
-93
-92
-91
-90
-89
-88
-87
-86
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 25. THDN vs Ampl, BRM, VA = 3V Figure 26. THDN vs Freq, BRM, VA = 3V
CS4340
DS297PP3 23
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
Figure 27. FFT 0 dB input, BRM, VA = 5V Figure 28. FFT -60 dB input, BRM, VA = 5V
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
-10
+20
-8
-6
-4
-2
+0
+2
+4
+6
+8
+10
+12
+14
+16
+18
d
B
r
A
-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
Figure 29. FFT Idle Noise, BRM, VA = 5V Figure 30. Fade-to-Noise Linearity, BRM, VA = 5V
-105
-85
-104
-103
-102
-101
-100
-99
-98
-97
-96
-95
-94
-93
-92
-91
-90
-89
-88
-87
-86
d
B
r
A
-60 +0-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
dBFS
-105
-85
-104
-103
-102
-101
-100
-99
-98
-97
-96
-95
-94
-93
-92
-91
-90
-89
-88
-87
-86
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 31. THDN vs Ampl, BRM, VA = 5V Figure 32. THDN vs Freq, BRM, VA = 5V
CS4340
24 DS297PP3
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
5k 40k10k 15k 20k 25k 30k 35k
Hz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
5k 40k10k 15k 20k 25k 30k 35k
Hz
Figure 33. FFT 0 dB input, HRM, VA = 3V Figure 34. FFT -60 dB input, HRM, VA = 3V
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
5k 40k10k 15k 20k 25k 30k 35k
Hz
-10
+20
-8
-6
-4
-2
+0
+2
+4
+6
+8
+10
+12
+14
+16
+18
d
B
r
A
-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
Figure 35. FFT Idle Noise, HRM, VA = 3V Figure 36. Fade-to-Noise Linearity, HRM, VA = 3V
-105
-85
-104
-103
-102
-101
-100
-99
-98
-97
-96
-95
-94
-93
-92
-91
-90
-89
-88
-87
-86
d
B
r
A
-60 +0-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
dBFS
-105
-85
-104
-103
-102
-101
-100
-99
-98
-97
-96
-95
-94
-93
-92
-91
-90
-89
-88
-87
-86
d
B
r
A
20 40k50 100 200 500 1k 2k 5k 10k 20k
Hz
Figure 37. THDN vs Ampl, HRM, VA = 3V Figure 38. THDN vs Freq, HRM, VA = 3V
CS4340
DS297PP3 25
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
5k 40k10k 15k 20k 25k 30k 35k
Hz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
5k 40k10k 15k 20k 25k 30k 35k
Hz
Figure 39. FFT 0 dB input, HRM, VA = 5V Figure 40. FFT -60 dB input, HRM, VA = 5V
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
5k 40k10k 15k 20k 25k 30k 35k
Hz
-10
+20
-8
-6
-4
-2
+0
+2
+4
+6
+8
+10
+12
+14
+16
+18
d
B
r
A
-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
Figure 41. FFT Idle Noise, HRM, VA = 5V Figure 42. Fade-to-Noise Linearity, HRM, VA = 5V
-105
-85
-104
-103
-102
-101
-100
-99
-98
-97
-96
-95
-94
-93
-92
-91
-90
-89
-88
-87
-86
d
B
r
A
-60 +0-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
dBFS
-105
-85
-104
-103
-102
-101
-100
-99
-98
-97
-96
-95
-94
-93
-92
-91
-90
-89
-88
-87
-86
d
B
r
A
20 40k50 100 200 500 1k 2k 5k 10k 20k
Hz
Figure 43. THDN vs Ampl, HRM, VA = 5V Figure 44. THDN vs Freq, HRM, VA = 5V
CS4340
26 DS297PP3
8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
A measure of crosstalk between the left and right channels. Measured for each channel at the converter’ s
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
9. REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2) CDB4340 Evaluation Board Datasheet
CS4340
DS297PP3 27
10.PACKAGE DIMENSIONS
INCHES MILLIMETERS
DIM MIN NOM MAX MIN NOM MAX
A 0.053 0.064 0.069 1.35 1.63 1.75
A1 0.004 0.006 0.010 0.10 0.15 0.25
b 0.013 0.016 0.020 0.33 0.41 0.51
C 0.0075 0.008 0.010 0.19 0.20 0.25
D 0.386 0.390 0.394 9.80 9.91 10.00
E 0.150 0.154 0.157 3.80 3.90 4.00
e 0.040 0.050 0.060 1.02 1.27 1.52
H 0.228 0.236 0.244 5.80 6.0 6.20
L 0.016 0.025 0.050 0.40 0.64 1.27
∝0° 4° 8° 0° 4° 8°
JEDEC #: MS-012
Controling Dimension is Millimeters
e
16L SOIC (150 MIL BODY) PACKAGE DRAWING
D
H
E
b
A1
A
c
L
∝
SEATING
PLANE
1
