CHR3763-QDG 12-16GHz Integrated Down Converter GaAs Monolithic Microwave IC in SMD leadless package Description The CHR3763-QDG is a multifunction monolithic receiver, which integrates a balanced cold FET mixer, a LO buffer, and a RF low noise amplifier. It is designed for a wide range of applications, from military to commercial communication systems. The circuit is manufactured with a pHEMT process, 0.25m gate length. It is supplied in RoHS compliant SMD package. UMS R3763 A3667A A3688A YYWW YYWWG Conversion Gain & Noise Figure versus RF frequency @ IF = 2GHz (LSB mode) Main Features Broadband RF performances: 12-16GHz 12dB Conversion Gain 2.3dB Noise Figure 0dBm Input IP3 DC bias: Vd=3.0V @Id= 80mA 24L-QFN4x4 MSL1 20 Conversion Gain Conversion Gain & Noise Figure (dB) 18 NF 16 14 12 10 8 6 4 2 0 10 10,5 11 11,5 12 12,5 13 13,5 14 14,5 15 15,5 16 16,5 17 17,5 18 RF Frequency (GHz) Main Electrical Characteristics Tamb.= +25C Symbol Parameter FRF RF Frequency FIF IF frequency G Conversion gain NF Noise Figure Ref. : DSCHR3763-QDG3324 - 20 Nov 13 Min 12 DC Typ Max 16 3.5 12 2.3 1/16 Unit GHz GHz dB dB Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Electrical Characteristics Tamb.= +25C, VD1= VD2= VD3 = +3.0V (1) Symbol Parameter FRF RF Frequency range FLO LO frequency range FIF IF frequency range G Conversion gain (2) NF Noise Figure Im_rej Image rejection (2) PLO LO Input power IIP3 Input IP3 LO RL LO return loss RF RL RF return loss VDx DC drain voltage (1) VG1 1st stage LNA DC gate voltage VG2 2nd stage LNA DC gate voltage VG3 LO buffer DC gate voltage VG4 Mixer DC gate voltage Id Total drain current (ID1+ID2+ID3) (3) Min 12 8.5 DC Typ 12 2.3 20 5 0 12 10 3 -0.52 -0.46 -0.46 -1 80 Max 16 19.5 3.5 Unit GHz GHz GHz dB dB dBc dBm dBm dB dB V V V V V mA These values are representative of onboard measurements as defined on the drawing in paragraph "Evaluation mother board". (1) (1) (2) VD1: 1st stage LNA drain bias voltage. VD2: 2nd stage LNA drain bias voltage. VD3: LO-chain drain bias voltage. An external combiner 90 is required on I / Q. (3) ID1: 1st stage LNA drain current, typically 14mA, should be tuned with VG1. ID2: 2nd stage LNA drain current, typically 31mA, should be tuned with VG2. (3) ID3: LO-chain drain current, typically 35mA, should be tuned with VG3. (3) Electrostatic discharge sensitive device observe handling precautions! Ref. : DSCHR3763-QDG3324 - 20 Nov 13 2/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Absolute Maximum Ratings (1) Tamb.= +25C Symbol Parameter Vdx Drain bias voltage Id Drain bias current VG1,VG2 LNA gate bias voltages VG3 LO buffer gate bias voltage VG4 Mixer gate bias voltage P_RF Maximum peak input power overdrive (2) P_LO Maximum LO input power Tj Junction temperature Ta Operating temperature range Tstg Storage temperature range (1) Operation of this device above anyone of these parameters damage. (2) Duration < 1s. Values Unit 3.5 V 120 mA -2 to +0.4 V -2 to +0.4 V -2 to +0.4 V +15 dBm +10 dBm 175 C -40 to +85 C -55 to +150 C may cause permanent Typical Bias Conditions Tamb.= +25C Symbol Pad No VDx 13,15,18 Id 13,15,18 VG1 12 VG2 14 VG3 19 VG4 17 Parameter DC drain voltages Total drain current 1st stage LNA DC gate voltage (14mA) 2nd stage LNA DC gate voltage (31mA) LO buffer DC gate voltage (35mA) Mixer DC gate voltage Ref. : DSCHR3763-QDG3324 - 20 Nov 13 3/16 Values 3 80 -0.52 -0.46 -0.46 -1 Unit V mA V V V V Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Device thermal performances All the figures given in this section are obtained assuming that the QFN device is cooled down only by conduction through the package thermal pad (no convection mode considered). The temperature is monitored at the package back-side interface (Tcase) as shown below. The system maximum temperature must be adjusted in order to guarantee that Tcase remains below the maximum value specified in the next table. So, the PCB system must be designed to comply with this requirement. A derating must be applied on the dissipated power if the Tcase temperature cannot be maintained below the maximum temperature specified (see the curve Pdiss. Max) in order to guarantee the nominal device life time (MTTF). DEVICE THERMAL SPECIFICATION : CHR3763-QDG Recommended max. junction temperature (Tj max) : 139 Junction temperature absolute maximum rating : 175 Max. continuous dissipated power (Pdiss. Max.) : 0.3 (1) => Pdiss. Max. derating above Tcase = 85 C : 5 Junction-Case thermal resistance (Rth J-C)(2) : 201.5 Minimum Tcase operating temperature(3) : -40 Maximum Tcase operating temperature(3) : 85 Minimum storage temperature : -55 Maximum storage temperature : 150 C C W mW/C C/W C C C C (1) Derating at junctio n temperature co nstant = Tj max. (2) Rth J-C is calculated fo r a wo rst case co nsidering the ho t t e s t junc t io n o f the M M IC and all the devices biased. (3) Tcase=P ackage back side temperature measured under the die-attach-pad (see the drawing belo w). 0.3 0.2 0.15 0.1 0.05 Pdiss. Max. @Tj <Tj max (W) -50 -25 0 25 50 75 100 125 0 150 Pdiss. Max. @Tj <Tj max (W) 0.25 Tcase Example: QFN 16L 3x3 Location of temperature reference point (Tcase) on package's bottom side Tcase (C) 6.4 Ref. : DSCHR3763-QDG3324 - 20 Nov 13 4/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Typical Board Measurements Tamb.= +25C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm These values are representative of onboard measurements as defined on the drawing in paragraph "Evaluation mother board". Data are given in the package access planes. Conversion Gain versus RF & LO power at IF = 2GHz (LSB mode) 20 19 18 17 Conversion Gain (dB) 16 15 14 13 12 11 P_LO= 7dBm P_LO= 5dBm P_LO= 3dBm P_LO= 1dBm 10 9 8 7 6 5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 17 17.5 18 RF Frequency (GHz) Image Rejection versus RF and IF frequencies 60 55 50 Image rejection (dBc) 45 LSB at IF= 1GHz USB at IF= 1GHz LSB at IF= 2GHz USB at IF= 2GHz LSB at IF= 3.5GHz USB at IF=3.5GHz 40 35 30 25 20 15 10 5 0 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 17 17.5 18 RF Frequency (GHz) Ref. : DSCHR3763-QDG3324 - 20 Nov 13 5/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Typical Board Measurements Tamb.= +25C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm Noise Figure versus RF and IF frequencies (LSB mode) 6 5,5 5 IF= 1GHz Noise Figure (dB) 4,5 IF= 2GHz 4 IF= 3.5GHz 3,5 3 2,5 2 1,5 1 0,5 0 11 11,5 12 12,5 13 13,5 14 14,5 15 15,5 16 16,5 17 -13 -12 RF Frequency (GHz) Input IP3 versus LO power at RF =14.5GHz & IF = 2GHz (USB mode) 10 8 P_LO= 7dBm P_LO= 5dBm P_LO= 3dBm P_LO= 1dBm Input IP3 (dBm) 6 4 2 0 -2 -4 -6 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 Input Power DCL (dBm) Ref. : DSCHR3763-QDG3324 - 20 Nov 13 6/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Typical Board Measurements Tamb.= +25C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm Input IP3 versus RF frequency at IF = 2GHz (USB & LSB modes) 10 8 Input IP3 (dBm) 6 USB at RF= 16.5GHz LSB at RF= 16.5GHz USB at RF= 14.5GHz LSB at RF= 14.5GHz USB at RF= 12.5GHz LSB at RF= 12.5GHz 4 2 0 -2 -4 -6 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 Input Power DCL (dBm) Input IP3 versus RF frequency at IF = 3.5GHz (USB & LSB modes) 10 8 Input IP3 (dBm) 6 4 2 0 -2 -4 USB at RF= 16GHz LSB at RF= 16GHz USB at RF= 14.5GHz LSB at RF= 14.5GHz USB at RF= 12GHz LSB at RF= 12GHz -6 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 Input Power DCL (dBm) Ref. : DSCHR3763-QDG3324 - 20 Nov 13 7/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Typical Board Measurements Tamb.= +25C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm Conversion Gain versus temperature at IF = 1GHz (USB & LSB modes) 20 19 18 17 Conversion Gain (dB) 16 15 14 13 12 11 10 LSB at 85C LSB at 25C LSB at -40C 9 8 7 USB at 85C USB at 25C USB at -40C 6 5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 17 17.5 18 17 17.5 18 RF Frequency (GHz) Conversion Gain versus temperature at IF = 3.5GHz (USB & LSB modes) 20 19 18 17 Conversion Gain (dB) 16 15 14 13 12 11 10 9 LSB at 85C LSB at 25C LSB at -40C 8 7 6 USB at 85C USB at 25C USB at -40C 5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 RF Frequency (GHz) Ref. : DSCHR3763-QDG3324 - 20 Nov 13 8/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Typical Board Measurements Tamb.= +25C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm Noise Figure versus temperature at IF = 3.5GHz (USB mode) 6 5,5 85C 5 25C Noise Figure (dB) 4,5 -40C 4 3,5 3 2,5 2 1,5 1 0,5 0 10 10,5 11 11,5 12 12,5 13 13,5 14 14,5 15 15,5 16 16,5 17 17,5 18 RF Frequency (GHz) Input IP3 versus temperature at IF = 2GHz (USB & LSB modes - RF = -20dBm DCL) 10 8 Input IP3 (dBm) 6 4 2 0 -2 -4 USB at 85C LSB at 85C USB at 25C LSB at 25C USB at -40C LSB at -40C -6 11 12 13 14 15 16 17 RF Frequency (GHz) Ref. : DSCHR3763-QDG3324 - 20 Nov 13 9/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Typical Board Measurements Tamb.= +25C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm Input IP3 versus temperature at RF = 14.5GHz (USB & LSB modes - RF = -20dBm DCL) 10 8 Input IP3 (dBm) 6 4 2 0 -2 -4 USB at 85C LSB at 85C USB at 25C LSB at 25C USB at -40C LSB at -40C -6 0.5 1 1.5 2 2.5 3 3.5 4 IF Frequency (GHz) Return Loss LO & RF 0 -5 Return Loss (dB) -10 -15 -20 -25 LO Return Loss -30 RF Return Loss -35 -40 5 7.5 10 12.5 15 17.5 20 22.5 25 Frequency (GHz) Ref. : DSCHR3763-QDG3324 - 20 Nov 13 10/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Typical Board Measurements Tamb.= +25C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm Spurious on IF outputs RF = LO + IF P_RF = -20dBm @ 14.5GHz / P_LO = +5dBm @ 12.5GHz mRF 0 1 2 3 4 0 xx 23 >90 >90 >90 nLO 2 27 38 29 >90 >90 1 13 0 60 >90 >90 3 47 44 50 53 >90 4 >90 >90 58 >90 >90 All values in dBc below IF power level (IF = 2GHz). Data measured without external hybrid coupler. Definition of the package access planes The package access planes are symmetrical from the axis of the package (see drawing beside). The input and output reference planes are located at 3.18mm offset (input wise and output wise respectively) from this axis. 3.18 Ref. : DSCHR3763-QDG3324 - 20 Nov 13 11/16 3.18 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Package outline (1) Matt tin, Lead Free Units : From the standard : (Green) mm JEDEC MO-220 (VGGD) 25- GND 12345678- Nc IF_Q Gnd(2) Gnd(2) IF_I Nc Nc Gnd(2) 910111213141516- RF in Gnd(2) Nc VG1 VD1 VG2 VD2 Nc 1718192021222324- VG4 VD3 VG3 Nc Gnd(2) LO in Gnd(2) Nc (1) The package outline drawing included in this data-sheet is given for indication. Refer to the application note AN0017 (http://www.ums-gaas.com) for exact package dimensions. (2) It is strongly recommended to ground all pins marked "Gnd" through the PCB board. Ensure that the PCB board is designed to provide the best possible ground to the package. Ref. : DSCHR3763-QDG3324 - 20 Nov 13 12/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Evaluation mother board Compatible with the proposed footprint. Based on typically Ro4003 / 8mils or equivalent. Using a micro-strip to coplanar transition to access the package. Recommended for implementation of this product on a module board. Decoupling capacitors of 100pF 5% and 10nF 10% are recommended for all DC accesses. See application note AN0017 for details. Hybrid coupler 90 for 1-2GHz or 2-4GHz. Ref. : DSCHR3763-QDG3324 - 20 Nov 13 13/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter NC GND LO IN GND NC VG3 Notes 24 23 22 21 20 19 2 17 VG4 GND 3 16 NC GND 4 15 VD2 IF_I 5 14 VG2 6 13 VD1 7 8 9 10 11 12 VG1 NC NC IF_Q GND VD3 RF IN 18 GND 1 NC NC ESD protections are implemented on gate DC bias accesses and RF input. The DC connections do not include any decoupling capacitor in package, therefore it is mandatory to provide a good external DC decoupling (100pF + 10nF) on the PC board, as close as possible to the package. Ref. : DSCHR3763-QDG3324 - 20 Nov 13 14/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter DC Schematic LNA: 3V, 45mA LO Buffer: 3V, 35mA VD3 = 3V 17mA 49.5mA 18mA 49.5mA 50 1 k x3 VG3 # -0.46V Ref. : DSCHR3763-QDG3324 - 20 Nov 13 15/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3763-QDG 12-16GHz Integrated Down Converter Recommended package footprint Refer to the application note AN0017 available at http://www.ums-gaas.com for package foot print recommendations. SMD mounting procedure For the mounting process standard techniques involving solder paste and a suitable reflow process can be used. For further details, see application note AN0017. Recommended environmental management UMS products are compliant with the regulation in particular with the directives RoHS N2011/65 and REACh N1907/2006. More environmental data are available in the application note AN0019 also available at http://www.ums-gaas.com. Recommended ESD management Refer to the application note AN0020 available at http://www.ums-gaas.com for ESD sensitivity and handling recommendations for the UMS package products. Ordering Information QFN 4x4 package: CHR3763-QDG/XY Stick: XY = 20 Tape & reel: XY = 21 Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use as critical components in life support devices or systems without express written approval from United Monolithic Semiconductors S.A.S. Ref. : DSCHR3763-QDG3324 - 20 Nov 13 16/16 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Quebec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34