CHR3763-QDG
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
1/16
Specifications subject to change without notice
United Monolithic Semiconductors S.A.S.
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
12-16GHz Integrated Down Converter
GaAs Monolithic Microwave IC in SMD leadless package
Description
The CHR3763-QDG is a multifunction
monolithic receiver, which integrates a
balanced cold FET mixer, a LO buffer, and a
RF low noise amplifier.
It is designed for a wide range of
applications, from military to commercial
communication systems.
The circuit is manufactured with a pHEMT
process, 0.25µm gate length.
It is supplied in RoHS compliant SMD
package.
Main Features
Conversion Gain & Noise Figure versus RF
frequency @ IF = 2GHz (LSB mode)
■ Broadband RF performances: 12-16GHz
■ 12dB Conversion Gain
■ 2.3dB Noise Figure
■ 0dBm Input IP3
■ DC bias: Vd=3.0V @Id= 80mA
■ 24L-QFN4x4
■ MSL1
Main Electrical Characteristics
Tamb.= +25°C
Symbol
Parameter
Min
Typ
Max
Unit
FRF
RF Frequency
12
16
GHz
FIF
IF frequency
DC
3.5
GHz
G
Conversion gain
12
dB
NF
Noise Figure
2.3
dB
0
2
4
6
8
10
12
14
16
18
20
10 10,5 11 11,5 12 12,5 13 13,5 14 14,5 15 15,5 16 16,5 17 17,5 18
Conversion Gain & Noise Figure (dB)
RF Frequency (GHz)
Conversion Gain
NF
UMS
A3667A
YYWWG
UMS
A3667A
YYWWG
UMS
A3688A
YYWWG
UMS
A3667A
YYWWG
UMS
A3667A
YYWWG
UMS
A3688A
YYWWG
UMS
R3763
YYWW
CHR3763-QDG
12-16GHz Integrated Down Converter
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
2/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Electrical Characteristics
Tamb.= +25°C, VD1= VD2= VD3 = +3.0V (1)
Symbol
Parameter
Min
Typ
Max
Unit
FRF
RF Frequency range
12
16
GHz
FLO
LO frequency range
8.5
19.5
GHz
FIF
IF frequency range
DC
3.5
GHz
G
Conversion gain (2)
12
dB
NF
Noise Figure
2.3
dB
Im_rej
Image rejection (2)
20
dBc
PLO
LO Input power
5
dBm
IIP3
Input IP3
0
dBm
LO RL
LO return loss
12
dB
RF RL
RF return loss
10
dB
VDx
DC drain voltage (1)
3
V
VG1
1st stage LNA DC gate voltage
-0.52
V
VG2
2nd stage LNA DC gate voltage
-0.46
V
VG3
LO buffer DC gate voltage
-0.46
V
VG4
Mixer DC gate voltage
-1
V
Id
Total drain current (ID1+ID2+ID3) (3)
80
mA
These values are representative of onboard measurements as defined on the drawing in
paragraph "Evaluation mother board".
(1) VD1: 1st stage LNA drain bias voltage. VD2: 2nd stage LNA drain bias voltage.
(1) VD3: LO-chain drain bias voltage.
(2) An external combiner 90° is required on I / Q.
(3) ID1: 1st stage LNA drain current, typically 14mA, should be tuned with VG1.
(3) ID2: 2nd stage LNA drain current, typically 31mA, should be tuned with VG2.
(3) ID3: LO-chain drain current, typically 35mA, should be tuned with VG3.
Electrostatic discharge sensitive device observe handling precautions!
12-16GHz Integrated Down Converter
CHR3763-QDG
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
3/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Absolute Maximum Ratings (1)
Tamb.= +25°C
Symbol
Parameter
Values
Unit
Vdx
Drain bias voltage
3.5
V
Id
Drain bias current
120
mA
VG1,VG2
LNA gate bias voltages
-2 to +0.4
V
VG3
LO buffer gate bias voltage
-2 to +0.4
V
VG4
Mixer gate bias voltage
-2 to +0.4
V
P_RF
Maximum peak input power overdrive (2)
+15
dBm
P_LO
Maximum LO input power
+10
dBm
Tj
Junction temperature
175
°C
Ta
Operating temperature range
-40 to +85
°C
Tstg
Storage temperature range
-55 to +150
°C
(1) Operation of this device above anyone of these parameters may cause permanent
damage.
(2) Duration < 1s.
Typical Bias Conditions
Tamb.= +25°C
Symbol
Pad No
Parameter
Values
Unit
VDx
13,15,18
DC drain voltages
3
V
Id
13,15,18
Total drain current
80
mA
VG1
12
1st stage LNA DC gate voltage (14mA)
-0.52
V
VG2
14
2nd stage LNA DC gate voltage (31mA)
-0.46
V
VG3
19
LO buffer DC gate voltage (35mA)
-0.46
V
VG4
17
Mixer DC gate voltage
-1
V
CHR3763-QDG
12-16GHz Integrated Down Converter
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
4/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Device thermal performances
All the figures given in this section are obtained assuming that the QFN device is cooled
down only by conduction through the package thermal pad (no convection mode considered).
The temperature is monitored at the package back-side interface (Tcase) as shown below.
The system maximum temperature must be adjusted in order to guarantee that Tcase
remains below the maximum value specified in the next table. So, the PCB system must be
designed to comply with this requirement.
A derating must be applied on the dissipated power if the Tcase temperature cannot be
maintained below the maximum temperature specified (see the curve Pdiss. Max) in order to
guarantee the nominal device life time (MTTF).
Recommended max. junction temperature (Tj max) : 139 °C
Junction temperature absolute maximum rating : 175 °C
Max. continuous dissipated power (Pdiss. Max.) : 0.3 W
=>
Pdiss. Max. derating above Tcase(1)=85 °C : 5 mW/°C
Junction-Case thermal resistance (Rth J-C)(2) : 201.5 °C/W
Minimum Tcase operating temperature(3) : -40 °C
Maximum Tcase operating temperature(3) :85 °C
Minimum storage temperature : -55 °C
Maximum storage temperature : 150 °C
(1) Derating at junction temperature co nstant = Tj max.
(2) Rth J-C is calculated for a wo rst case co nsidering the ho t t est junc t io n o f the M M IC and all the devices biased.
(3) Tcase=Package back side temperature measured under the die-attach-pad (see the drawing below).
6.4
DEVICE THERMAL SPECIFICATION : CHR3763-QDG
0
0.05
0.1
0.15
0.2
0.25
0.3
-50 -25 025 50 75 100 125 150
Pdiss. Max. @Tj <Tj max (W)
Tcase (°C)
Pdiss. Max. @Tj <Tj max (W)
Tcase
Example: QFN 16L 3x3
Location of temperature
reference point (Tcase)
on package's bottom side
12-16GHz Integrated Down Converter
CHR3763-QDG
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
5/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Typical Board Measurements
Tamb.= +25°C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm
These values are representative of onboard measurements as defined on the drawing in
paragraph "Evaluation mother board". Data are given in the package access planes.
Conversion Gain versus RF & LO power at IF = 2GHz
(LSB mode)
Image Rejection versus RF and IF frequencies
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 17 17.5 18
Conversion Gain (dB)
RF Frequency (GHz)
P_LO= 7dBm
P_LO= 5dBm
P_LO= 3dBm
P_LO= 1dBm
0
5
10
15
20
25
30
35
40
45
50
55
60
10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 17 17.5 18
Image rejection (dBc)
RF Frequency (GHz)
LSB at IF= 1GHz
USB at IF= 1GHz
LSB at IF= 2GHz
USB at IF= 2GHz
LSB at IF= 3.5GHz
USB at IF=3.5GHz
CHR3763-QDG
12-16GHz Integrated Down Converter
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
6/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Typical Board Measurements
Tamb.= +25°C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm
Noise Figure versus RF and IF frequencies
(LSB mode)
Input IP3 versus LO power at RF =14.5GHz & IF = 2GHz
(USB mode)
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
5
5,5
6
11 11,5 12 12,5 13 13,5 14 14,5 15 15,5 16 16,5 17
Noise Figure (dB)
RF Frequency (GHz)
IF= 1GHz
IF= 2GHz
IF= 3.5GHz
-6
-4
-2
0
2
4
6
8
10
-27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12
Input IP3 (dBm)
Input Power DCL (dBm)
P_LO= 7dBm
P_LO= 5dBm
P_LO= 3dBm
P_LO= 1dBm
12-16GHz Integrated Down Converter
CHR3763-QDG
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
7/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Typical Board Measurements
Tamb.= +25°C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm
Input IP3 versus RF frequency at IF = 2GHz
(USB & LSB modes)
Input IP3 versus RF frequency at IF = 3.5GHz
(USB & LSB modes)
-6
-4
-2
0
2
4
6
8
10
-27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12
Input IP3 (dBm)
Input Power DCL (dBm)
USB at RF= 16.5GHz
LSB at RF= 16.5GHz
USB at RF= 14.5GHz
LSB at RF= 14.5GHz
USB at RF= 12.5GHz
LSB at RF= 12.5GHz
-6
-4
-2
0
2
4
6
8
10
-27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12
Input IP3 (dBm)
Input Power DCL (dBm)
USB at RF= 16GHz
LSB at RF= 16GHz
USB at RF= 14.5GHz
LSB at RF= 14.5GHz
USB at RF= 12GHz
LSB at RF= 12GHz
CHR3763-QDG
12-16GHz Integrated Down Converter
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
8/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Typical Board Measurements
Tamb.= +25°C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm
Conversion Gain versus temperature at IF = 1GHz
(USB & LSB modes)
Conversion Gain versus temperature at IF = 3.5GHz
(USB & LSB modes)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 17 17.5 18
Conversion Gain (dB)
RF Frequency (GHz)
LSB at 85°C
USB at 85°C
LSB at 25°C
USB at 25°C
LSB at -40°C
USB at -40°C
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 17 17.5 18
Conversion Gain (dB)
RF Frequency (GHz)
LSB at 85°C
USB at 85°C
LSB at 25°C
USB at 25°C
LSB at -40°C
USB at -40°C
12-16GHz Integrated Down Converter
CHR3763-QDG
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
9/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Typical Board Measurements
Tamb.= +25°C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm
Noise Figure versus temperature at IF = 3.5GHz
(USB mode)
Input IP3 versus temperature at IF = 2GHz
(USB & LSB modes – RF = -20dBm DCL)
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
5
5,5
6
10 10,5 11 11,5 12 12,5 13 13,5 14 14,5 15 15,5 16 16,5 17 17,5 18
Noise Figure (dB)
RF Frequency (GHz)
85°C
25°C
-40°C
-6
-4
-2
0
2
4
6
8
10
11 12 13 14 15 16 17
Input IP3 (dBm)
RF Frequency (GHz)
USB at 85°C
LSB at 85°C
USB at 25°C
LSB at 25°C
USB at -40°C
LSB at -40°C
CHR3763-QDG
12-16GHz Integrated Down Converter
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
10/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Typical Board Measurements
Tamb.= +25°C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm
Input IP3 versus temperature at RF = 14.5GHz
(USB & LSB modes – RF = -20dBm DCL)
Return Loss LO & RF
-6
-4
-2
0
2
4
6
8
10
0.5 1 1.5 2 2.5 3 3.5 4
Input IP3 (dBm)
IF Frequency (GHz)
USB at 85°C
LSB at 85°C
USB at 25°C
LSB at 25°C
USB at -40°C
LSB at -40°C
-40
-35
-30
-25
-20
-15
-10
-5
0
5 7.5 10 12.5 15 17.5 20 22.5 25
Return Loss (dB)
Frequency (GHz)
LO Return Loss
RF Return Loss
12-16GHz Integrated Down Converter
CHR3763-QDG
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
11/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Typical Board Measurements
Tamb.= +25°C, VD1= VD2= VD3= +3V, VG4= -1V, P_LO = +5dBm
Spurious on IF outputs
RF = LO + IF
P_RF = -20dBm @ 14.5GHz / P_LO = +5dBm @ 12.5GHz
nLO
mRF
0
1
2
3
4
0
xx
13
27
47
>90
1
23
0
38
44
>90
2
>90
60
29
50
58
3
>90
>90
>90
53
>90
4
>90
>90
>90
>90
>90
All values in dBc below IF power level (IF = 2GHz).
Data measured without external hybrid coupler.
Definition of the package access planes
The package access planes are symmetrical
from the axis of the package (see drawing
beside). The input and output reference
planes are located at 3.18mm offset (input
wise and output wise respectively) from this
axis.
3.18 3.18
CHR3763-QDG
12-16GHz Integrated Down Converter
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
12/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Package outline (1)
Matt tin, Lead Free
(Green)
1-
Nc
9-
RF in
17-
VG4
Units :
mm
2-
IF_Q
10-
Gnd(2)
18-
VD3
From the standard :
JEDEC MO-220
3-
Gnd(2)
11-
Nc
19-
VG3
(VGGD)
4-
Gnd(2)
12-
VG1
20-
Nc
25-
GND
5-
IF_I
13-
VD1
21-
Gnd(2)
6-
Nc
14-
VG2
22-
LO in
7-
Nc
15-
VD2
23-
Gnd(2)
8-
Gnd(2)
16-
Nc
24-
Nc
(1) The package outline drawing included in this data-sheet is given for indication. Refer to the
application note AN0017 (http://www.ums-gaas.com) for exact package dimensions.
(2) It is strongly recommended to ground all pins marked “Gnd” through the PCB board.
Ensure that the PCB board is designed to provide the best possible ground to the package.
12-16GHz Integrated Down Converter
CHR3763-QDG
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
13/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Evaluation mother board
■ Compatible with the proposed footprint.
■ Based on typically Ro4003 / 8mils or equivalent.
■ Using a micro-strip to coplanar transition to access the package.
■ Recommended for implementation of this product on a module board.
■ Decoupling capacitors of 100pF ±5% and 10nF ±10% are recommended for all DC
accesses.
■ See application note AN0017 for details.
■ Hybrid coupler 90° for 1-2GHz or 2-4GHz.
CHR3763-QDG
12-16GHz Integrated Down Converter
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
14/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Notes
ESD protections are implemented on gate DC bias accesses and RF input.
The DC connections do not include any decoupling capacitor in package, therefore it is
mandatory to provide a good external DC decoupling (100pF + 10nF) on the PC board, as
close as possible to the package.
1
3
4
2
6
5
7 8 9 10 11 12
13
14
15
16
17
18
19
20
21
2223
24
NC
IF_Q
GND
GND
IF_I
NC
VD3
VG4
NC
VD2
VG2
VD1
NC
GND
LO IN
GND
NC
VG3
NC
GND
RF IN
GND
NC
VG1
12-16GHz Integrated Down Converter
CHR3763-QDG
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
15/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
DC Schematic
LNA: 3V, 45mA
LO Buffer: 3V, 35mA
VD3 = 3V
1 k
x3
VG3 # -0.46V
49.5mA18mA
49.5mA17mA
50
CHR3763-QDG
12-16GHz Integrated Down Converter
Ref. : DSCHR3763-QDG3324 - 20 Nov 13
16/16
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
Recommended package footprint
Refer to the application note AN0017 available at http://www.ums-gaas.com for package foot
print recommendations.
SMD mounting procedure
For the mounting process standard techniques involving solder paste and a suitable reflow
process can be used. For further details, see application note AN0017.
Recommended environmental management
UMS products are compliant with the regulation in particular with the directives RoHS
N°2011/65 and REACh N°1907/2006. More environmental data are available in the
application note AN0019 also available at http://www.ums-gaas.com.
Recommended ESD management
Refer to the application note AN0020 available at http://www.ums-gaas.com for ESD
sensitivity and handling recommendations for the UMS package products.
Ordering Information
QFN 4x4 package:
CHR3763-QDG/XY
Stick: XY = 20
Tape & reel: XY = 21
Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors
S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of
patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use
as critical components in life support devices or systems without express written approval from United
Monolithic Semiconductors S.A.S.
