HMXADC9225 Radiation Hardened 12-Bit, 20 MSPS Monolithic A/D Converter Features n n n n n n n n n n n Monolithic 12-Bit, 20 MSPS A/D Converter Rad Hard: >500k Rad(Si) Total Dose Single +5 V Analog Supply Complete On-Chip S/H Amplifier Straight Binary Output Data 5V or 3.3V Digital and I/O Supply No Missing Codes Guaranteed Differential Nonlinearity Error: 0.4 LSB Signal-to-Noise and Distortion Ratio: 69.6 dB Spurious-Free Dynamic Range: -81 dB 28-Lead Ceramic Flat Pack Mixed Signal Rad Hard Process The HMXADC9225 is fabricated on space qualified SOI CMOS process. High-speed precision analog circuits are now combined with high-density logic circuits that can reliably withstand the harshest environments. Space Qualified Package The HMXADC9225 is packaged in a 28 lead ceramic flat pack. Low Power The HMXADC9225 at 335 mW consumes a fraction of the power of presently available in existing monolithic solutions. Output Enable (OE) The OE input allows user to put the tri-state digital outputs into a high impedance mode. Dual Power Supply Capability The HMXADC9225 uses a single +5 V power supply simplifying system power supply design. It also features a separate digital I/O power supply line to accommodate 3.3V and 5V logic families. On-Chip Sample-and-Hold (SHA) The versatile SHA input can be configured for either single-ended or differential inputs. The HMXADC9225 is a radiation hardened monolithic, single supply, 12-bit, 20 MSPS, analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier. The HMXADC9225 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20 MSPS data rates, and guarantees no missing codes over the full operating temperature range. The HMXADC9225 is fabricated on a radiation hardened SOI-IV Silicon On Insulator (SOI) process with very low power consumption. The input of the HMXADC9225 allows for easy interfacing to space and military imaging, sensor, and communications systems. With a truly differential input structure, the user can select a variety of input ranges and offsets including single-ended applications. The dynamic performance is excellent. The sample-and-hold amplifier (SHA) is well suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and well beyond the Nyquist rate. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. Block Diagram DRVDD REFP, REFN DRVSS VINP MDAC1 X16 S/H MDAC2 X4 MDAC3 X4 VINN Correct Logic A/D Clock In CML A/D 5 Clock Buffer A/D 3 3 4 REFT Diff Buffer IREF + - AVDD REFCOM RBIAS 5k Data Output Drivers Output Tri-State Control Master Bias CML Gen AVSS A/D VREF * = 0.1F in parallel with a 10uF External Reference Input Cap* 0.1uF 0.1uF 1 CLK DRVDD 28 2 BIT 12 (LSB) DRVSS 27 Data Output Bit 3 BIT 11 AVDD 26 BIT 1 Most Significant Bit (MSB) 4 BIT 10 AVSS 25 14 OE Output Enable (high active) 15 AVDD +5V Analog Supply 5 BIT 9 VIN B 24 16 AVSS Analog Ground 6 BIT 8 VIN A 23 17 RBIAS Reference Current Bias Resistor 18 VREF INPUT Reference Voltage Input 7 BIT 7 CML 22 19 REFCOMM Reference Common 8 BIT 6 REFT 21 20 REFB Noise Reduction Pin 21 REFT Noise Reduction Pin 9 BIT 5 REFB 20 22 CML Common Mode Level (AVDD/2) 10 BIT 4 REFCOM 19 23 VINA Analog Input (+) 11 BIT 3 VREF IN 18 24 VINB Analog Input (-) 25 AVSS Analog Ground 12 BIT 2 RBIAS 17 26 AVDD +5V Analog Supply 27 DRVSS Digital Output Driver Ground 28 DRDVDD +5V or 3.3V Digital Output Driver Supply Pin Name Description 1 CLK Clock Input 2 BIT 12 Least Significant Data Bit (LSB) 3-12 BIT 11 - 2 13 Output Enable REFB Pin Description Pin D0-D11 13 BIT 1 (MSB) AVSS 16 14 OE AVDD 15 Signal Definition Total Ionizing Radiation Dose The HMXADC9225 will meet all stated functional and electrical DRVDD specifications over the entire operating temperature range after The Digital Output Power Supply (DRVDD) can operate at either 5.0V the specified total ionizing radiation dose. All electrical and timing or 3.3V. The DRVDD voltage defines the interface voltage level for performance parameters will remain within specifications after all the digital I/O signals including Clock input, Output Enable, and all rebound at VDD = 5.0 V extrapolated to ten years of operation. Total data output signals. dose hardness is assured by wafer level testing of process monitor transistors using 10 KeV X-ray and Co60 radiation sources. Transistor Output Enable (OE) gate threshold shift correlations have been made between 10 KeV This signal controls the electrical state of the digital output drivers. X-rays applied at a dose rate of 1x105 rad(SiO2)/min at T=25C and A high logic level will enable the outputs and a low logic level will put gamma rays (Cobalt 60 source) to ensure that wafer level X-ray the output drivers into a high impedance state. testing is consistent with standard military radiation test environments. RBIAS Transient Pulse Ionizing Radiation R-Bias is required to create the internal bias currents. An external The HMXADC9225 will meet any functional or electrical specification resistor with a value of 5k shall be connected between pin 17 and after exposure to a radiation pulse up to the transient dose rate ground. survivability specification, when applied under recommended operating conditions. Note that the current conducted during the The R-Bias resistor can also be used to change the power pulse by the ADC inputs, outputs, and power supply may significantly consumption. By changing the resistor value, the current exceed the normal operating levels. The application design must consumption can be changed. The range of this feature not yet accommodate these effects. characterized. Soft Error Rate Voltage Reference Input The HMXADC9225 is not guaranteed to operate through an SEU The HMXADC9225 requires the user to provide an external voltage or dose rate event, but it will recover and continue to meet all reference as an INPUT to the device. The device is designed to specifications over the full temperature range after an event. operate using a 1.0V to 2.0V external voltage reference. The input range will then be defined by the VREF. Latchup and Snapback The HMXADC9225 will not latch up due to any of the above radiation The full scale signal input = 2 x VREF. Signals outside this range will exposure conditions when applied under recommended operating be considered "out of range". conditions. Fabrication with the SIMOX substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and CML (Common Mode Level) eliminates any potential SCR latchup structures. Sufficient transistor This signal is an analog output at a value of AVDD/2. It can be used body tie connections to the p- and n-channel substrates are made to as a reference for biasing external circuits to a "mid-rail" value. This ensure no source/drain snapback occurs. signal should be decoupled with a 0.1uF capacitor. Radiation Performance Analog Sampling Timing Diagram S2 S1 tC Analog Input tCH Clock Data Out tCL S3 S4 tOD Data 1 Output Enable Timing Diagram OE 50 D1-D12 85pF TDLZ TDHZ TDLZ TDHZ (a) (b) Output Enable Timing Diagram (a) and Effective Load (b) Switching Specifications (TMIN to TMAX with AVDD = +5V, DRVDD = +5V, CL = 85 pF) Parameter Symbol Min Clock Period (1) tC 50 Typ Max Units ns Clock Pulsewidth High (46% of tC ) (1) tCH 23 ns Clock Pulsewidth High (46% of tC ) (1) tCH 23 ns Output Delay tOD 3 25 ns High Z to Output High (DRVDD=5V) (2) TDZH_50 25 ns High Z to Output Low (DRVDD=5V) (2) TDZL_50 25 ns Output High to High Z (DRVDD=5V) (2) TDHZ_50 25 ns Output Low to High Z (DRVDD=5V) (2) TDLZ_50 25 ns High Z to Output High (DRVDD=3.3V) (2) TDZH_33 25 ns High Z to Output Low (DRVDD=3.3V) (2) TDZL_33 25 ns Output High to High Z (DRVDD=3.3V) (2) TDHZ_33 25 ns Output Low to High Z (DRVDD=3.3V) (2) TDLZ_33 25 ns (1) These are parameters of the input clock signal to the chip. (2) Refer to "Output Enable Timing Diagram" for waveform and loading. Radiation Specifications (TMIN to TMAX with AVDD = +5V, DRVDD = +5V, CL = 20 pF) Parameters Min Total Dose Hardness >5 x 105 Rad (Si) Dose Rate Upset Hardness >2.5 x 1012 Rad(Si)/sec Dose Rate Survivability >2.5 x 10 Rad(Si)/sec Soft Error Rate LET (1) 120 MeV cm2/mg 12 Soft Error Rate (2) Latch Up Max <1x10-10 Units Upsets/bit-day Immune (1) The HMXADC9225 will recover and continue to meet all specifications. (2) This error rate applies to only the logic portion of the device. Absolute Maximum Ratings (AVDD = +5V, DRVDD = +5V, unless otherwise noted) Parameters Min Max Units AVDD 6.5 Volts DRVDD 6.5 Volts AVSS -0.3 Volts DRVSS -0.3 Volts REFGND -0.3 Volts CLK, OE 6.5 Volts D1-D12 6.5 Volts VINA, VINB 6.5 Volts VREF 6.5 Volts REFT, REFB 6.5 Volts Package Thermal Resistance (JC) 2.0 C/W Junction Temperature +175 C (1) All voltages are with respect to VSS = 0V. Recommended Operating Conditions Parameters Min Type Max Units AVDD 4.75 5 5.25 Volts DRVDD (for 5V I/O operation) 4.75 5 5.25 Volts DRVDD (for 3.3V I/O operation) 3.0 3.3 3.6 Volts AVSS -0.3 0 Volts DRVSS -0.3 0 Volts REFGND -0.3 0 Volts CLK, OE DRVDD + 0.5 Volts D1-D125.5 Volts VINA, VINB 0.5 4.5 Volts VREF 1.0 2.0 Volts REFT, REFB5.5 Volts Operating Temperature (case) C -55 +125 (1) All voltages are with respect to VSS = 0V. ESD (Electrostatic Discharge) Sensitive The HMXADC9225 is rated as Class 1B ESD. Proper ESD precautions should be taken to avoid degradation or damage to the device. DC Specifications (AVDD = +5V, DRVDD = +5V, fSAMPLE = 20 MSPS, VREF 2.0V, VINB = 2.5V dc, TMIN to TMAX unless otherwise noted) Parameter Symbol Resolution (1) Min Typ Max Units 12Bits Max Conversion Rate (1)20 MHz Input Referred Noise VREF = 2V (1) 0.17 LSB rms Accuracy Integral Nonlinearity INL -2.5 Differential Nonlinearity DNL -1.0 1.2 2.5 0.4 1.0 LSB LSB No Missing Codes (1) 12 Bits guaranteed Zero Error (@ 25C) OFFSET -0.9 0.3 0.9 % FSR Gain Error (@ 25C) GAIN -2 0.5 2 % FSR Temperature Drift Zero Error (@ 25C) (1) +/- 2 PPM/C Gain Error (@ 25C) (1) +/- 26 PPM/C Input Span 4 V p-p Input Capacitance (1) 10 pF Analog Input External Voltage Reference Input Voltage (2) 1.0 Input Current 2.0 2.0 V 250 500 A Power Supply Currents IAVDD, IDVDD65 IDRVDD2 CML Output Current (3) 0.5 1.0 mA mA mA RBIAS Resistor Value5K (1) Guaranteed but not tested. (2) Recommended VREF tolerance is +/-110 mV. (3) It is recommended an external buffer be used for driving external circuitry. AC Specifications (AVDD = +5V, DRVDD = +5V, fSAMPLE = 20 MSPS, VREF 2.0V, TMIN to TMAX Differential Input unless otherwise noted) Parameter Symbol Min Typ Max Units Signal to Noise and Distortion fIN = 1MHz SINAD1 63 67 - dB Signal to Noise and Distortion fIN = 5MHz SINAD5 60 66 - dB Signal to Noise Ratio fIN = 1MHz SNR1 63 69 - dB Signal to Noise Ratio fIN = 5MHz SNR5 60 68 - dB Total Harmonic Distortion fIN = 1MHz THD1 - -70 -66 dB Total Harmonic Distortion fIN = 5MHz THD5 - -69 -66 dB Spurious Free Dynamic Range fIN = 1MHz SFDR1 70 72 - dB Spurious Free Dynamic Range fIN = 5MHz SFDR5 68 71 - dB Full Power Bandwidth (1) 120 MHz Small Signal Bandwidth (1) 120 MHz Aperture Delay (1) 1 ns Aperture Jitter (1) 4 ps rms Acquisition to Full Scale Step (1) 10 ns (1) Guaranteed but not tested. Digital Specifications (AVDD = +5V, DRVDD = +5V, unless otherwise noted) Parameter Symbol Min Typ Max Units Logic Inputs (CLK, OE) High Level Input Voltage (DRVDD = +5V) VIH_50 3.5 V High Level Input Voltage (DRVDD =+3.3V) VIH_33 2.3 V Low Level Input Voltage (DRVDD = +5V) VIL_50 1.0 V Low Level Input Voltage (DRVDD = +3.3V) VIL_33 1.0 V High Level Input Current (DRVDD=5V, VIN=5V) IIH_50 -10 10A Low Level Input Current (DRVDD=5V, VIN=0V) IIL_50 -10 10A High Level Input Current (DRVDD=3.3V, VIN=3.3V) IIH_33 -10 10A Low Level Input Current (DRVDD=3.3V, VIN=0V) IIL_33 -10 10A Input Capacitance (1) CIN 5 pF Logic Outputs (D1-D12 with DRVDD = +5V) High Level Output Voltage(IOH = 50A) VOH1_50 4.5 V High Level Output Voltage(IOH = 0.5mA) VOH2_50 2.4 V Low Level Output Voltage(IOL = 1.6mA) VOL2_50 0.4 V Low Level Output Voltage(IOL = 50A) VOL1_50 0.1 V High Z Output Current (DRVDD=5V, OE=0V, VOUT=5V) IOZH_50 -10 10A High Z Output Current (DRVDD=5V, OE=0v, VOUT=0V) IOZL_50 -10 10A High Level Output Voltage(IOH = 50A) VOH1_33 2.95 V High Level Output Voltage(IOH = 0.5mA) VOH2_33 2.80 V Low Level Output Voltage(IOL = 1.6mA) VOL2_33 0.4 V Low Level Output Voltage(IOL = 1.6mA) VOL2_33 0.4 V Logic Outputs (D1-D12 with DRVDD = +3.3V) High Z Output Current (DRVDD=3.3V, VOE=0V, VOUT=3.3V) IOZH_33 -10 10A High Z Output Current (DRVDD=3.3V, VOE=0V, VOUT=0V) IOZL_33 -10 10A Output Capacitance (1) COUT 5 pF (1) Guaranteed but not tested. Definitions of Specifications Gain Error The first code transition should occur at an analog value 1/2 LSB Integral Nonlinearity (INL) above negative full scale. The last transition should occur at an analog INL refers to the deviation of each individual code from a line drawn value 1 1/2 LSB below the nominal full scale. from "negative full scale" through "positive full scale." The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Temperature Drift The temperature drift for zero error and gain error specifies the Differential Nonlinearity (DNL, No Missing Codes) maximum change from the initial (+25C) value to the value at TMIN An ideal ADC exhibits code transitions that are exactly 1 LSB apart. or TMAX. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicate that all 4096 codes, respectively, must be present over all operating ranges. Aperature Drift Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. Zero Error Aperature Delay The major carry transition should occur for an analog value 1/2 LSB Aperture delay is a measure of the sample-and-hold amplifier (SHA) below VINA = VINB. Zero error is defined as the deviation of the performance and is measured from the rising edge of the clock input actual transition from that point. to when the input signal is held for conversion. Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio Total Harmonic Distortion (THD) S/N+D is the ratio of the rms value of the measured input signal to THD is the ratio of the rms sum of the first six harmonic components the rms sum of all other spectral components below the Nyquist to the rms value of the measured input signal and is expressed as a frequency, including harmonics but excluding dc. The value for S/ percentage or in decibels. N+D is expressed in decibels. Signal-to-Noise Ratio (SNR) Effective Number of Bits (ENOB) SNR is the ratio of the rms value of the measured input signal to For a sine wave, SINAD can be expressed in terms of the number of the rms sum of all other spectral components below the Nyquist bits. Using the following formula, frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. N = (SINAD - 1.76)/6.02 Spurious Free Dynamic Range (SFDR) it is possible to get a measure of performance expressed as N, the SFDR is the difference in dB between the rms amplitude of the input effective number of bits. Thus, effective number of bits for a device for signal and the peak spurious signal. sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Typical DNL (10MSPS) Typical INL (10MSPS) Functional Description The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the The HMXADC9225 is a complete high performance single-supply converter is capable of capturing a new input sample every clock 12-bit ADC. The analog input range of the HMXADC9225 is highly cycle, it actually takes three clock cycles for the conversion to be fully flexible allowing for either single-ended or differential inputs of varying processed and appear at the output. This latency is not a concern in amplitudes that can be AC or DC coupled. most applications. The digital output is latched into an output buffer to drive the output pins. It utilizes four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on an SOI CMOS The HMXADC9225 uses both edges of the clock in its internal timing process. Each stage of the pipeline, excluding the last stage, consists circuitry (see Timing Diagram and specification page for exact timing of a low-resolution flash A/D connected to a switched capacitor requirements). The A/D samples the analog input on the rising edge DAC and interstage residue amplifier (MDAC). The residue amplifier of the clock input. During the clock low time (between the falling edge amplifies the difference between the reconstructed DAC output and rising edge of the clock), the input SHA is in the sample mode; and the flash input for the next stage in the pipeline. One bit of during the clock high time it is in hold. System disturbances just prior redundancy is used in each of the stages to facilitate digital correction to the rising edge of the clock and/or excessive clock jitter may cause of flash errors. The last stage simply consists of a flash A/D. the input SHA to acquire the wrong value, and should be minimized. Analog Input Operation Clock Input and Considerations The HMX9225 internal timing uses the two edges of the clock input Figure 1 shows the equivalent analog input of the HMXADC9225, to generate a variety of internal timing signals. The clock input must which consists of a differential sample-and-hold amplifier (SHA). The meet or exceed the minimum specified pulse width high and low (tCH differential input structure of the SHA is highly flexible, allowing the and tCL) specifications for the given A/D as defined in the Switching devices to be easily configured for either a differential or single-ended Specifications at the beginning of the data sheet to meet the rated input. The dc offset, or common mode voltage, of the input(s) can performance specifications. be set to accommodate either single-supply or dual-supply systems. Also, note that the analog inputs, VINA and VINB, are interchangeable For example, the clock input to the HMX9225 operating at 20 MSPS with the exception that reversing the inputs to the VINA and VINB may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum specified tCH and tCL is 23 ns. For low pins results in a polarity inversion. clock rates, the duty cycle may deviate from this range to the extent that both tCH and tCL are satisfied. VIN A All high-speed high resolution A/Ds are sensitive to the quality of - the clock input. The degradation in SNR at a given full-scale input frequency (fIN) due to only aperture jitter (tA) can be calculated with + VIN B the following equation: SNR = 20 log10 1 2p IN tA Figure 1 - Analog Input Equivalent Circuit In the equation, the rms aperture jitter, tA, represents the root sum The full scale signal input = 2 x VREF. square of all the jitter sources, which include the clock input, analog input signal, and A/D aperture jitter specification. Under sampling Digital Outputs applications are particularly sensitive to jitter. The HMXADC9225 output data is presented in positive true straight binary for all input ranges. The table below indicates the output data Clock input should be treated as an analog signal in cases where formats for various input ranges regardless of the selected input aperture jitter may affect the dynamic range of the HMXADC9225. range. A twos complement output data format can be created by Power supplies for clock drivers should be separated from the A/D inverting the MSB. The outputs can be placed in high impedance output driver supplies to avoid modulating the clock signal with tri-state mode and are controlled by the Output Enable (OE) signal. digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source Output Data Format (by gating, dividing, or other method), it should be retimed by the Input (V) Condition (V) Digital Output original clock at the last step. The clock input is referred to the analog VINA-VINB < - VREF 0000 0000 0000 supply. Its logic threshold is AVDD/2. VINA-VINB = - VREF 0000 0000 0000 VINA-VINB =0 1000 0000 0000 VINA-VINB = + VREF - 1 LSB 1111 1111 1111 VINA-VINB > + VREF 1111 1111 1111 The HMXADC9225 has a clock tolerance of 5% at 20 MHz and should be a 50% duty cycle. The input circuitry for the CLOCK pin is designed to accommodate CMOS inputs. The quality of the logic input, particularly the rising Digital Output Driver Considerations (DRVDD) edge, is critical in realizing the best possible jitter performance of the The HMX9225 output drivers shall be operated at 5.0 volts or part: the faster the rising edge, the better the jitter performance. at 3.3 volts. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive As a result, careful selection of the logic family for the clock driver, as currents tend to cause glitches on the supplies and may affect well as the fanout and capacitive load on the clock line, is important. SINAD performance. Applications requiring the ADC to drive large Jitter-induced errors become more predominant at higher frequency, capacitive loads or large fanout may require additional decoupling large amplitude inputs, where the input slew rate is greatest. capacitors on DRVDD. In extreme cases, external buffers or latches Most of the power dissipated by the HMX9225 is from the analog may be required. power supplies. However, lower clock speeds will reduce digital current. Grounding and Decoupling Analog and Digital Grounding Proper grounding is essential in any high speed, high-resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. Quality and Radiation Hardness Assurance Honeywell maintains a high level of product integrity through process control, utilizing statistical process and six sigma controls. It is part of a "Total Quality Assurance Program", the computer based process performance tracking system and a radiation hardness assurance strategy. Screening Levels Honeywell offers several levels of device screening to meet your 2. The minimization of the impedance associated with ground and power paths. needs. "Engineering Devices" are available with limited performance and screening for prototype development and evaluation testing. Hi-Rel Level B based and S based devices undergo additional 3. The inherent distributed capacitor formed by the power plane, screening per the requirements of MIL-STD-883. PCB insulation and ground plane. These characteristics result in both a reduction of electromagnetic Reliability interference (EMI) and an overall improvement in performance. Honeywell understands the stringent reliability requirements that space and defense systems requires and has extensive experience It is important to design a layout that prevents noise from coupling in reliability testing on programs of this nature. Reliability attributes onto the input signal. Digital signals should not be run in parallel of the SOI process were characterized by testing specially designed with input signal traces and should be routed away from the input structures to evaluate failure mechanisms including hot carriers, circuitry. While the HMXADC9225 features separate analog and electro-migration, and time-dependent dielectric breakdown. The driver ground pins, it should be treated as an analog component. results are fed back to improve the process to ensure the highest The AVSS and DRVSS pins must be joined together directly under reliability products. the HMXADC9225. A solid ground plane under the A/D is acceptable if the power and ground return currents are carefully managed. In addition, our products are subjected to dynamic, accelerated life Alternatively, the ground plane under the A/D may contain serrations tests. The packages used are qualified through MIL-STD-883, to steer currents in predictable directions where cross coupling TM 5005 Class S. The product screening flow can be modified to between analog and digital would otherwise be unavoidable. meet the customer's specific requirements. Quality conformance Analog and Digital Driver Supply Decoupling The HMXADC9225 features separate analog and driver supply and ground pins, helping to minimize digital corruption of sensitive analog signals. In general, AVDD, the analog supply, should be decoupled to AVSS, the analog common, as close to the chip as physically possible. It is recommended to use 0.1 uF ceramic chip and 10 uF tantalum capacitors for the AVDD and DRVDD power inputs. A 0.1 uF ceramic chip capacitor is adequate on the CML pin. testing is performed as an option on all production lots to ensure on-going reliability. Package Definition L1 NO.1 NO.28 NO.14 NO.15 A E1 E2 e Dimensions b D1 Symbol A1 c (0.55) (.300) .026 MIN Ordering Information Min. Norm Max. A .108 .120 .133 A1 .098 .107 .117 b .015 .017 .019 c .004 .005 .006 D1 .404 .410 .416 E1 .712 .720 .728 E2 .645 .650 .655 (Inches) e .050 BSC L1 1.150 BSC N 28 H MX ADC 9225 Source H = Honeywell Process M = Mixed Signal X = SOI Part Type Part Number N Customer must specify QCI requirements. Package Destination N = 28 Pin Flat Pack (2) These receive the Class V screening but do not have QCI included. (3) Engineering Model Description: Parameters are tested -55C to 125C, 24 hour burn-in, no radiation guaranteed To learn more about Honeywell's radiation hardened integrated circuit products and technologies, visit www.honeywell.com/radhard. Honeywell reserves the right to make changes to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Honeywell Aerospace 12001 Highway 55 Plymouth, MN 55441 Tel: 800-323-8295 www.honeywell.com N61-1063-000-000 December 2010 (c) 2010 Honeywell International Inc. H Screen Level Z = Class S\QML V Equivalent (1) Y = Class B\QML Q Equivalent (2) E = Eng. Model(3) NAND00 (1) These receive the Class V screening and QCI is included. Z Total Dose Hardness G = 5x105 rad (Si) N = No Level Guaranteed (3)