TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS Check for Samples: TPS65021 FEATURES 1 * 1.2 A, 97% Efficient Step-Down Converter for System Voltage (VDCDC1) * 1 A, Up to 95% Efficient Step-Down Converter for Memory Voltage (VDCDC2) * 900 mA, 90% Efficient Step-Down Converter for Processor Core (VDCDC3) * 30 mA LDO/Switch for Real Time Clock (VRTC) * 2 x 200 mA General-Purpose LDO * Dynamic Voltage Management for Processor Core * Preselectable LDO Voltage Using Two Digital Input Pins * Externally Adjustable Reset Delay Time * Battery Backup Functionality * Separate Enable Pins for Inductive Converters * I2CTM Compatible Serial Interface * 85-A Quiescent Current * Low Ripple PFM Mode * Thermal Shutdown Protection * 40-Pin 6 mm x 6 mm QFN Package DESCRIPTION 234 APPLICATIONS * * * * * * * The TPS65021 is an integrated Power Management IC for applications powered by one Li-Ion or Li-Polymer cell, and which require multiple power rails. The TPS65021 provides three highly efficient, step-down converters targeted at providing the core voltage, peripheral, I/O and memory rails in a processor based system. All three step-down converters enter a low-power mode at light load for maximum efficiency across the widest possible range of load currents. The TPS65021 also integrates two general-purpose 200 mA LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage range between 1.5 V and 6.5 V, allowing them to be supplied from one of the step-down converters or directly from the battery. The default output voltage of the LDOs can be digitally set to 4 different voltage combinations using the DEFLDO1 and DEFLDO2 pins. The serial interface can be used for dynamic voltage scaling, masking interrupts, or for dis/enabling and setting the LDO output voltages. The interface is compatible with the Fast/Standard mode I2C specification, allowing transfers at up to 400 kHz. The TPS65021 is available in a 40-pin (RHA) QFN package, and operates over a free-air temperature of -40C to 85C. PDA Cellular/Smart Phone Internet Audio Player Digital Still Camera Digital Radio Player Split Supply TMS320TM DSP Family and P Solutions: OMAPTM1610, OMAP1710, OMAP330, XScale Bulverde, Samsung ARM-Based Processors, etc. Intel(R) PXA270, etc. 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320, OMAP, PowerPAD are trademarks of Texas Instruments. Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Electronics. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005-2011, Texas Instruments Incorporated TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (2) TA PACKAGE (1) PART NUMBER (2) -40C to 85C 40 pin QFN (RHA) TPS65021RHA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. The RHA package is available in tape and reel. Add the R suffix (TPS65021RHAR) to order quantities of 2500 parts per reel. Add the T suffix (TPS65021RHAT) to order quantities of 250 parts per reel. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE VI Input voltage range on all pins except AGND and PGND pins with respect to AGND Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 Peak Current at all other pins Continuous total power dissipation TA Operating free-air temperature TJ Maximum junction temperature V 2000 mA 1000 mA See Dissipation Rating Table Tstg Storage temperature (1) UNIT -0.3 to 7 -40 to 85 C 125 C -65 to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability THERMAL INFORMATION TPS65021 THERMAL METRIC (1) RHA UNITS 40 PINS JA Junction-to-ambient thermal resistance 31.6 JCtop Junction-to-case (top) thermal resistance 18.2 JB Junction-to-board thermal resistance 6.6 JT Junction-to-top characterization parameter 0.2 JB Junction-to-board characterization parameter 6.5 JCbot Junction-to-case (bottom) thermal resistance 1.7 (1) C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX Input voltage range step-down convertors (VINDCDC1, VINDCDC2, VINDCDC3); pins need to be tied to the same voltage rail 2.5 6 Output voltage range for VDCDC1 step-down convertor (1) 0.6 VINDCDC1 Output voltage range for VDCDC2 (mem) step-down convertor (1) 0.6 VINDCDC2 Output voltage range for VDCDC3 (core) step-down convertor (1) 0.6 VINDCDC3 VI Input voltage range for LDOs (VINLDO1, VINLDO2) 1.5 6.5 VO Output voltage range for LDOs (VLDO1, VLDO2) 1 VINLDO1-2 IO(DCDC2) Output current at L1 VCC VO (1) 2 1200 UNIT V V V V mA When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) Inductor at L1 (2) MIN NOM 2.2 3.3 CI(DCDC1) Input Capacitor at VINDCDC1 (2) 10 CO(DCDC1) Output Capacitor at VDCDC1 (2) 10 IO(DCDC2) Output current at L2 Inductor at L2 F 2.2 (2) 10 CO(DCDC2) Output Capacitor at VDCDC2 (2) 10 22 IO(DCDC3) Output current at L3 (2) 2.2 3.3 Input Capacitor at VINDCDC3 (2) 10 (2) 10 F Output Capacitor at VDCDC3 CI(VCC) Input Capacitor at VCC Ci(VINLDO) Input Capacitor at VINLDO CO(VLDO1-2) Output Capacitor at VLDO1, VLDO2 IO(VLDO1-2) Output current at VLDO1, VLDO2 CO(VRTC) Output Capacitor at VRTC TA Operating ambient temperature -40 TJ Operating junction temperature -40 (2) (2) (3) H F 22 1 F 1 F 2.2 F 200 (3) mA F mA F 4.7 Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering (4) (2) (3) (4) F 900 CO(DCDC3) mA H 3.3 Input Capacitor at VINDCDC2 CI(DCDC3) F 1000 (2) UNIT H 22 CI(DCDC2) Inductor at L3 MAX 1 85 C 125 C 10 See applications section for more information. See applications section for more information. Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted accordingly. ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONTROL SIGNALS : SCLK, SDAT (input), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2 VIH High level input voltage Rpullup at SCLK and SDAT = 4.7 k, pulled to VRTC 1.3 VCC V VIL Low level input voltage Rpullup at SCLK and SDAT = 4.7 k, pulled to VRTC 0 0.4 V IH Input bias current 0.1 A V 0.01 CONTROL SIGNALS : HOT_RESET VIH High level input voltage 1.3 VCC VIL Low level input voltage 0 0.4 V IIB Input bias current 0.01 0.1 A tdeglitch Deglitch time at HOT_RESET 30 35 ms 25 CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output) VOH High level output voltage VOL Low level output voltage IIL = 5 mA 6 V 0.3 V ICONST internal charge / discharge current on pin TRESPWRON used for generating RESPWRON delay 1.7 2 2.3 A TRESPWR ON_LOWT H internal lower comparator threshold on pin TRESPWRON used for generating RESPWRON delay 0.225 0.25 0.275 V TRESPWR ON_UPTH internal upper comparator threshold on pin TRESPWRON used for generating RESPWRON delay 0.97 1 1.103 V 0 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 3 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted) PARAMETER ILK 4 TEST CONDITIONS MIN TYP MAX External capacitor 1 nF Resetpwron threshold VRTC falling -3% 2.4 3% Resetpwron threshold VRTC rising -3% 2.52 3% V leakage current output inactive high 0.1 A Submit Documentation Feedback 100 UNIT Duration of low pulse at RESPWRON ms V Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3 I(q) II I(q) Operating quiescent current, PFM Current into VCC; PWM Quiescent current All 3 DCDC converters enabled, zero load and no switching, LDOs enabled VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 85 100 All 3 DCDC converters enabled, zero load and no switching, LDOs off VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 78 90 DCDC1 and DCDC2 converters enabled, zero load and no switching, LDOs off VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 57 70 DCDC1 converter enabled, zero load and no switching, LDOs off VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 43 55 All 3 DCDC converters enabled and running in PWM, LDOs off VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 2 3 DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 1.5 2.5 DCDC1 converter enabled and running in PWM, LDOs off VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 0.85 2 VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 23 33 A VCC = 2.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 3.5 5 A 43 A All converters disabled, LDOs off VCC = 3.6 V, VBACKUP = 0 V; V(VSYSIN) = 0 V A Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 mA 5 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 20 33 A 3 A SUPPLY PINS: VBACKUP, VSYSIN, VRTC I(q) Operating quiescent current VBACKUP = 3 V, VSYSIN = 0 V; VCC = 2.6 V, current into VBACKUP I(SD) Operating quiescent current VBACKUP < V_VBACKUP, current into VBACKUP 2 VRTC LDO output voltage VSYSIN = VBACKUP = 0 V, IO = 0 mA 3 Output current for VRTC VSYSIN < 2.57 V and VBACKUP < 2.57 V 30 mA VRTC short-circuit current limit VRTC = GND; VSYSIN = VBACKUP = 0 V 100 mA Maximum output current at VRTC for RESPWRON = 1 VRTC > 2.6 V, VCC = 3 V; VSYSIN = VBACKUP = 0 V Output voltage accuracy for VRTC VSYSIN = VBACKUP = 0 V; IO = 0 mA -1% 1% Line regulation for VRTC VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA -1% 1% Load regulation VRTC IO = 1 mA to 30 mA; VSYSIN = VBACKUP = 0 V -3% 1% Regulation time for VRTC Load change from 10% to 90% Input leakage current at VSYSIN VSYSIN < V_VSYSIN IO VO Ilkg V 30 mA s 10 2 A rDS(on) of VSYSIN switch 12.5 rDS(on) of VBACKUP switch 12.5 3.75 V Input voltage range at VBACKUP (1) Input voltage range at VSYSIN 2.73 (1) 3.75 V VSYSIN threshold VSYSIN falling -3% 2.73 2.55 3% V VSYSIN threshold VSYSIN rising -3% 2.65 3% V VBACKUP threshold VBACKUP falling -3% 2.55 3% V VBACKUP threshold VBACKUP falling -3% 2.65 3% V SUPPLY PIN: VINLDO I(q) I(SD) (1) 6 Operating quiescent current Current per LDO into VINLDO 16 30 A Shutdown current Total current for both LDOs into VINLDO, VLDO = 0 V 0.1 1 A Based on the requirements for the Intel PXA270 processor. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC1 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC1 IO Maximum output current I(SD) Shutdown supply current in VINDCDC1 DCDC1_EN = GND 0.1 1 A rDS(on) P-channel MOSFET on-resistance VINDCDC1 = V(GS) = 3.6 V 125 261 m Ilkg P-channel leakage current VINDCDC1 = 6 V 2 A rDS(on) N-channel MOSFET on-resistance VINDCDC1 = V(GS) = 3.6 V 130 260 m Ilkg N-channel leakage current V(DS) = 6 V 7 10 A Forward current limit (P- and N-channel) 2.5 V < VI(MAIN) < 6 V 1.55 1.75 1.95 A 1.3 1.5 1.7 MHz fS 2.5 6 1200 Oscillator frequency 3V VINDCDC1 = 3.3 V to 6 V; 0 mA IO 1.2 A -2% 2% 3.3 V VINDCDC1 = 3.6 V to 6 V; 0 mA IO 1.2 A -2% 2% 3V VINDCDC1 = 3.3 V to 6 V; 0 mA IO 1.2 A -1% 1% 3.3 V VINDCDC1 = 3.6 V to 6 V; 0 mA IO 1.2 A -1% 1% Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1=0 VINDCDC1 = VDCDC1 +0.3 V (min 2.5 V) to 6 V; 0 mA IO 1.2 A -2% 2% Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1=1 VINDCDC1 = VDCDC1 +0.3 V (min 2.5 V) to 6 V; 0 mA IO 1.2 A -1% 1% Line Regulation VINDCDC1 = VDCDC1 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA Load Regulation Soft start ramp time Fixed output voltage FPWMDCDC1=0 Fixed output voltage FPWMDCDC1=1 0 %/V IO = 10 mA to 1200 mA 0.25 %/A VDCDC1 ramping from 5% to 95% of target value 750 s 1 M DCDC1 discharge = 1 300 Internal resistance from L1 to GND VDCDC1 discharge resistance V mA Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 7 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC2 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC2 IO Maximum output current 2.5 I(SD) Shutdown supply current in VINDCDC2 DCDC2_EN = GND 0.1 1 A rDS(on) P-channel MOSFET on-resistance VINDCDC2 = V(GS) = 3.6 V 140 300 m Ilkg P-channel leakage current VINDCDC2 = 6 V 2 A rDS(on) N-channel MOSFET on-resistance VINDCDC2 = V(GS) = 3.6 V 150 297 m Ilkg N-channel leakage current V(DS) = 6 V 7 10 A ILIMF Forward current limit (P- and N-channel) 2.5 V < VINDCDC2 < 6 V 1.4 1.55 1.7 A fS Oscillator frequency 1.3 1.5 1.7 MHz VINDCDC2 = 2.5 V to 6 V; 0 mA IO 1 A -2% 2% 2.5 V VINDCDC2 = 2.8 V to 6 V; 0 mA IO 1 A -2% 2% 1.8 V VINDCDC2 = 2.5 V to 6 V; 0 mA IO 1 A -2% 2% 2.5 V VINDCDC2 = 2.8 V to 6 V; 0 mA IO 1 A -1% 1% Adjustable output voltage with resistor divider at DEFDCDC2 FPWMDCDC2=0 VINDCDC2 = VDCDC2 +0.3 V (min 2.5 V) to 6 V; 0 mA IO 1 A -2% 2% Adjustable output voltage with resistor divider at DEFDCDC2; FPWMDCDC2=1 VINDCDC2 = VDCDC2 +0.3 V (min 2.5 V) to 6 V; 0 mA IO 1 A -1% 1% Line Regulation VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA Load Regulation Soft start ramp time Fixed output voltage FPWMDCDC2=1 0 %/V IO = 10 mA to 1 mA 0.25 %/A VDCDC2 ramping from 5% to 95% of target value 750 s 1 M DCDC2 discharge =1 300 Internal resistance from L2 to GND VDCDC2 discharge resistance V mA 1.8 V Fixed output voltage FPWMDCDC2=0 8 6 1000 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC3 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC3 2.5 IO Maximum output current 900 I(SD) Shutdown supply current in VINDCDC3 DCDC3_EN = GND 0.1 1 A rDS(on) P-channel MOSFET on-resistance VINDCDC3 = V(GS) = 3.6 V 310 698 m Ilkg P-channel leakage current VINDCDC3 = 6 V 0.1 2 A rDS(on) N-channel MOSFET on-resistance VINDCDC3 = V(GS) = 3.6 V 220 503 m Ilkg N-channel leakage current V(DS) = 6 V 7 10 A Forward current limit (P- and N-channel) 2.5 V < VINDCDC3 < 6 V 1.15 1.34 1.52 A 1.3 1.5 1.7 MHz fS Oscillator frequency Fixed output voltage FPWMDCDC3=0 6 VINDCDC3 = 2.5 V to 6 V; 0 mA IO 800 mA -2% 2% VINDCDC3 = 2.5 V to 6 V; 0 mA IO 800 mA -1% 1% Adjustable output voltage with resistor divider at DEFDCDC3 FPWMDCDC3=0 VINDCDC3 = VDCDC3 +0.5 V (min 2.5 V) to 6 V; 0 mA IO 800 mA -2% 2% Adjustable output voltage with resistor divider at DEFDCDC3; FPWMDCDC3=1 VINDCDC3 = VDCDC3 +0.5 V (min 2.5 V) to 6 V; 0 mA IO 800 mA -1% 1% Line Regulation VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA Load Regulation Soft start ramp time Fixed output voltage FPWMDCDC3=1 All VDCDC3 0 %/V IO = 10 mA to 400 mA 0.25 %/A VDCDC3 ramping from 5% to 95% of target value 750 s 1 M DCDC3 discharge =1 300 Internal resistance from L3 to GND VDCDC3 discharge resistance V mA Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 9 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VLDO1 and VLDO2 LOW DROPOUT REGULATORS VI Input voltage range for LDO1, 2 1.5 6.5 V VO LDO1 output voltage range 1 3.3 V VO LDO2 output voltage range 1 3.3 V IO Maximum output current for LDO1, LDO2 I(SC) LDO1 and LDO2 short circuit current limit VI = 1.8 V, VO = 1.3 V 200 VI = 1.5 V, VO = 1.3 V V(LDO1) = GND, V(LDO2) = GND 400 IO = 50 mA, VINLDO = 1.8 V Minimum voltage drop at LDO1, LDO2 mA 120 mA 120 IO = 50 mA, VINLDO = 1.5 V 65 IO = 200 mA, VINLDO = 1.8 V 150 mV 300 Output voltage accuracy for LDO1, LDO2 IO = 10 mA -2% 1% Line regulation for LDO1, LDO2 VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5 V, IO = 10 mA -1% 1% Load regulation for LDO1, LDO2 IO = 0 mA to 50 mA -1% Regulation time for LDO1, LDO2 Load change from 10% to 90% 1% s 10 ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3 VIH High level input voltage 1.3 VCC VIL Low level input voltage 0 0.1 V 0.05 A Input bias current 0.001 V THERMAL SHUTDOWN T(SD) Thermal shutdown Increasing junction temperature 160 C Thermal shutdown hysteresis Decreasing junction temperature 20 C INTERNAL UNDERVOLTAGE LOCK OUT UVLO Internal UVLO V(UVLO_HYST) Internal UVLO comparator hysteresis -2% VCC falling 2.35 2% 120 V mV VOLTAGE DETECTOR COMPARATORS Comparator threshold (PWRFAIL_SNS, LOWBAT_SNS) Falling threshold Hysteresis Propagation delay -1% 1 1% V 40 50 60 mV 10 s 25 mV overdrive POWER GOOD V(PGOODF) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing -12% -10% -8% V(PGOODR) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing -7% -5% -3% 10 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com PWRFAIL DEFDCDC2 PGND2 VDCDC2 L2 VINDCDC2 PWRFAIL_SNS VCC LOWBAT_SNS AGND1 PIN ASSIGNMENT (TOP VIEW) 40 39 38 37 36 35 34 33 32 31 DEFDCDC3 1 30 SCLK VDCDC3 2 29 SDAT 3 28 INT 4 27 RESPWRON 5 26 TRESPWRON VINDCDC1 6 25 DCDC1_EN L1 7 24 DCDC2_EN PGND1 8 23 DCDC3_EN 9 22 LDO_EN 10 21 LOWBAT PGND3 L3 VINDCDC3 VDCDC1 DEFDCDC1 VLDO1 VINLDO VLDO2 VRTC AGND2 VBACKUP VSYSIN DEFLDO1 DEFLDO2 HOT_RESET 11 12 13 14 15 16 17 18 19 20 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION SWITCHING REGULATOR SECTION AGND1 40 Analog ground connection. All analog ground pins are connected internally on the chip. AGND2 17 Analog ground connection. All analog ground pins are connected internally on the chip. PowerPADTM - Connect the power pad to analog ground. VINDCDC1 6 L1 7 VDCDC1 9 PGND1 8 VINDCDC2 36 L2 35 VDCDC2 33 PGND2 34 VINDCDC3 5 L3 4 VDCDC3 2 PGND3 3 I Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC. Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. I VDCDC1 feedback voltage sense input, connect directly to VDCDC1 Power ground for VDCDC1 converter I Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC. Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here. I VDCDC2 feedback voltage sense input, connect directly to VDCDC2 Power ground for VDCDC2 converter I Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC. Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here. I VDCDC3 feedback voltage sense input, connect directly to VDCDC3 Power ground for VDCDC3 converter Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 11 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION VCC 37 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. Also supplies serial interface block DEFDCDC1 10 I Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V This pin can also be connected to a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V. DEFDCDC2 32 I Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V This pin can also be connected to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V. DEFDCDC3 1 I Input signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V This pin can also be connected to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V. DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. LDO REGULATOR SECTION VINLDO 19 I I Input voltage for LDO1 and LDO2 VLDO1 20 O Output voltage of LDO1 VLDO2 18 O Output voltage of LDO2 LDO_EN 22 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs VBACKUP 15 I Connect the backup battery to this input pin. VRTC 16 O Output voltage of the LDO/switch for the real time clock VSYSIN 14 I Input of system voltage for VRTC switch DEFLD01 12 I Digital input, used to set default output voltage of LDO1 and LDO2 DEFLD02 13 I Digital input, used to set default output voltage of LDO1 and LDO2 CONTROL AND I2C SECTION HOT_RESET 11 I Push button input used to reboot or wake-up processor via RESPWRON output pin TRESPWRON 26 I Connect the timing capacitor to this pin to set the reset delay time: 1 nF 100 ms RESPWRON 27 O Open drain System reset output PWRFAIL 31 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition. LOW_BAT 21 O Open drain output of LOW_BAT comparator INT 28 O Open drain output SCLK 30 I Serial interface clock line SDAT 29 I/O PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output. LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output. 12 Serial interface data/address Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM VSYSIN THERMAL SHUTDOWN VCC VBACKUP BBAT SWITCH VRTC VINDCDC1 DCDC1 L1 VDCDC1 STEP-DOWN CONVER TER SCLK SDAT Serial Interface VINDCDC2 DCDC1_EN DCDC2_EN DCDC2 DCDC3_EN LDO_EN HOT_RESET DEFDCDC1 PGND1 STEP-DOWN CONVERTER CONTROL L2 VDCDC2 DEFDCDC2 PGND2 RESPWRON VCC INT AGND1 VINDCDC3 LOWBAT_SNS PWRFAIL_SNS LOW_BATT PWRFAIL TRESPWRON L3 DCDC3 UVLO VREF OSC VDCDC3 STEP-DOWN CONVERTER DEFDCDC3 PGND3 DEFLDO1 VLDO1 VLDO1 200-mA LDO DEFLDO2 AGND2 VINLDO VLDO2 VLDO2 200-mA LDO Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 13 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS Graphs were taken using the EVM with the following inductor/output capacitor combinations: CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE VDCDC1 VLCF4020-2R2 C2012X5R0J106M 2 x 10 F VDCDC2 VLCF4020-2R2 C2012X5R0J106M 2 x 10 F VDCDC3 VLF4012AT-2R2M1R5 C2012X5R0J106M 2 x 10 F Table 1. Table of Graphs FIGURE Efficiency vs Output current 1, 2, 3, 4, 5, 6, 7 Line transient response 8, 9, 10 Load transient response 11, 12, 13 VDCDC2 PFM operation 14 VDCDC2 low ripple PFM operation 15 VDCDC2 PWM operation 16 Startup VDCDC1, VDCDC2 and VDCDC3 17 Startup LDO1 and LDO2 18 Line transient response 19, 20, 21 Load transient response 22, 23, 24 DCDC1: EFFICIENCY vs OUTPUT CURRENT DCDC1: EFFICIENCY vs OUTPUT CURRENT VI = 3.8 V VI = 4.2 V VI = 4.2 V VI = 3.8 V Efficiency - % Efficiency - % VI = 5 V VI = 5 V o o TA = 25 C VO = 3.3 V PFM / PWM Mode 0.01 14 0.1 1 10 100 1k TA = 25 C VO = 3.3 V PWM Mode 10 k 0.01 0.1 1 10 100 IO - Output Current - mA IO - Output Current - mA Figure 1. Figure 2. Submit Documentation Feedback 1k 10 k Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com DCDC2: EFFICIENCY vs OUTPUT CURRENT DCDC2: EFFICIENCY vs OUTPUT CURRENT VI = 2.5 V VI = 3.8 V Efficiency - % Efficiency - % VI = 3.8 V VI = 4.2 V VI = 4.2 V VI = 2.5 V VI = 5 V VI = 5 V o o TA = 25 C VO = 1.8 V PWM Mode TA = 25 C VO = 1.8 V PWM / PFM Mode 0.01 0.1 10 1 100 1k 10 k 0.01 0.1 10 1 IO - Output Current - mA 100 1k 10 k IO - Output Current - mA Figure 3. Figure 4. DCDC3: EFFICIENCY vs OUTPUT CURRENT DCDC3: EFFICIENCY vs OUTPUT CURRENT VI = 3 V o TA = 25 C VO = 1.55 V PWM Mode VI = 2.5 V VI = 3.8 V Efficiency - % Efficiency - % VI = 3.8 V VI = 4.2 V VI = 3 V VI = 2.5 V VI = 5 V VI = 4.2 V o TA = 25 C VO = 1.55 V PWM / PFM Mode 0.01 0.1 1 10 100 VI = 5 V 1k 0.01 IO - Output Current - mA 0.1 1 10 100 1k IO - Output Current - mA Figure 5. Figure 6. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 15 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com DCDC3: EFFICIENCY vs OUTPUT CURRENT VDCDC1 LINE TRANSIENT RESPONSE Ch1 = VI Ch2 = VO Efficiency - % VI = 3 V C1 High 4.74 V VI = 3.8 V VI = 2.5 V C1 Low 3.08 V VI = 4.2 V C2 PK-PK 85 mV VI = 5 V C2 Mean 3.2957 V IO = 100 mA VI = 3.6 V to 4.7 V VO = 3 V PWM Mode o TA = 25 C VO = 1.3 V Low Ripple PFM Mode 0.01 0.1 10 1 IO - Output Current - mA Figure 7. Figure 8. VDCDC2 LINE TRANSIENT RESPONSE VDCDC3 LINE TRANSIENT RESPONSE Ch1 = VI Ch2 = VO C1 High 4.04 V Ch1 = VI Ch2 = VO C1 High 4.05 V C1 Low 2.95 V C1 Low 2.94 V C2 PK-PK 46.0 mV C2 PK-PK 49.9 mV C2 Mean 1.59798 V C2 Mean 1.79419 V IO = 100 mA VI = 3 V to 4 V VO = 1.6 V PWM Mode IO = 100 mA VI = 3 V to 4 V VO = 1.8 V PWM Mode Figure 9. 16 Figure 10. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com VDCDC1 LOAD TRANSIENT RESPONSE VDCDC2 LOAD TRANSIENT RESPONSE Ch2 = VO Ch4 = IO Ch2 = VO Ch4 = IO C4 High 1.09 A C4 High 830 mA C4 Low 120 mA C4 Low 90 mA C2 PK-PK 188 mV C2 PK-PK 80 mV C2 Mean 3.3051 V C2 Mean 1.7946 V IO = 100 mA to 800 mA VI = 3.8 V IO = 120 mA to 1080 mA VI = 3.8 V VO = 1.8 V PWM Mode VO = 3.3 V PWM Mode Figure 11. Figure 12. VDCDC3 LOAD TRANSIENT RESPONSE VDCDC2 OUTPUT VOLTAGE RIPPLE Ch2 = VO Ch4 = IO C4 High 730 mA VI = 3.8 V VO = 1.8 V IO = 1 mA TA = 25oC PFM Mode C4 Low 80 mA C2 PK-PK 17.0 mV C2 PK-PK 80 mV C2 Mean 1.80522 V C2 Mean 1.5931 V IO = 80 mA to 720 mA VI = 3.8 V VO = 1.6 V o TA = 25 C PWM Mode Figure 13. Figure 14. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 17 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com VDCDC2 OUTPUT VOLTAGE RIPPLE VO = 1.8 V VI = 3.8 V IO = 1 mA o TA = 25 C Low Ripple PFM Mode VDCDC2 OUTPUT VOLTAGE RIPPLE VI = 3.8 V VO = 1.8 V IO = 1 mA TA = 25oC PWM Mode C2 PK-PK 7.7 mV C2 Mean 1.79955 mV Figure 15. Figure 16. STARTUP VDCDC1, VDCDC2, AND VDCDC3 STARTUP LDO1 AND LDO2 ENABLE ENABLE VDCDC1 LDO1 VDCDC2 LDO2 VDCDC3 Figure 17. 18 Figure 18. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com LDO1 LINE TRANSIENT RESPONSE Ch1 = VI Ch2 = VO IO = 25 mA VO = 1.1 V o TA = 25 C LDO2 LINE TRANSIENT RESPONSE C1 High 3.83 V Ch1 = VI Ch2 = VO IO = 25 mA VO = 3.3 V TA = 25oC C1 Low 3.29 V C1 Low 3.99 V C2 PK-PK 6.2 mV C2 PK-PK 6.1 mV C2 Mean 1.09702 V Ch1 = VI Ch2 = VO C2 Mean 3.29828 V Figure 19. Figure 20. VRTC LINE TRANSIENT RESPONSE LDO1 LOAD TRANSIENT RESPONSE IO = 10 mA VO = 3 V o TA = 25 C C1 High 4.51 V C1 High 3.82 V C4 High 48.9 mA C1 Low 3.28 V C4 Low 2.1 mA C2 PK-PK 22.8 mV C2 PK-PK 42.5 mV C2 Mean 2.98454 V C2 Mean 1.09664 V Ch2 = VO Ch4 = IO Figure 21. VI = 3.3 V VO = 1.1 V o TA = 25 C Figure 22. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 19 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com LDO2 LOAD TRANSIENT RESPONSE VRTC LOAD TRANSIENT RESPONSE C4 High 47.8 mA C4 High 21.4 mA C4 Low -2.9 mA C4 Low -1.4 mA C2 PK-PK 40.4 mV C2 PK-PK 76 mV C2 Mean 3.29821 V VI = 4 V VO = 3.3 V o TA = 25 C Ch2 = VO Ch4 = IO C2 Mean 2.9762 V Ch2 = VO Ch4 = IO Figure 23. 20 VI = 3.8 V VO = 3 V o TA = 25 C Figure 24. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 www.ti.com SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 DETAILED DESCRIPTION VRTC OUTPUT AND OPERATION WITH OR WITHOUT BACKUP BATTERY The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail. This is the VCC_BATT rail of the Intel(R) PXA270 Bulverde processor for example. In applications using a backup battery, the backup voltage can be either directly connected to the TPS65021 VBACKUP pin if a Li-Ion cell is used, or via a boost converter (e.g. TPS61070) if a single NiMH battery is used. The voltage applied to the VBACKUP pin is fed through a PMOS switch to the VRTC pin. The TPS65021 asserts the RESPWRON signal if VRTC drops below 2.4 V. This, together with 375 mV at 30 mA drop out for the PMOS switch means that the voltage applied at VBACKUP must be greater than 2.775 V for normal system operation. When the voltage at the VSYSIN pin exceeds 2.65 V, the path from VBACKUP to VRTC is cut, and VRTC is supplied by a similar PMOS switch from the voltage source connected to the VSYSIN input. Typically this is the VDCDC1 converter but can be any voltage source within the appropriate range. In systems where no backup battery is used, the VBACKUP pin is connected to GND. In this case, a low power LDO is enabled, supplied from VCC and capable of delivering 30 mA to the 3 V output. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V. VRTC is then supplied from the external source connected to this pin as previously described. Inside TPS65021 there is a switch (Vmax switch) which selects the higher voltage between VCC and VBACKUP. This is used as the supply voltage for some basic functions. The functions powered from the output of the Vmax switch are: * INT output * RESPWRON output * HOT_RESET input * LOW_BATT output * PWRFAIL output * Enable pins for dc-dc converters, LDO1 and LDO2 * Undervoltage lockout comparator (UVLO) * Reference system with low frequency timing oscillators * LOW_BATT and PWRFAIL comparators The main 1.5-MHz oscillator, and the I2CTM interface are only powered from VCC. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 21 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 VSYSIN Vref V_VSYSIN priority #1 www.ti.com VCC VBACKUP Vref V_VBACKUP priority #2 V_VSYSIN V_VBACKUP EN VRTC LDO priority #3 VRTC Vref A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V 3% B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V 3% RESPWRON Figure 25. STEP-DOWN CONVERTERS, VDCDC1, VDCDC2, and VDCDC3 The TPS65021 incorporates three synchronous step-down converters operating typically at 1.5 MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter the power save mode (PSM), and operate with pulse frequency modulation (PFM). The VDCDC1 converter is capable of delivering 1.2 A output current, the VDCDC2 converter is capable of delivering 1 A and the VDCDC3 converter is capable of delivering up to 900 mA. The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The VDCDC1 converter defaults to 3 V or 3.3 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1 is tied to ground, the default is 3 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See the application information section for more details. The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin. If DEFDCDC2 is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 2.5 V. When the DEFDCDC2 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V. The VDCDC3 converter defaults to 1.3 V or 1.55 V depending on the DEFDCDC3 configuration pin. If DEFDCDC3 is tied to ground the default is 1.3 V. If it is tied to VCC, the default is 1.55 V. When the DEFDCDC3 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V. The core voltage can be reprogrammed via the serial interface in the range of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst any programmed voltage change is underway, whether the voltage is being increased or decreased. The DEFCORE and DEFSLEW registers are used to program the output voltage and slew rate during voltage transitions. The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs of which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged via on-chip 300- resistors when the dc-dc converters are disabled. 22 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com During PWM operation, the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch. The three dc-dc converters operate synchronized to each other with the VDCDC1 converter as the master. A 180 phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90 shift to the VDCDC3 switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the VDCDC2 converter from 3.7 V to 2.5 V, and the VDCDC3 converter from 3.7 V to 1.5 V. The phase of the three converters can be changed using the CON_CTRL register. POWER SAVE MODE OPERATION As the load current decreases, the converters enter the power save mode operation. During PSM, the converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 1.5 MHz, nominal for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency. In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM is calculated as follows: VINDCDC1 IPFMDCDC1 enter = 24 W IPFMDCDC2 enter = VINDCDC2 26 W IPFMDCDC3 enter = VINDCDC3 39 W (1) During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter effectively delivers a constant current defined as follows. VINDCDC1 IPFMDCDC1 leave = 18 W IPFMDCDC2 leave = VINDCDC2 20 W IPFMDCDC3 leave = VINDCDC3 29 W (2) If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode if either of the following conditions are met: 1. the output voltage drops 2% below the nominal VO due to increasing load current 2. the PFM burst time exceeds 16 x 1/fs (10.67 s typical). Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 23 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com These control methods reduce the quiescent current to typically 14 A per converter, and the switching activity to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM mode. LOW RIPPLE MODE Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is reduced, depending on the actual load current. The lower the actual output current on the converter, the lower the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is used to keep the switching frequency above the audible range in PFM mode down to a low output current. SOFT START Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft start is realized by using a very low current to initially charge the internal compensation capacitor. The soft start time is typically 750 s if the output voltage ramps from 5% to 95% of the final target value. If the output is already precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a short delay of typically 170 s between the converter being enabled and switching activity actually starting. This is to allow the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent discharging of the output while the internal soft start ramp catches up with the output voltage. 100% DUTY CYCLE LOW DROPOUT OPERATION The TPS65021 converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load current and output voltage. It is calculated as: Vin min + Vout min ) Iout max rDS(on) max ) RL (3) with: Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions) rDS(on)max = maximum P-channel switch rDS(on) RL = DC resistance of the inductor Voutmin = nominal output voltage minus 2% tolerance limit ACTIVE DISCHARGE WHEN DISABLED When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled via the CON_CTRL2 register in the serial interface. When this feature is enabled, the VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300 (typical) load which is active as long as the converters are disabled. POWER GOOD MONITORING All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5% hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are disabled and the relevant PGOODZ register bits indicate that power is good. 24 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com LOW DROPOUT VOLTAGE REGULATORS The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the LDO_EN pin, both LDOs can be disabled or programmed via the serial interface using the REG_CTRL and LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect external regulators in parallel in systems with a backup battery. The TPS65021 step-down and LDO voltage regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the junction temperature rises above 160C. POWER GOOD MONITORING Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the LDOs are disabled and the relevant PGOODZ register bits indicate that power is good. UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit for the five regulators on the TPS65021 prevents the device from malfunctioning at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note that when any of the dc-dc converters are running, there is an input current at the VCC pin, which is up to 3 mA when all three converters are running in PWM mode. This current needs to be taken into consideration if an external RC filter is used at the VCC pin to remove switching noise from the TPS65021 internal analog circuitry supply. POWER-UP SEQUENCING The TPS65021 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The relevant control pins are described in Table 2. Table 2. Control Pins and Status Outputs for DC-DC Converters PIN NAME INPUT OUTPUT FUNCTION DEFDCDC3 I Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.3 V, DEFDCDC3 = VCC defaults VDCDC3 to 1.55 V. DEFDCDC2 I Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5 V. DEFDCDC1 I Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 3 V, DEFDCDC1 = VCC defaults VDCDC1 to 3.3 V. DCDC3_EN I Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter DCDC2_EN I Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter DCDC1_EN I Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter HOT_RESET I The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any TPS65021 settings except the output voltage of VDCDC3. Activating HOT_RESET sets the voltage of VDCDC3 to its default value defined with the DEFDCDC3 pin. HOT_RESET is internally de-bounced by the TPS65021. RESPWRON O RESPWRON is held low when power is initially applied to the TPS65021. The VRTC voltage is monitored: RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin. TRESPWRON I Connect a capacitor here to define the RESET time at the RESPWRON pin. 1 nF typically gives 100 ms. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 25 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com SYSTEM RESET + CONTROL SIGNALS The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms. The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV) hysteresis. The DCDC3 converter is reset to its default output voltage defined by the DEFDCDC3 input, when HOT_RESET is asserted. Other I2C registers are not affected. Generally, the DCDC3 converter is set to its default voltage with one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout (UVLO) condition, RESPWRON active, both DCDC3-converter AND DCDC1-converter disabled. In addition, the voltage of VDCDC3 changes to 1xxx0, if the VDCDC1 converter is disabled. Where xxx is the state before VDCDC1 was disabled. DEFLDO1 and DEFLDO2 These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of both LDOs can be changed during operation with the I2C interface as described in the interface description. Table 3. DEFLDO2 DEFLDO1 VLDO1 VLDO2 0 0 1.1 V 1.3 V 0 1 1.5 V 1.3 V 1 0 2.6 V 2.8 V 1 1 3.15 V 3.3 V Interrupt Management and the INT Pin The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and LDOs. The INT pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register is read via the serial interface, any active bits are then blocked from the INT output pin. Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO interrupts since this provides the POWER_OK function. 26 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com TIMING DIAGRAMS HOT_RESET tDEGLITCH RESPWRON VO DCDC3 tNRESPWRON default voltage any voltage set 2 with I C interface Figure 26. HOT_RESET Timing VCC 1.9 V 0.8 V 2.35 V 1.9 V 1.2 V 2.47 V UVLO* 2.52 V VRTC 2.4 V 3V RESPWRON tNRESPWRON DCDCx_EN Ramp Within 800 ms VODCDCx 1.8 V slope depending on load LDO_EN VOLDOx 1.5 V *... Internal Signal VSYSIN = VBACKUP = GND; VINLDO = VCC Figure 27. Power-Up and Power-Down Timing Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 27 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com VCC RESPWRON tNRESPWRON DCDC1_EN DCDC2_EN 3.3 V or 3 V VODCDC1 Ramp Within 800 ms VODCDC2 Ramp Within 800 ms 2.5 V or 1.8 V Ramp Within 800 ms DEFCORE register Default Value Set Higher Output Voltage for DCDC3 GO bit in CON_CTRL2 Cleared Automatically Automatically Set to Default Value DCDC3_EN VODCDC3 1.3 V or 1.55 V Ramp Within 800 ms 1.3 V or 1.55 V Programmed Slope Depending On Load Slew Rate Ramp Within 800 ms Figure 28. DVS Timing SERIAL INTERFACE The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS65021 has a 7-bit address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from the register addresses not listed in this section results in FFh being read out. For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable 28 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65021 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65021 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65021 device must leave the data line high to enable the master to generate the stop condition DATA CLK Data Line Stable; Data Valid Change of Data Allowed Figure 29. Bit Transfer on the Serial Interface DATA CLK S P START Condition STOP Condition Figure 30. START and STOP Conditions SCLK SDAT A6 A5 A4 A0 R/W ACK 0 Start Slave Address R7 R6 R5 R0 0 ACK D7 D6 D5 D0 ACK 0 0 Register Address Data Stop Note: SLAVE = TPS65020 Figure 31. Serial i/f WRITE to TPS65021 Device Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 29 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com SCLK SDAT A6 Start A0 R/W ACK 0 0 R0 R7 A6 ACK A0 R/W ACK 1 0 0 Register Address Slave Address D0 D7 ACK Slave Drives the Data Slave Address Stop Master Drives ACK and Stop Repeated Start Note: SLAVE = TPS65020 Figure 32. Serial i/f READ from TPS65021: Protocol A SCLK SDA A6 A0 R/W ACK 0 Start R0 R7 0 A6 ACK 0 R/W 1 Stop Start Register Address Slave Address A0 ACK D7 D0 ACK 0 Slave Drives the Data Slave Address Stop Master Drives ACK and Stop Note: SLAVE = TPS65020 Figure 33. Serial i/f READ from TPS65021: Protocol B DATA t(BUF) th(STA) t(LOW) tf tr CLK th(STA) t(HIGH) tsu(STA) th(DATA) STO tsu(STO) tsu(DATA) STA STA STO Figure 34. Serial i/f Timing Diagram 30 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com MIN MAX UNIT 400 kHz fMAX Clock frequency twH(HIGH) Clock high time 600 twL(LOW) Clock low time 1300 tR DATA and CLK rise time 300 ns tF DATA and CLK fall time 300 ns th(STA) Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns th(DATA) Setup time for repeated START condition 600 ns th(DATA) Data input hold time 300 ns tsu(DATA) Data input setup time 300 ns tsu(STO) STOP condition setup time 600 ns t(BUF) Bus free time 1300 ns ns ns VERSION. Register Address: 00h (read only) VERSION B7 B6 B5 B4 B3 B2 B1 B0 Bit name and function 0 0 1 0 0 0 0 1 Read/Write R R R R R R R R Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 31 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com PGOODZ. Register Address: 01h (read only) PGOODZ B7 Bit name and function PWRFAILZ Set by signal PWRFAIL Default value loaded by: PWRFAILZ Read/Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 32 B6 B5 B4 B3 B2 B1 LOWBATTZ PGOODZ VDCDC1 PGOODZ VDCDC2 PGOODZ VDCDC3 PGOODZ LDO2 PGOODZ LDO1 LOWBATT PGOODZ VDCDC1 PGOODZ VDCDC2 PGOODZ VDCDC3 PGOODZ LDO2 PGOODZ LDO1 LOWBATTZ PGOOD VDCDC1 PGOOD VDCDC2 PGOOD VDCDC3 PGOOD LDO2 PGOOD LDO1 R R R R R R R B0 R PWRFAILZ: 0= indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold. 1= indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold. LOWBATTZ: 0= indicates that the LOWBATT_SNS input voltage is above the 1-V threshold. 1= indicates that the LOWBATT_SNS input voltage is below the 1-V threshold. PGOODZ VDCDC1: 0= indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if the VDCDC1 converter is disabled. 1= indicates that the VDCDC1 converter output voltage is below its target regulation voltage PGOODZ VDCDC2: 0= indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if the VDCDC2 converter is disabled. 1= indicates that the VDCDC2 converter output voltage is below its target regulation voltage PGOODZ VDCDC3: . 0= indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if the VDCDC3 converter is disabled and during a DVM controlled output voltage transition 1= indicates that the VDCDC3 converter output voltage is below its target regulation voltage PGOODZ LDO2: 0= indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is disabled. 1= indicates that LDO2 output voltage is below its target regulation voltage PGOODZ LDO1 0= indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is disabled. 1= indicates that the LDO1 output voltage is below its target regulation voltage Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com MASK. Register Address: 02h (read/write) MASK Bit name and function Default Default value loaded by: Read/Write Default Value: C0h B7 B6 B5 B4 B3 B2 B1 MASK PWRFAILZ MASK LOWBATTZ MASK VDCDC1 MASK VDCDC2 MASK VDCDC3 MASK LDO2 MASK LDO1 1 1 0 0 0 0 0 UVLO UVLO UVLO UVLO UVLO UVLO UVLO R/W R/W R/W R/W R/W R/W R/W B0 0 The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1 masks PGOODZ<n>. REG_CTRL. Register Address: 03h (read/write) Default Value: FFh The REG_CTRL register is used to disable or enable the power supplies via the serial interface. The contents of the register are logically AND'ed with the enable pins to determine the state of the supplies. A UVLO condition resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The REG_CTRL bits are automatically reset to default when the corresponding enable pin is low. REG_CTRL B7 B6 Bit name and function Default 1 1 Set by signal Default value loaded by: Read/Write Bit 5 B5 B4 B3 B2 B1 VDCDC1 ENABLE VDCDC2 ENABLE VDCDC3 ENABLE LDO2 ENABLE LDO1 ENABLE 1 1 1 1 1 LDO_ENZ LDO_ENZ DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ UVLO UVLO UVLO UVLO UVLO R/W R/W R/W R/W R/W B0 1 VDCDC1 ENABLE DCDC1 Enable. This bit is logically AND'ed with the state of the DCDC1_EN pin to turn on the DCDC1 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when DCDC1_EN returns high. Bit 4 VDCDC2 ENABLE DCDC2 Enable. This bit is logically AND'ed with the state of the DCDC2_EN pin to turn on the DCDC2 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when DCDC2_EN returns high. Bit 3 VDCDC3 ENABLE DCDC3 Enable. This bit is logically AND'ed with the state of the DCDC3_EN pin to turn on the DCDC3 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when DCDC3_EN returns high. Bit 2 LDO2 ENABLE LDO2 Enable. This bit is logically AND'ed with the state of the LDO2_EN pin to turn on LDO2. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high. Bit 1 LDO1 ENABLE LDO1 Enable. This bit is logically AND'ed with the state of the LDO1_EN pin to turn on LDO1. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 33 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com CON_CTRL. Register Address: 04h (read/write) Default Value: B1h CON_CTRL B7 B6 B5 B4 B3 B2 B1 B0 Bit name and function DCDC2 PHASE1 DCDC2 PHASE0 DCDC3 PHASE1 DCDC3 PHASE0 LOW RIPPLE FPWM DCDC2 FPWM DCDC1 FPWM DCDC3 1 0 1 1 0 0 0 1 UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO R/W R/W R/W R/W R/W R/W R/W R/W Default Default value loaded by: Read/Write The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is taken as the reference and consequently has a fixed zero phase shift. DCDC2 CONVERTER DELAYED BY CON_CTRL<5:4> 00 zero 00 zero 01 1/4 cycle 01 1/4 cycle 10 1/2 cycle 10 1/2 cycle 11 3/4 cycle 11 3/4 cycle CON_CTRL<7:6> Bit 3 Bit 2 Bit 1 Bit 0 34 DCDC3 CONVERTER DELAYED BY LOW RIPPLE: 0= PFM mode operation optimized for high efficiency for all converters 1= PFM mode operation optimized for low output voltage ripple for all converters FPWM DCDC2: 0= DCDC2 converter operates in PWM / PFM mode 1= DCDC2 converter is forced into fixed frequency PWM mode FPWM DCDC1: 0= DCDC1 converter operates in PWM / PFM mode 1= DCDC1 converter is forced into fixed frequency PWM mode FPWM DCDC3: 0= DCDC3 converter operates in PWM / PFM mode 1= DCDC3 converter is forced into fixed frequency PWM mode Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com CON_CTRL2. Register Address: 05h (read/write) CON_CTRL2 Bit name and function Default Default value loaded by: Read/Write B7 B6 GO Core adj allowed 0 1 UVLO + DONE UVLO R/W R/W B5 0 Default Value: 40h B4 0 B3 B2 B1 B0 DCDC2 discharge DCDC1 discharge DCDC3 discharge 0 0 0 UVLO UVLO UVLO R/W R/W R/W 0 The CON_CTRL2 register can be used to take control the inductive converters. Bit 7 Bit 6 Bit 2- 0 GO: 0= no change in the output voltage for the DCDC3 converter 1= the output voltage of the DCDC3 converter is changed to the value defined in DEFCORE with the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is complete. The transition is considered complete in this case when the desired output voltage code has been reached, not when the VDCDC3 output voltage is actually in regulation at the desired voltage. CORE ADJ Allowed: 0= the output voltage is set with the I2C register 1= DEFDCDC3 is either connected to GND or VCC or an external voltage divider. When connected to GND or VCC, VDCDC3 defaults to 1.3 V or 1.55 V respectively at start-up 0= the output capacitor of the associated converter is not actively discharged when the converter is disabled 1= the output capacitor of the associated converter is actively discharged when the converter is disabled. This decreases the fall time of the output voltage at light load Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 35 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com DEFCORE. Register Address: 06h (read/write DEFCORE B7 B6 Default Value: 14h/1Eh B5 Bit name and function Default 0 0 B4 B3 B2 B1 B0 CORE4 CORE3 CORE2 CORE1 CORE0 1 DEFDCDC3 1 DEFDCDC3 0 RESET(1) RESET(1) RESET(1) RESET(1) RESET(1) R/W R/W R/W R/W R/W 0 Default value loaded by: Read/Write RESET(1): DEFCORE is reset to its default value by one of these events: * undervoltage lockout (UVLO) * DCDC1 AND DCDC3 disabled * HOT_RESET pulled low * RESPWRON active * VRTC below threshold CORE4 CORE3 CORE2 CORE1 CORE0 VDCDC3 CORE4 CORE3 CORE2 CORE1 CORE0 0 0 0 0 0 0.8 V 1 0 0 0 0 1.2 V 0 0 0 0 1 0.825 V 1 0 0 0 1 1.225 V 0 0 0 1 0 0.85 V 1 0 0 1 0 1.25 V 0 0 0 1 1 0.875 V 1 0 0 1 1 1.275 V 0 0 1 0 0 0.9 V 1 0 1 0 0 1.3 V 0 0 1 0 1 0.925 V 1 0 1 0 1 1.325 V 0 0 1 1 0 0.95 V 1 0 1 1 0 1.35 V 0 0 1 1 1 0.975 V 1 0 1 1 1 1.375 V 0 1 0 0 0 1V 1 1 0 0 0 1.4 V 0 1 0 0 1 1.025 V 1 1 0 0 1 1.425 V 0 1 0 1 0 1.05 V 1 1 0 1 0 1.45 V 0 1 0 1 1 1.075 V 1 1 0 1 1 1.475 V 0 1 1 0 0 1.1 V 1 1 1 0 0 1.5 V 0 1 1 0 1 1.125 V 1 1 1 0 1 1.525 V 0 1 1 1 0 1.15 V 1 1 1 1 0 1.55 V 0 1 1 1 1 1.175 V 1 1 1 1 1 1.6 V DEFSLEW. Register Address: 07h (read/write) DEFSLEW B7 B6 Default Value: 06h B5 B4 B3 Bit name and function B2 B1 B0 SLEW2 SLEW1 SLEW0 1 1 0 UVLO UVLO UVLO R/W R/W R/W Default Default value loaded by: Read/Write 36 VDCDC3 SLEW2 SLEW1 SLEW0 VDCDC3 SLEW RATE 0 0 0 0.15 mV/s 0 0 1 0.3 mV/s 0 1 0 0.6 mV/s 0 1 1 1.2 mV/s 1 0 0 2.4 mV/s 1 0 1 4.8 mV/s 1 1 0 9.6 mV/s Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com SLEW2 SLEW1 SLEW0 VDCDC3 SLEW RATE 1 1 1 Immediate Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 37 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com LDO_CTRL. Register Address: 08h (read/write) LDO_CTRL B7 B6 B5 B4 LDO2_2 LDO2_1 DEFLDOx Bit name and function Default Default Value: set with DEFLDO1 and DEFLDO2 Default value loaded by: B2 B1 B0 LDO2_0 LDO1_2 LDO1_1 LDO1_0 DEFLDOx DEFLDOx DEFLDOx DEFLDOx DEFLDOx UVLO UVLO UVLO UVLO UVLO UVLO R/W R/W R/W R/W R/W R/W Read/Write B3 The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2. The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 3. LDO1 OUTPUT VOLTAGE LDO2_2 LDO2_1 LDO2_0 LDO2 OUTPUT VOLTAGE 0 1V 0 0 0 1.05 V 1 1.1 V 0 0 1 1.2 V 1 0 1.35 V 0 1 0 1.3 V 0 1 1 1.5 V 0 1 1 1.8 V 1 0 0 2.2 V 1 0 0 2.5 V 1 0 1 2.6 V 1 0 1 2.8 V 1 1 0 2.85 V 1 1 0 3V 1 1 1 3.15 V 1 1 1 3.3 V LDO1_2 LDO1_1 LDO1_0 0 0 0 0 0 DESIGN PROCEDURE Inductor Selection for the DC-DC Converters Each of the converters in the TPS65021 typically use a 3.3 H output inductor. Larger or smaller inductor values are used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest efficiency. For a fast transient response, a 2.2-H inductor in combination with a 22-F output capacitor is recommended. Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is needed because during heavy load transient the inductor current rises above the value calculated under Equation 4. 1 * Vout Vin DI + Vout L L (4) I Lmax + I outmax ) DI L 2 (5) with: f = Switching Frequency (1.5 MHz typical) L = Inductor Value IL = Peak-to-Peak inductor ripple current ILMAX = Maximum Inductor current The highest inductor current occurs at maximum Vin. Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents versus a comparable shielded inductor. 38 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS65021 (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core material from inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies. See Table 4 and the typical applications for possible inductors. Table 4. Tested Inductors DEVICE INDUCTOR VALUE TYPE 3.3 H CDRH2D14NP-3R3 Sumida 3.3 H LPS3010-332 Coilcraft 3.3 H VLF4012AT-3R3M1R3 TDK DCDC3 converter DCDC2 converter DCDC1 converter COMPONENT SUPPLIER 2.2 H VLF4012AT-2R2M1R5 TDK 3.3 H CDRH2D18/HPNP-3R3 Sumida 3.3 H VLF4012AT-3R3M1R3 TDK 2.2 H VLCF4020-2R2 TDK 3.3 H CDRH3D14/HPNP-3R2 Sumida 3.3 H CDRH4D28C-3R2 Sumida 3.3 H MSS5131-332 Coilcraft 2.2 H VLCF4020-2R2 TDK Output Capacitor Selection The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the TPS65021 allow the use of small ceramic capacitors with a typical value of 10 F for each converter without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. See Table 5 for recommended components. If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. Just for completeness, the RMS ripple current is calculated as: V 1 - out Vin 1 x IRMSCout = Vout x L x | 2 x O3 (6) At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: V 1 - out Vin 1 DVout = Vout x x + ESR L x | 8 x Cout x | ( ) (7) Where the highest output voltage ripple occurs at the highest input voltage Vin. At light load currents, the converters operate in PSM and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. Each dc-dc converter requires a 10-F ceramic input capacitor on its input pin VINDCDCx. The input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the input for the dc-dc converters. A filter resistor of up to 10R and a 1-F capacitor is used for decoupling the VCC pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can flow via this resistor into the VCC pin when all converters are running in PWM mode. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 39 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com Table 5. Possible Capacitors CAPACITOR VALUE CASE SIZE COMPONENT SUPPLIER COMMENTS 22 F 1206 TDK C3216X5R0J226M Ceramic 22 F 1206 Taiyo Yuden JMK316BJ226ML Ceramic 22 F 0805 TDK C2012X5R0J226MT Ceramic 22F 0805 Taiyo Yuden JMK212BJ226MG Ceramic 10 F 0805 Taiyo Yuden JMK212BJ106M Ceramic 10 F 0805 TDK C2012X5R0J106M Ceramic Output Voltage Selection The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down converter. See Table 6 for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 35. The output voltage of VDCDC3 is set with the I2C interface. If the voltage is changed from the default, using the DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC3 does not change the voltage set with the register. Table 6. PIN DEFDCDC1 DEFDCDC2 DEFDCDC3 LEVEL DEFAULT OUTPUT VOLTAGE VCC 3.3 V GND 3V VCC 2.5 V GND 1.8 V VCC 1.55 V GND 1.3 V Using an external resistor divider at DEFDCDCx: 10 R V(bat) VCC 1 mF VDCDC3 L3 VINDCDC3 VO L CI CO R1 DEFDCDC3 DCDC3_EN R2 AGND PGND Figure 35. External Resistor Divider When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input voltage V(bat). The total resistance (R1+R2) of the voltage divider should be kept in the 1-MR range in order to maintain a high efficiency at light load. V(DEFDCDCx) = 0.6 V VOUT = VDEFDCDCx x 40 R1 + R2 R2 R1 = R2 x ( VOUT VDEFDCDCx Submit Documentation Feedback ) - R2 (8) Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com VRTC Output The VRTC output is typically connected to the Vcc_Batt pin of a Intel(R) PXA270 processor. During power-up of the processor, the TPS65021 internally switches from the LDO or the backup battery to the system voltage connected at the VSYSIN pin (see Figure 25). It is required to add a capacitor of 4.7-F minimum to the VRTC pin, even the output may be unused. LDO1 and LDO2 The LDOs in the TPS65021 are general-purpose LDOs which are stable using ceramics capacitors. The minimum output capacitor required is 2.2 F. The LDOs output voltage can be changed to different voltages between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in applications powering processors different from PXA270. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and provides the highest efficiency. TRESPWRON This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V. The timing is generated by charging and discharging the capacitor with a current of 2 A between a threshold of 0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms. While there is no real upper and lower limit for the capacitor connected to TRESPWRON, it is recommended to not leave signal pins open. t(reset) = 2 x 128 x ( (1 V - 0.25 V) x C(reset) 2 mA ) (9) Where: t(reset) is the reset delay time C(reset) is the capacitor connected to the TRESPWRON pin The minimum and maximum values for the timing parameters called ICONST (2uA), TRESPWRON_UPTH (1V) and TRESPWRON_LOWTH (0.25V) can be found under the electrical characteristics. VCC-Filter An RC filter connected at the VCC input is used to prevent noise from the internal supply for the bandgap and other analog circuitry. A typical resistor value of 1 and 1 F is used to filter the switching spikes generated by the dc-dc converters. A resistor larger than 10 should not be used because the current (up to 3 mA) into VCC causes a voltage drop at the resistor. This causes the undervoltage lockout circuitry connected internally at VCC to switch off too early. Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 41 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com APPLICATION INFORMATION Layout Considerations As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulators may show poor line and/or load regulation, and stability issues as well as EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitors should be placed as close as possible to the IC pins as well as the inductor and output capacitor. For TPS65021, connect the PGND pins of the device to the PowerPADTM land of the PCB and connect the analog ground connections (AGND) to the PGND at the PowerPADTM. It is essential to provide a good thermal and electrical connection of all GND pins using multiple vias to the GND-plane. Keep the common path to the AGND pins, which returns the small signal components, and the high current of the output capacitors as short as possible to avoid ground noise. The VDCDCx line should be connected right to the output capacitor and routed away from noisy components and traces (for example, the L1, L2 and L3 traces). Input Voltage Connection The low power section of the control circuit for the step-down converters DCDC1, DCDC2 and DCDC3 is supplied by the Vcc pin while the circuitry with high power such as the power stage is powered from the VINDCDC1, VINDCDC2 and VINDCDC3 pins. For proper operation of the step-down converters, VINDCDC1, VINDCDC2,VNDCDC3 and Vcc need to be tied to the same voltage rail. Step-down converters that are plannned to be not used, still need to be powered from their input pin on the same rails than the other step-down converters and Vcc. LDO1 and LDO2 share a supply voltage pin which can be powered from the Vcc rails or from a voltage lower than Vcc e.g. the output of one of the step-down converters as long as it is operated within the input voltage range of the LDOs. If both LDOs are not used, the VINLDO pin can be tied to GND. Requirements for Supply Voltages below 3.0V For a supply voltage on pins Vcc, VINDCDC1, VINDCDC2 and VINDCDC3 below 3.0V, it is recommended to enable the DCDC1, DCDC2 and DCDC3 converters in sequence. If all 3 step-down converters are enabled at the same time while the supply voltage is close to the internal reset detection threshold, a reset may be generated during power-up. Therefore it is recommended to enable the dcdc convertes in sequence. This can be done by driving one or two of the enable pins with a RC delay or by driving the enable pin by the output voltage of one of the other step-down converters. If a voltage above 3.0V is applied on pin VBACKUP while Vcc and VINDCDCx is below 3.0V, there is no restriction in the power-up sequencing as VBACKUP will be used to power the internal circuitry. Unused Regulators In case a step-down converter is not used, its input supply voltage pin VINDCDCx still needs to be connected to the Vcc rail along with supply input of the other step-down converters. It is recommended to close the control loop such that an inductor and output capacitor is added in the same way as it would be when operated normally. If one of the LDOs is not used, its output capacitor should be added as well. If both LDOs are not used, the input supply pin as well as the output pins of the LDOs (VINLDO, VLDO1, VLDO2) should be tied to GND. 42 Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 TPS65021 SLVS613C - OCTOBER 2005 - REVISED SEPTEMBER 2011 www.ti.com TYPICAL CONFIGURATION FOR THE Intel(R) PXA270 BULVERDE PROCESSOR Vcc_IO Vcc PWRFAIL 10 R nBatt_Fault Vcc 1 mF 10 mF 10 mF 10 mF LOW_BATT VINDCDC1 GPIOx VRTC Vcc_Batt DCDC2_EN VINDCDC2 SYS_EN DCDC1_EN VINDCDC3 VDCDC1 TPS65021 Vcc L1 2.2 mH PWRFAIL_SNS LOWBAT_SNS 2.2 mH Vcc_IO 3 V; 3.3 V Vcc_LCD 1.8 V; 2.5 V; 3 V; 3.3 V Vcc_BB 1.8 V; 2.5 V; 3 V; 3.3 V Vcc_MEM 1.8 V; 2.5 V; 3 V; 3.3 V Vcc_USIM 1.8 V; 3 V 22 mF VDCDC2 L2 Vcc 3V 4.7 mF 22 mF VIN_LDO 1 MR HOT_RESET DCDC3_EN LDO_EN 1nF TRESPWRON LDO1 Vcc_PLL 1.3 V 2.2 mF GND DEFLDO1 GND DEFLDO2 VDCDC1 PWR_EN Vcc_SRAM 1.1 V LDO2 2.2 mF Vcc DEFDCDC1 VDCDC3 INT DEFDCDC2 RESPWRON DEFDCDC3 3V backup battery L3 VSYSIN VBACKUP 2.2 mH Vcc_CORE variable 0.85 V to 1.4 V 22mF nVcc_Fault nRESET SCLK SCLK SDAT SDAT 4.7 kW 4.7 kW Vcc_Batt Vcc_Batt Submit Documentation Feedback Copyright (c) 2005-2011, Texas Instruments Incorporated Product Folder Link(s) : TPS65021 43 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) TPS65021RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPS 65021 TPS65021RHARG4 ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPS 65021 TPS65021RHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPS 65021 TPS65021RHATG4 ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPS 65021 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65021RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 TPS65021RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65021RHAR VQFN RHA 40 2500 367.0 367.0 38.0 TPS65021RHAT VQFN RHA 40 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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