S1F75510M0A0 - EPSON ELECTRONICS AMERICA

Rev. 1.0 1

S1F75510

■DESCRIPTION

The S1F75510 is a power IC designed for use with medium or small capacity TFT–LCD panel modules.

A single chip of this IC is capable of generating three different levels of positive and negative output voltages

simultaneously, which are necessary to drive the LCD, by use of a single input power of +2.7 through +3.6V.

Since the S1F75510 does not require external transistors nor diodes as its voltage conversion circuit, its built-

in CMOS transistors constituting a complete charge pump type DC/DC converter, it is most suitable for the

purpose of reducing the current consumption levels of the LCD modules.

Moreover, the charge pump type DC/DC converter of the S1F75510 can be operated upon the frequencies,

which are to be switched over by the mode changing signals, using either of the built-in clock signals or external

clock signals optimal to respective cases.

This function can drastically suppress the current consumption of this IC while under light load state, thus

exhibiting very high power conversion efficiencies.

■FEATURES

●Supply voltage ································································ 2.7V to 3.6V single power input

●Self consumption current (normal mode/blank mode) ···· 300µA / 30µA (TBD)

Normal mode: Boosting by use of the internal clock

Blank mode: Selectable between boosting by use of the internal clock or by use of the external clock.

●Conversion efficiency of the charge pump······················ 90% or more respectively

●Built-in voltage conversion circuits constituted by charge pump type DC/DC converter,

• ✕2 boosting circuit in the positive direction

• ✕3 boosting circuit in the positive direction

• ✕3 boosting circuit in the negative direction

●Built-in voltage stabilizing circuit

●Capable of outputting the positive supply voltage VOUT2 for the source driver

• ✕2 boosting circuit in the positive direction + voltage stabilizing circuit

Output voltage: +5.0V ±3% (TBD)

●Capable of outputting the positive supply voltage VOUT3 for the gate driver

• ✕3 boosting circuit in the positive direction

Output voltage: +15V

VOUT3 = VOUT2 ✕ 3

●Capable of outputting the negative supply voltage VOUT4 for the gate driver

• ✕3 boosting circuit in the negative direction

Output voltage: –10V

VOUT4 = VOUT2 ✕ –2

●Built-in electric charge discharging circuit

●Built-in shut down function

●Shipping state ································································· SSOP3–24pin

●This IC is not of the radiation resistant design nor of the light resistance design.

Charge-pump DC/DC Converter &

Voltage Regulator

S1F75510

PF1233-01

Preliminary

2Rev. 1.0

S1F75510

■BLOCK DIAGRAM

VDD

VSS

POFFX

ROSC

OSC1

C1P

C1N

C2P

C2N

C3P

C3N

C4P

C4N

CVOUT4

CVOUT3

CVOUT2

CVOUT1

C5P

C5N

C6P

C6N

OSC2

MODE

OSCSEL

VOUT1

VOUT2

VOUT3

VOUT4

(8)

Discharging

circuit

(1)

CR oscillation circuit

(2)

Mode changeover

circuit

(3)

Timing signal forming

circuit

(4)

×2 boosting circuit in

the positive direction

(5)

Voltage stabilizing

circuit

(6)

×3 boosting circuit in

the positive direction

(7)

×3 boosting circuit in

the negative direction

Fig. 1 Block diagram

Rev. 1.0 3

S1F75510

■DESCRIPTIONS FOR THE BLOCK DIAGRAM

(1) CR oscillation circuit

The oscillation circuit is constituted by connecting a resistor between the OSC1 pin and the OSC2 pin. The

clock signals being generated by this oscillation circuit will become effective as boosting clock signals while the

mode changeover signal MODE is on the VDD level (normal mode) or while the mode changeover signal MODE

is on the VSS level and, at the same time, when the internal/external clock selection signal OSCSEL is on the

VDD level (blank mode · internal clock). When the MODE is set to the V SS level and, at the same time, when the

OSCSEL is set to the VSS level (blank mode · external clock), the oscillation will be interrupted.

(2) Mode changeover circuit

The operation modes of the boosting circuit and voltage stabilizing circuit are being switched over by the mode

changeover signal MODE. Also, it selects the clock signals to feed to the timing signal forming circuit from

either of the external clock signals or internal clock signals.

(3) Timing signal forming circuit

This circuit generates the charge pump boosting clock signals. This circuit outputs timing signals of the clock

type (internal clock or external clock) having been selected by the mode changeover circuit to drive respective

boosting circuits. When the shut down signal POFFX is set to the V SS level, the timing signal stops to interrupt

the boosting operation.

(4) ✕2 boosting circuit in the positive direction

This circuit makes ✕2 boosting in the positive direction by charge pump boosting upon the inputted supply

voltage VDD – VSS using the VSS potential as the reference voltage. The ✕2 boosted output will enter into the

voltage stabilizing circuit.

(5) Voltage stabilizing circuit

This circuit generates the positive supply voltage VOUT2 for the source driver. ON the basis of the built-in

reference, this circuit stabilizes the output from the above "(4) ✕2 boosting circuit in the positive direction" by

use of the series regulator.

(6) ✕3 boosting circuit in the positive direction

This circuit generates the positive supply voltage VOUT3 for the gate driver. This circuit effects ✕3 boosting in

the positive direction by charge pump boosting upon the voltage VOUT2 – VSS using the VSS potential as the

reference voltage.

(7) ✕3 boosting circuit in the negative direction

This circuit generates the negative supply voltage VOUT4 for the gate driver. This circuit effects ✕3 boosting in

the negative direction by charge pump boosting upon the voltage VOUT2 – VSS using the VOUT2 potential as the

reference voltage.

(8) Electric charge discharging circuit

This circuit discharges the electric charge remaining in the VOUT3 pin and VOUT4 pin to the VSS level. This

circuit will work when the POFFX pin is set to the VSS level.

4Rev. 1.0

S1F75510

■PIN ASSIGNMENT

SSOP3–24pin S1F75510M0A0

Pin No. Pin name Pin No. Pin name

1 C3N 13 MODE

2 C3P 14 CL

3 C4P 15 POFFX

4 C4N 16 OSC1

5VOUT3 17 OSC2

6VDD 18 OSCSEL

7 C1N 19 VOUT2

8 C1P 20 VOUT4

9VOUT1 21 C6P

10 C2P 22 C6N

11 C2N 23 C5N

12 VSS 24 C5P

24 13

112

Rev. 1.0 5

S1F75510

■PIN DESCRIPTION

(1) CR oscillation circuit · Mode changeover circuit · Timing signal forming circuit · Electric charge discharging

circuit

MODE OSCSEL Function

HIGH(VDD) HIGH(VDD) Normal mode

LOW(VSS) The boosting clock signals are being

generated through the internal

oscillation.

The built-in oscillation circuit will ope-

rate and the voltage stabilizing circuit

will operate.

LOW(VSS) HIGH(VDD) Blank mode (internal oscillation)

The boosting clock signals are being

generated through the internal

oscillation.

The built-in oscillation circuit will

operate and the voltage stabilizing

circuit will operate under low current

consumption state.

LOW(VSS) Blank mode (external oscillation)

The boosting clock signals are being

generated by the external clock.

The built-in oscillation circuit will be

interrupted and the voltage stabiliz-

ing circuit will operate under low

current consumption state.

Pin name I/O Pin No. Function

POFFX I 15 This is the shut down pin. Set it to the VDD level while the IC is in

operation. When this signal is set to the VSS level, operations of all

the circuits will be interrupted bringing the IC into the shut down

state. The electric charge discharging circuit discharges the electric

charge remaining in the VOUT3 pin and VOUT4 pin to the VSS level.

OSC1 I 16 This is the CR oscillation circuit gate input pin. This is the pin to

connect the oscillation resistor. Fix it to the VSS level in case the

built-in oscillation circuit will not be used.

OSC2 O 17 This is the CR oscillation circuit drain input pin. Connect the osci-

llation resistor between this pin and the OSC1 pin.

CL I 14 This is the boosting external clock signal input pin. Input the charge

pump clock signals under the blank mode into this pin.

MODE I 13 This is the mode changeover pin.

OSCSEL I 18 This is the pin for selection between the internal clock and exter-

nal clock signals.

6Rev. 1.0

S1F75510

Pin name I/O Pin No. Function

VOUT1 O 9 This is the output pin of the ✕2 boosting circuit in the positive

direction.

C1P (O) 8 This is the pin to connect the positive side of the VOUT1 output

voltage generating flying capacitor C1.

C1N (O) 7 This is the pin to connect the negative side of the VOUT1 output

voltage generating flying capacitor C1.

C2P (O) 10 This is the pin to connect the positive side of the VOUT1 output

voltage generating flying capacitor C2.

C2N (O) 11 This is the pin to connect the negative side of the VOUT1 output

voltage generating flying capacitor C2.

(2) ✕2 boosting circuit in the positive direction

(3) Voltage stabilizing circuit

Pin name I/O Pin No. Function

VOUT1 I 9 This is the input power pin (+) for the voltage stabilizing circuit.

This pin is being connected to the output pin of the ✕2 boosting

circuit in the positive direction internally, inside this IC.

VOUT2 O 19 This is the output pin of the voltage stabilizing circuit.

(4) ✕3 boosting circuit in the positive direction

Pin name I/O Pin No. Function

VOUT3 O 5 This is the output pin of the ✕3 boosting circuit in the positive

direction.

C3P (O) 2 This is the pin to connect the positive side of the VOUT3 output

voltage generating flying capacitor C3.

C3N (O) 1 This is the pin to connect the negative side of the VOUT3 output

voltage generating flying capacitor C3.

C4P (O) 3 This is the pin to connect the positive side of the VOUT3 output

voltage generating flying capacitor C4.

C4N (O) 4 This is the pin to connect the negative side of the VOUT3 output

voltage generating flying capacitor C4.

Rev. 1.0 7

S1F75510

(5) ✕3 boosting circuit in the negative direction

Pin name I/O Pin No. Function

VOUT4 O 20 This is the output pin of the ✕3 boosting circuit in the negative

direction.

C5P (O) 24 This is the pin to connect the positive side of the VOUT4 output

voltage generating flying capacitor C5.

C5N (O) 23 This is the pin to connect the negative side of the VOUT4 output

voltage generating flying capacitor C5.

C6P (O) 21 This is the pin to connect the positive side of the VOUT4 output

voltage generating flying capacitor C6.

C6N (O) 22 This is the pin to connect the negative side of the VOUT4 output

voltage generating flying capacitor C6.

(6) Power pins

Pin name I/O Pin No. Function

VDD I 6 This is the input power pin (+).

VSS I 12 This is the input power pin (–).

8Rev. 1.0

S1F75510

■FUNCTIONAL DESCRIPTION

●Operational description

Generating voltage levels are:

· Positive boosting supply voltage necessary for the voltage stabilizing circuit (VOUT1)

· Positive stabilized supply voltage necessary for the source driver (VOUT2)

· Positive and negative boosting supply voltages necessary for the gate driver (VOUT3 and VOUT4)

The VOUT1 supply voltage is being generated by the charge pump type DC/DC converter (✕2 boosting circuit in

the positive direction). It makes ✕2 boosting in the positive direction of the potential difference occurring be-

tween the VDD – VSS using the VSS potential as the reference voltage.

The V OUT2 supply voltages is being generated by the series regulator stabilizing the potential difference occur-

ring between the VOUT1 – VSS using the VSS potential as the reference voltage.

The VOUT3 supply voltage is being generated by the charge pump type DC/DC converter (✕3 boosting circuit in

the positive direction). It makes ✕3 boosting in the positive direction of the potential difference occurring be-

tween the VOUT2 – VSS using the VSS potential as the reference voltage.

The VOUT4 supply voltage is being generated by the charge pump type DC/DC converter (✕3 boosting circuit in

the negative direction). It makes ✕3 boosting in the negative direction of the potential difference occurring

between the VOUT2 – VSS using the VOUT2 potential as the reference voltage.

Indicated below is the system configuration diagram for the power circuit.

Fig. 2 System configuration diagram

Gate driver LCD panel

Source driverS1F75510

VSS

VDD

VOUT2

VOUT3, VOUT4

Rev. 1.0 9

S1F75510

Indicated below is the potential correlation diagram inside the system as is shown in Fig. 2.

●CR oscillation circuit

The S1F75510 incorporates a CR oscillation circuit as the oscillation circuit for the boosting clock signals. This

circuit is to be used connecting the external oscillation resistor ROSC between the OSC1 pin and the OSC2 pin.

The CR oscillation circuit will stop operation under the blank mode and when using the external clock (MODE =

VSS level and OSCSEL = VSS level) or under the shut down state (POFFX = VSS level). Also, the oscillation will

be interrupted by setting the OSC1 pin to the VSS level and, at the same time, setting the OSC2 pin into open

state.

As the external oscillation resistance, we recommend use of ROSC = 1 MΩ.

VDD

VSS

VOUT4

VOUT2

VOUT1

VOUT3

×3 boosting in the

positive direction

Voltage stabilizing

×3 boosting in the

negative direction

Source driver

Power Supply IC (S1F75510)

Gate driver

×2 boosting in the

positive direction

Fig. 3 Potential correlation diagram inside the system

10 Rev. 1.0

S1F75510

●Mode changeover circuit

By external settings of the mode changeover signal MODE and the internal/external clock selection signal

OSCSEL, the charge pump boosting can be driven under optimum frequencies. Since the current consumption

of the IC can be suppressed drastically under the blank mode, it is possible to achieve high power conversion

efficiency even under light load operations.

MODE pin OSCSEL Mode name Max. output current

Built-in CR

Built in voltage

oscillation circuit

stabilizing circuit

HIGH(VDD)VOUT2:(10mA) (TBD)

HIGH(VDD) Normal mode VOUT3:(100µA) (TBD) In operation In normal operation

LOW(VSS)VOUT4:(100µA) (TBD)

VOUT2:(200µA) (TBD)

HIGH(VDD) Blank mode VOUT3:(10µA) (TBD) In operation In low current

LOW(VSS)VOUT4:(10µA) (TBD) consumption operation

VOUT2:(200µA) (TBD)

LOW(VSS) Blank mode VOUT3:(10µA) (TBD) In standstill In low current

VOUT4:(10µA) (TBD) consumption operation

●Timing signal forming circuit

This circuit generates the clock signals necessary for charge pump boosting using the internal oscillation or

using external clock signals.

Two different types of capacitors are being used as the charge pump capacitors, one being the flying capacitor

which shifts between the charging state and the discharging state and the other being the smoothing capacitor

which preserves the electric charge. The operating frequency of the flying capacitor should equal to the fre-

quency of the charge pump clock being generated by this timing signal forming circuit.

Under the shut down state (POFFX = VSS level), the charge pump clock stops operation and all the boosting

operations of this IC will be interrupted. The operating frequencies of the flying capacitor are as follows.

MODE pin OSCSEL Mode name Operating frequencies of the flying capacitor

pin ✕2 boosting in ✕3 boosting in ✕3 boosting in

the positive direction

the negative direction

HIGH(VDD)HIGH(VDD)Normal mode (TBD) kHz (TBD) kHz (TBD) kHz

LOW(VSS) (Typ.10 kHz) (Typ.10 kHz) (Typ.10 kHz)

HIGH(VDD) Blank mode (TBD) kHz (TBD) kHz (TBD) kHz

(Typ.625 Hz) (Typ.625 Hz) (Typ.625 Hz)

LOW(VSS) Blank mode (TBD) Hz (TBD) Hz (TBD) Hz

LOW(VSS) CL=(TBD) Hz

(Min.300 Hz) (Min.150 Hz) (Min.150 Hz) (Min.150 Hz)

Rev. 1.0 11

S1F75510

●✕2 boosting circuit in the positive direction

The ✕2 boosting circuit in the positive direction generates the voltages necessary to input into the voltage

stabilizing circuit. It makes ✕2 boosting in the positive direction of the potential difference occurring between the

VDD – VSS using the VSS potential as the reference voltage to output through the VOUT1 pin.

Under the blank mode, since the boosting operation is being carried out with the flying capacitor C2 stopping its

operation, the current consumption can be suppressed accordingly.

The theoretical equation (output voltage value under the idealistic non-load state) for the VOUT1 becomes as

follows:

VOUT1 = (VDD – VSS) ✕ 2

Actually, when a load is connected to the VOUT1, the output voltage will drop to the value represented by the

equation indicated below.

VOUT1 = (VDD – VSS) ✕ 2 – RVOUT1 ✕ IVOUT1

RVOUT1 : Output impedance of the x2 boosting circuit in the positive direction

IVOUT1 : Load current

●Voltage stabilizing circuit

The voltage stabilizing circuit stabilizes the voltage being output through the VOUT1 pin by the series regulator

to output the positive supply voltage for the source driver through the VOUT2 pin.

The output voltage setting for the VOUT2 pin should be Typ. +5.0V (TBD).

Since it is necessary to let the VOUT1 satisfy the correlation of "VOUT1 > VOUT2 + 0.1V" in order to obtain normal

output voltage value through the VOUT2 pin, use the IC within the range of the max. load current (7.3).

The circuit configuration · connection diagram for the voltage stabilizing circuit is as follows:

Fig. 4 Configuration diagram of the voltage stabilizing circuit

To the source driver

[Internal structure of the S1F75510]

Voltage stabilizing

circuit

Reference voltage circuit

OUT1

= (V

–V

) × 2

OUT1

CVOUT1

CVOUT2

OUT2

–

×2 boosting circuit in the

positive direction

×3 boosting circuit in the positive direction

×3 boosting circuit in the negative direction

12 Rev. 1.0

S1F75510

●✕3 boosting circuit in the positive direction

The ✕3 boosting circuit in the positive direction generates the VOUT3 output voltage, means the positive supply

voltage for the gate driver. It makes ✕3 boosting in the positive direction of the potential difference occurring

between the VOUT2 – V SS using the VSS potential as the reference voltage, by charge pump boosting, to output

through the VOUT3 pin.

The theoretical equation (output voltage value under the idealistic non-load state) for the VOUT3 becomes as

follows:

VOUT3 = (V OUT2 – VSS) ✕ 3

Actually, when a load is connected to the VOUT3, the output voltage will drop to the value represented by the

equation indicated below.

VOUT3 = (VOUT2 – VSS) ✕ 3 – (RVOUT3 ✕ IVOUT3)

RVOUT3 : Output impedance of the ✕3 boosting circuit in the positive direction

IVOUT3 : Load current

It means that the VOUT3 voltage will drop by the load.

To acquire desired output voltage, use the IC within the range of the specified load (7.3).

●✕3 boosting circuit in the negative direction

The ✕3 boosting circuit in the negative direction generates the VOUT3 output voltage, means the negative

supply voltage for the gate driver. It makes ✕3 boosting in the negative direction of the potential difference

occurring between the VOUT2 – VSS using the VOUT2 potential as the reference voltage, by charge pump boost-

ing, to output through the VOUT4 pin.

The theoretical equation (output voltage value under the idealistic non-load state) for the VOUT4 becomes as

follows:

VOUT4 = (VOUT2 – VSS) ✕ (–2) (The voltage value using the VSS potential as the reference voltage)

Actually, when a load is connected to the VOUT4, the output voltage will drop to the value represented by the

equation indicated below.

VOUT4 = (VOUT2 – VSS) ✕ (–2) – (RVOUT4 ✕ IVOUT4)

RVOUT4 : Output impedance of the ✕3 boosting circuit in the negative direction

IVOUT4 : Load current

It means that the VOUT4 voltage will drop by the load.

To acquire desired output voltage, use the IC within the range of the specified load (7.3).

●Electric charge discharging circuit

The electric charge discharging circuit discharges the electric charge remaining in the VOUT3 pin and VOUT4 pin

to the VSS level.

This circuit starts operation when the POFFX pin is set to the VSS level.

The discharging sequence and the discharging impedance are according to the (TBD).

Rev. 1.0 13

S1F75510

Rating Unit

Applicable

Remarks

Item Symbol Min. Max. pin

Input supply voltage VDD – 0.3 4.0 V VDD —

Output voltage 1 VOUT1 – 0.3 7.5 V VOUT1 —

Output voltage 2 VOUT2 – 0.3 7.5 V VOUT2 —

Output voltage 3 VOUT3 – 0.3 22.5 V VOUT3 —

Output voltage 4 VOUT4 – 15.0 0.3 V VOUT4 —

Input pin voltage 1 VIN – 0.3 VDD + 0.3 V <Note 1> —

Input current IVDD — (TBD) mA VDD

Output current 1 IVOUT1 — (TBD) mA VOUT1 —

Output current 2 IVOUT2 — (TBD) mA VOUT2 —

Output current 3 IVOUT3 — (TBD) mA VOUT3 —

Output current 4 IVOUT4 — (TBD) mA VOUT4 —

Allowable dissipation PD— (TBD) mW — Ta ≤ 55˚C

Operating temperature Topr – 30 85 ˚C — —

Storage temperature Tstg – 55 150 ˚C — —

Soldering temperature Tsol — 260·10 ˚C·s — At leads

and time

■ABSOLUTE MAXIMUM RATINGS

<Note 1> The applicable pins are POFFX, OSC1, CL, MODE and OSCSEL.

<Note 2> Do not apply external voltage to the output pins and the pin connecting to the capacitor.

<Note 3> Use of the IC under any conditions exceeding the above absolute maximum ratings may cause malfunc-

tioning or permanent breakdown. Or, even if the IC may operate normally temporarily, the reliability may

greatly drop.

14 Rev. 1.0

S1F75510

■ELECTRICAL CHARACTERISTICS

●DC characteristics In case particular designations are not made (Note 1): Ta = –10 to +70˚C

Item Symbol Conditions Rating Unit

Remarks

Min. Typ. Max.

Input supply voltage VDD Applicable pin: VDD (TBD) 3.0 3.6 V —

High level input voltage VIH — 0.8VDD —VDD V2

Low level input voltage VIL — 0 — 0.2VDD V2

Input leak current 1 ILKI1 VSS ≤ VI ≤ VDD, – 0.5 — 0.5 µA2

VDD = (TBD) to 3.6V

Current consumption 1 IOPR1 VDD = 3.0V, no load — (TBD) (TBD) µA—

Under the normal mode

(300)

Current consumption 2 IOPR2 VDD = 3.0V, no load — (TBD) (TBD) µA—

Under the blank mode (30)

CL = (TBD) kHz

Power conversion efficiency 1

Peff1 VDD = 3.0V (TBD) (TBD) (TBD) % 3

(Overall efficiency including Under the normal mode

the stabilized outputs)

Power conversion efficiency 2

Peff2 VDD = 3.0V (TBD) (TBD) (TBD) % 4

(Overall efficiency including

Under the blank mode

the stabilized outputs) CL = (TBD) kHz

Resting current IQ VDD = 3.6V — — (TBD) µA—

POFFX = LOW (1.0)

<Note 1> Conditions on the operation mode, external parts constant, pins, etc. in case particular designations are

not made are as follows.

Connection and parts constant : Standard connection 1, 10.1

MODE pin : MODE = HIGH (Normal mode)

CL pin : CL = LOW (Fixed voltage)

<Note 2> The applicable pins are XDIS, SSLP, PCK1 and CNT

<Note 3> Load conditions: IVOUT2 = (TBD)mA, IVOUT3 = (TBD)µA, IVOUT4 = (TBD)µA

Conversion efficiency = [(VOUT2 ✕ IVOUT2) + (VOUT3 ✕ IVOUT3) + (V OUT4 ✕ IVOUT4)] / (VDD* ✕ IVDD*) ✕ 100

<Note 4> Load conditions: IVOUT2 = (TBD)µA, IVOUT3 = (TBD)µA, IVOUT4 = (TBD)µA

Conversion efficiency = [(VOUT2 ✕ IVOUT2) + (VOUT3 ✕ IVOUT3) + (V OUT4 ✕ IVOUT4)] / (VDD* ✕ IVDD*) ✕ 100

Rev. 1.0 15

S1F75510

●Characteristics of ✕2 boosting in the positive direction + stabilized outputTa = –10 to +70˚C

Item Symbol Conditions Rating Unit

Remarks

Min. Typ. Max.

VOUT1 output impedance RVOUT1-1 Applicable pin: — (TBD) (TBD) Ω5

(Normal mode) VOUT1

VOUT1 output impedance RVOUT1-2 Applicable pin: — (TBD) (TBD) Ω6

(Blank mode) VOUT1

VOUT2 VOUT2 Applicable pin: (TBD) (TBD) (TBD) V 7

Stabilized output voltage VOUT2 (4.90) (5.00) (5.20)

VOUT2 Stabilized output RVOUT2 Applicable pin: — — 10 Ω8

saturated resistance VOUT2

<Note 5> VDD = (TBD)V to 3.6V, Load condition: IVOUT1 = (TBD)mA

<Note 6> VDD = (TBD)V to 3.6V, Load condition: IVOUT1 = (TBD)mA

<Note 7> VDD = (TBD)V to 3.6V, Load condition: IVOUT2 = (TBD)mA

<Note 8> VDD = (TBD)V to 3.6V, Load condition: IVOUT2 = (TBD)mA

●Characteristics of ✕3 boosting in the positive direction and ✕3 boosting in he negativet

direction Ta = –10 to +70˚C

Item Symbol Conditions Rating Unit

Remarks

Min. Typ. Max.

VOUT3 output impedance RVOUT3-1 Applicable pin: — (TBD) (TBD) Ω9

(Normal mode) VOUT3

VOUT3 output impedance RVOUT3-2 Applicable pin: — (TBD) (TBD) Ω10

(Blank mode) VOUT3

VOUT4 output impedance RVOUT4-1 Applicable pin: — (TBD) (TBD) Ω11

(Normal mode) VOUT4

VOUT4 output impedance RVOUT4-2 Applicable pin: — (TBD) (TBD) Ω12

(Blank mode) VOUT4

<Note 9> VDD = (TBD)V to 3.6V, Load condition: IVOUT3 = (TBD)µA

<Note 10> VDD = (TBD)V to 3.6V, Load condition: IVOUT3 = (TBD)µA

<Note 11> VDD = (TBD)V to 3.6V, Load condition: IVOUT4 = (TBD)µA

<Note 12> VDD = (TBD)V to 3.6V, Load condition: IVOUT4 = (TBD)µA

16 Rev. 1.0

S1F75510

●AC characteristics

Measurement conditions for the AC characteristics

· Input signal level VIH = 0.8 VDD (V)

VIL = 0.2 VDD (V)

· Input signal rise time Tr = Max. 100ns

· Input signal fall time Tf = Max. 100ns

VDD = (TBD) to 3.6V, VSS = 0V

Ta = –10 to +70˚C

CL inputting timing

Item Symbol Rating Unit

Applicable

Remarks

Min. Typ. Max. pin

CL cycle tCCK (TBD) (TBD) (TBD) µs

CL High pulse duration tWHCK (TBD) — — ns CL —

CL Low pulse duration tWICK (TBD) — — ns

tWHCK

tWLCK

tCCK

VIH

VILVIL

VIHVIH

Rev. 1.0 17

S1F75510

■REFERENCE EXTERNAL CONNECTION (AN EXAMPLE)

●Standard connection 1

VDD

VSS

CVOUT1

CVOUT2

CVOUT3

CVOUT4

POFFX

OSC1

OSC2

MODE

OSCSEL

VSS

POFFX

MODE

OSCSEL

C1P

C1N

C2P

C2N

C3P

C3N

C4P

C4N

VOUT4

VOUT3

VOUT2

VOUT1 VOUT1

VOUT2

VOUT3

VOUT4

C5P

C5N

C6P

C6N

ROSC

Reference values for the

external parts

ROSC=1MΩ

C1=C2=CVOUT1=4.7µF

CVOUT2=4.7µF

C3=C4=CVOUT3=1.0µF

C5=C6=CVOUT4=1.0µF

S1F75510

18 Rev. 1.0

■DIMENSIONAL OUTLINE DRAWING

SSOP3–24pin

Unit : mm

0 ~ 10°

5.6±0.2

7.6±0.2

1.15±0.1

0.10±0.05

0.375 Typ .

7.9±0.2

0.5±0.2

0.10

0.22

+0.1

–0.05

0.15

+0.1

–0.05

0.65

0.12 M

ELECTRONIC DEVICES MARKETING DIVISION

NOTICE:

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson

reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any

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Printed in Japan H

IC Marketing & Engineering Group

ED International Marketing Department

Europe & U.S.A

421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: 042

–

587

–

5812 FAX: 042

–

587

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5564

ED International Marketing Department

Asia

421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: 042

–

587

–

5814 FAX: 042

–

587

–

5110

■ EPSON Electronic Devices Website

http://www.epson.co.jp/device/

First issue July, 2001