eGaN(R) FET DATASHEET EPC2019 EPC2019 - Enhancement Mode Power Transistor VDS, 200 V RDS(on) , 50 mW ID , 8.5 A D EFFICIENT POWER CONVERSION G Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 60 years. GaN's exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VALUE UNIT Drain-to-Source Voltage (Continuous) 200 V Continuous (TA = 25C, RJA = 18C/W) 8.5 Pulsed (25C, TPULSE = 300 s) 42 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 VDS ID VGS HAL S A V C EPC2019 eGaN(R) FETs are supplied only in passivated die form with solder bars Applications * High Speed DC-DC conversion * Class-D Audio * High Frequency Hard-Switching and Soft-Switching Circuits Benefits * Ultra High Efficiency * Ultra Low RDS(on) * Ultra Low QG * Ultra Small Footprint www.epc-co.com/epc/Products/eGaNFETs/EPC2019.aspx Thermal Characteristics PARAMETER TYP RJC Thermal Resistance, Junction to Case 2.7 RJB Thermal Resistance, Junction to Board 7.5 RJA Thermal Resistance, Junction to Ambient (Note 1) 72 UNIT C/W Note 1: RJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25C unless otherwise stated) PARAMETER TEST CONDITIONS MIN 200 TYP MAX UNIT BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 A IDSS Drain-Source Leakage VGS = 160 V, VDS = 0 V 20 100 A Gate-to-Source Forward Leakage VGS = 5 V 0.8 2.5 mA Gate-to-Source Reverse Leakage VGS = -4 V 20 100 A IGSS VGS(TH) Gate Threshold Voltage RDS(on) Drain-Source On Resistance VSD Source-Drain Forward Voltage VDS = VGS, ID = 1.5 mA 0.8 V 1.4 2.5 V VGS = 5 V, ID = 7 A 3.6 50 m IS = 0.5 A, VGS = 0 V 1.8 V All measurements were done with substrate connected to source. EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1 eGaN(R) FET DATASHEET EPC2019 Dynamic Characteristics (TJ = 25C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX 200 270 110 150 1 CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance 0.7 RG Gate Resistance 0.4 QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge VGS = 100 V, VDS = 0 V VDS = 100 V, VGS = 5 V, ID = 7 A UNIT pF 1.8 2.5 0.6 VDS = 100 V, ID = 7 A 0.35 0.6 nC 0.4 VDS = 100 V, VDS = 0 V 18 23 0 All measurements were done with substrate connected to source. Figure 2: Transfer Characteristics 40 40 35 35 30 30 ID - Drain Current (A) ID - Drain Current (A) Figure 1: Typical Output Characteristics at 25C 25 20 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 15 10 20 15 10 5 0 1 2 3 4 5 VDS - Drain-to-Source Voltage (V) Figure 3: RDS(on) vs. VGS for Various Drain Currents 100 60 40 20 2.0 2.5 3.0 3.5 4.0 0.5 120 ID = 4 A ID = 8 A ID = 12 A ID = 24 A 80 0 0 6 RDS(on) - Drain-to-Source Resistance (m) 120 RDS(on) - Drain-to-Source Resistance (m) VDS = 6 V 25 5 0 25C 125C 4.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS - Gate-to-Source Voltage (V) 4.0 4.5 5.0 Figure 4: RDS(on) vs. VGS for Various Temperatures 25C 125C 100 ID = 7 A 80 60 40 20 5.0 VGS - Gate-to-Source Voltage (V) EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VGS - Gate-to-Source Voltage (V) | 2 eGaN(R) FET DATASHEET EPC2019 Figure 5a: Capacitance (Linear Scale) Figure 5b: Capacitance (Log Scale) 400 1000 350 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 100 Capacitance (pF) Capacitance (pF) 300 250 200 150 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 1 100 50 0 0 50 100 150 0.1 200 VDS - Drain-to-Source Voltage (V) Figure 6: Gate Charge 50 16 ID = 7 A VDS = 100 V 150 200 25C 125C 14 ISD - Source-to-Drain Current (A) 4 100 VDS - Drain-to-Source Voltage (V) Figure 7: Reverse Drain-Source Characteristics 5 VGS - Gate-to-Source Voltage (V) 0 3 2 1 12 10 8 6 4 2 0 0 0.5 1.0 QG - Gate Charge (nC) 1.5 0 2.0 Figure 8: Normalized On-State Resistance vs. Temperature 1.5 2.0 2.5 3.0 3.5 4 .0 4.5 5.0 Figure 9: Normalized Threshold Voltage vs. Temperature 1.3 ID = 7 A VGS = 5 V Normalized Threshold Voltage (V) Normalized On-State Resistance RDS(on) 1.0 1.4 1.6 1.4 1.2 1.0 0.8 0.5 VSD - Source-to-Drain Voltage (V) 2.0 1.8 0 ID = 1.5 mA 1.2 1.1 1.0 0.9 0.8 0.7 0 25 50 75 100 TJ - Junction Temperature (C) 125 150 0.6 0 25 50 75 100 TJ - Junction Temperature (C) 125 150 All measurements were done with substrate shortened to source. EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 3 eGaN(R) FET DATASHEET EPC2019 Figure 10: Gate Leakage Current 6 25C 125C IG - Gate Current (mA) 5 4 3 2 1 0 0 1 2 3 4 5 VGS - Gate-to-Source Voltage (V) 6 Figure 11: Transient Thermal Response Curves Junction-to-Board ZJB, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.1 0.1 PDM 0.05 t1 0.02 0.01 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZJB x RJB + TB Single Pulse 0.001 10-5 t2 10-4 10-3 10-2 10-1 1 10+1 tp, Rectangular Pulse Duration, seconds Junction-to-Case ZJC, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 PDM t1 0.001 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZJC x RJC + TC Single Pulse 0.0001 10-6 t2 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 4 eGaN(R) FET DATASHEET EPC2019 Figure 12: Safe Operating Area I D - Drain Current (A) 100 10 Limited by RDS(on) Pulse Width 100 ms 10 ms 1 ms 100 s 10 s 1 0.1 TJ = Max Rated, TC = +25C, Single Pulse 0.1 1 10 100 1000 VDS - Drain-Source Voltage (V) TAPE AND REEL CONFIGURATION 4 mm pitch, 8 mm wide tape on 7" reel 7" reel d e f Loaded Tape Feed Direction g b 2019 YYYY ZZZZ a c a b c (see note) d e f (see note) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 Gate solder bar is under this corner Die is placed into pocket solder bar side down (face side down) EPC2019 (note 1) Dimension (mm) target min Die orientation dot max 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2019 Die orientation dot Gate Pad bump is under this corner YYYY ZZZZ Part Number EPC2019 EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 2019 YYYY ZZZZ | 5 eGaN(R) FET DATASHEET EPC2019 A f X3 DIE OUTLINE DIM A B c d e f g h i k Solder Bar View 5 c 4 1 7 g X2 g X4 100 20 (685) Side View Seating plane 815 Max e B 6 3 h d 2 MIN MICROMETERS Nominal MAX 2736 920 697 247 168 245 600 450 235 2766 950 700 250 183 250 600 450 250 2796 980 703 253 198 255 600 450 265 Pad no.1 is Gate; Pad no. 3, 5 are Drain; Pad no. 2, 4, 6 are Source; Pad no. 7 is Substrate.* *Substrate pin should be connected to Source RECOMMENDED LAND PATTERN 600 X2 1 7 680 3 4 5 450 X2 230 X4 The land pattern is solder mask defined. Copper is larger than the solder mask opening. Solder mask is 10 m smaller per side than bump. 2766 600 X4 950 (measurements in m) 2 6 X4 230 X3 230 Pad no. 1 is Gate Pad no. 3, 5 are Drain Pad no. 2, 4, 6 are Source Pad no. 7 is Substrate* *Substrate pin should be connected to Source RECOMMENDED STENCIL DRAWING 600 X4 600 X2 7 3 4 Intended for use with SAC305 Type 3 solder, reference 88.5% metals content 6 2 X4 230 5 450 X2 1 680 230 X4 Recommended stencil should be 4 mil (100 m) thick, must be laser cut , opening per drawing. The corner has a radius of R60. 2766 950 (units in m) X3 230 Additional assembly resources available at http://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN(R) is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | Information subject to change without notice. revised May, 2019 | 6