eGaN® FET DATASHEET
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1
EPC2019
EPC2019 – Enhancement Mode Power Transistor
VDS, 200 V
RDS(on) , 50 mW
ID , 8.5 A
EPC2019 eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• High Speed DC-DC conversion
• Class-D Audio
• High Frequency Hard-Switching and
Soft-Switching Circuits
Benets
• Ultra High Eciency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
G
D
S
HAL
www.epc-co.com/epc/Products/eGaNFETs/EPC2019.aspx
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally
high electron mobility and low temperature coecient allows very low RDS(on), while its lateral
device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end
result is a device that can handle tasks where very high switching frequency, and low on-time are
benecial as well as those where on-state losses dominate.
Maximum Ratings
PARAMETER VALUE UNIT
VDS Drain-to-Source Voltage (Continuous) 200 V
ID
Continuous (TA = 25˚C, RθJA = 18°C/W) 8.5 A
Pulsed (25°C, TPULSE = 300 µs) 42
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature -40 to 150 °C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC
Thermal Resistance, Junction to Case
2.7
°C/W RθJB
Thermal Resistance, Junction to Board
7.5
RθJA
Thermal Resistance, Junction to Ambient (Note 1)
72
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 μA 200 V
IDSS Drain-Source Leakage VGS = 160 V, VDS = 0 V 20 100 µA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.8 2.5 mA
Gate-to-Source Reverse Leakage VGS = -4 V 20 100 µA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 1.5 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 7 A 3.6 50 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V
All measurements were done with substrate connected to source.
eGaN® FET DATASHEET EPC2019
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40
35
30
25
20
15
10
5
0
0 1 2 3 4 5 6
Figure 1: Typical Output Characteristics at 25°C
ID – Drain Current (A)
VDS – Drain-to-Source Voltage (V)
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
120
100
80
60
40
20
0
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 4 A
ID = 8 A
ID = 12 A
ID = 24 A
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
Figure 2: Transfer Characteristics
25˚C
125˚C
VDS = 6 V
40
35
30
25
20
15
10
5
0
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
120
100
80
60
40
20
0
Figure 4: RDS(on) vs. VGS for Various Temperatures
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0
25˚C
125˚C
ID = 7 A
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance
VGS = 100 V, VDS = 0 V
200 270
pFCOSS Output Capacitance 110 150
CRSS Reverse Transfer Capacitance 0.7 1
RGGate Resistance 0.4 Ω
QGTotal Gate Charge VDS = 100 V, VGS = 5 V, ID = 7 A 1.8 2.5
nC
QGS Gate-to-Source Charge
VDS = 100 V, ID = 7 A
0.6
QGD Gate-to-Drain Charge 0.35 0.6
QG(TH) Gate Charge at Threshold 0.4
QOSS Output Charge VDS = 100 V, VDS = 0 V 18 23
QRR Source-Drain Recovery Charge 0
All measurements were done with substrate connected to source.
eGaN® FET DATASHEET EPC2019
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All measurements were done with substrate shortened to source.
Capacitance (pF)
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
1000
100
10
1
0.1
0 50 100 150 200
ISD – Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 7: Reverse Drain-Source Characteristics
0
2
4
6
8
10
12
14
16
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4 .0 4.5 5.0
25˚C
125˚C
Figure 9: Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage (V)
1.4
1.3
1.2
1.0
1.1
0.9
0.8
0.7
0.6 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 1.5 mA
Capacitance (pF)
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
400
350
300
250
200
150
100
50
0
0 50 100 150 200
5
4
3
2
1
0
0 0.5 1.0 1.5 2.0
Figure 6: Gate Charge
VGS – Gate-to-Source Voltage (V)
QG – Gate Charge (nC)
ID = 7 A
VDS = 100 V
Figure 8: Normalized On-State Resistance vs. Temperature
ID = 7 A
VGS = 5 V
Normalized On-State Resistance R
DS(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.8 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
eGaN® FET DATASHEET EPC2019
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Figure 11: Transient Thermal Response Curves
Junction-to-Board
tp, Rectangular Pulse Duration, seconds
Duty Cycle:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
0.5
0.1
0.05
0.02
0.01
Single Pulse
ZθJB
, Normalized Thermal Impedance
10-4
10-5 10-3 10-2 10-1 1 10+1
1
0.1
0.01
0.001
Junction-to-Case
tp, Rectangular Pulse Duration, seconds
Duty Cycle:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
ZθJC
, Normalized Thermal Impedance
10-5
10-6 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
IG – Gate Current (mA)
VGS – Gate-to-Source Voltage (V)
Figure 10: Gate Leakage Current
25˚C
125˚C
0
0
1
2
3
4
5
6
1 2 3 4 5 6
eGaN® FET DATASHEET EPC2019
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2019
YYYY
ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC2019 2019 YYYY ZZZZ
DIE MARKINGS
TAPE AND REEL CONFIGURATION
4 mm pitch, 8 mm wide tape on 7” reel
7” reel
a
d e f g
c
b
EPC2019 (note 1)
2019
YYYY
ZZZZ
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (see note) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (see note) 2.00 1.95 2.05
g 1.5 1.5 1.6
Note 1: MSL 1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
Loaded Tape Feed Direction
Figure 12: Safe Operating Area
0.1
1
10
100
0.1 1 10 100 1000
ID – Drain Current (A)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
TJ = Max Rated, TC = +25°C, Single Pulse
Pulse Width
100 ms
10 ms
1 ms
100 µs
10 µs
eGaN® FET DATASHEET EPC2019
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DIE OUTLINE
Solder Bar View
Side View
1
2 6
7
43 5
A
e g g
B
c
d
X2
X4
f
X3
k
h
815 Max
100 ± 20
Seating plane
(685)
DIM MIN Nominal MAX
A2736 2766 2796
B920 950 980
c697 700 703
d247 250 253
e168 183 198
f245 250 255
g600 600 600
h450 450 450
i235 250 265
MICROMETERS
Pad no.1 is Gate;
Pad no. 3, 5 are Drain;
Pad no. 2, 4, 6 are Source;
Pad no. 7 is Substrate.*
*Substrate pin should be connected to Source
Pad no. 1 is Gate
Pad no. 3, 5 are Drain
Pad no. 2, 4, 6 are Source
Pad no. 7 is Substrate*
*Substrate pin should be connected to Source
2
1 7
6
43 5
230
230
X3
230
X4
X4
680
2766
950
600
X2
600
X4
450
X2
The land pattern is solder mask dened.
Copper is larger than the solder mask opening.
Solder mask is 10 µm smaller per side than bump.
RECOMMENDED
LAND PATTERN
(measurements in µm)
Ecient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Ecient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
RECOMMENDED
STENCIL DRAWING
(units in µm)
Recommended stencil should be 4 mil (100 μm)
thick, must be laser cut , opening per drawing.
The corner has a radius of R60.
Intended for use with SAC305 Type 3 solder,
reference 88.5% metals content
Additional assembly resources available at
http://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
230
230
X3
230
X4
X4
680
2766
950
600
X2
600
X4
450
X2
2
1 7
6
43 5
Information subject to
change without notice.
revised May, 2019