HY57V643220D(L/S)T(P)-6(I) - Hynix Semiconductor, Inc.

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.3 / Sep. 2004 1

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

Document Title

4Bank x 512K x 32bits Synchronous DRAM

Revision History

Revision

No. History Draft Date Remark

0.1 Initial Draft June. 2004 Preliminary

0.2 Removed Preliminary July 2004

0.3

1. Updated Output Load Capacitance for Access Time Measurement CL = 30pF in

AC OPERATING TEST CONDITION

2. Updated the tolerance zone of the leads and the description of the package type

in PACKAGE DIMENSION

Sep. 2004

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.3 / Sep. 2004 2

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

DESCRIPTION

The Hynix HY57V643220D(L/S)T(P)-xI series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications

which require wide data I/O and high bandwidth. HY57V643220D(L/S)T(P)-xI is organized as 4banks of 524,228x32.

HY57V643220D(L/S)T(P)-xI is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs

are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All

input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)

FEATURES

ORDERING INFORMATION

Note

1. HY57V643220DT(P)-xI Series : Normal Power

2. HY57V643220DLT(P)-xI Series : Low Power

3. HY57V643220DST(P)-xI Series : Super Low Power

4. HY57V643220D(L/S)T-xI Series : Leaded

5. HY57V643220D(L/S)TP-xI Series : Lead Free

6. I : Industrial Temperature (-40oC ~ 85oC)

Part No. Clock

Frequency Organization Interface Package

HY57V643220D(L/S)T(P)-45I6) 222MHz

4Banks x 512Kbits x32 LVTTL 86pin TSOP-II

HY57V643220D(L/S)T(P)-5I6) 200MHz

HY57V643220D(L/S)T(P)-55I6) 183MHz

HY57V643220D(L/S)T(P)-6I6) 166MHz

HY57V643220D(L/S)T(P)-7I6) 143MHz

• Voltage : VDD, VDDQ 3.3V supply voltage

• All device pins are compatible with LVTTL interface

• JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin

pitch

• All inputs and outputs referenced to positive edge of sys-

tem clock

• Data mask function by DQM 0, 1, 2 and DQM 3

• Internal four banks operation

• Auto refresh and self refresh

• 4096 Refresh cycles / 64ms

• Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

• Programmable CAS Latency ; 2, 3 Clocks

• Burst Read Single Write operation

Rev. 0.3 / Sep. 2004 3

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

86PIN TSOP II CONFIGURATION

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

DQM1

CLK

CKE

DQM3

VSS

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

VSSQ

DQ24

VSS

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

DQM0

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

DQM2

VDD

DQ16

VSSQ

DQ17

DQ18

VDDQ

DQ19

DQ20

VSSQ

DQ21

DQ22

VDDQ

DQ23

VDD

86Pin TSOP II

400Mil x 875mil

0.5mm Pin Pitch

Rev. 0.3 / Sep. 2004 4

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

Pin FUNCTION DESCRIPTIONS

Pin Pin Name DESCRIPTION

CLK Clock The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK.

CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CS Chip Select Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1 Bank Address Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

A0 ~ A10 Address Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

RAS, CAS, WE

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin

VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers

VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

Rev. 0.3 / Sep. 2004 5

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

FUNCTIONAL BLOCK DIAGRAM

512Kbit x 4banks x 32 I/O Synchronous DRAM

Internal Row

Counter

Column

Pre

Decoder

Column Add

Counter

Self refresh

logic & timer

Sense AMP & I/O Gate

I/O Buffer & Logic

Address

Counter

Mode Register

State Machine Address Buffers

Bank Select

Column Active

Row Active

CAS Latency

CLK

CKE

RAS

CAS

DQM0~3

BA1

BA0

A10

Row

Pre

Decoder

Refresh

DQ0

DQ31

X-Decoder

Y-Decoder

512Kx32 BANK 0

512Kx32 BANK 1

512Kx32 BANK 2

512Kx32 BANK 3

Memory

Cell

Array

Data Out Control

Pipe Line

Control

Rev. 0.3 / Sep. 2004 6

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

BASIC FUNCTIONAL DESCRIPTION

Mode Register

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0000 OP Code 00 CAS Latency BT Burst Length

OP Code

A9 Write Mode

0Burst Read and Burst Write

1 Burst Read and Single Write

Burst Type

A3 Burst Type

0Sequential

1Interleave

Burst Length

A2 A1 A0 Burst Length

A3 = 0 A3=1

00 0 1 1

00 1 2 2

01 0 4 4

01 1 8 8

1 0 0 Reserved Reserved

1 0 1 Reserved Reserved

1 1 0 Reserved Reserved

1 1 1 Full Page Reserved

CAS Latency

A6 A5 A4 CAS Latency

0 0 0 R e s e r v e d

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 Reserved

1 0 1 R e s e r v e d

1 1 0 R e s e r v e d

1 1 1 Reserved

Rev. 0.3 / Sep. 2004 7

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

ABSOLUTE MAXIMUM RATING

DC OPERATING CONDITION (TA= -40 to 85oC )

Note : 1. All voltages are referenced to VSS = 0V

2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration

AC OPERATING TEST CONDITION (TA= -40 to 85 oC, VDD=3.3±0.3V, VSS=0V)

CAPACITANCE (TA= -40 to 85 oC, f=1MHz, VDD=3.3V)

Parameter Symbol Rating Unit

Ambient Temperature TA -40 ~ 85 oC

Storage Temperature TSTG -55 ~ 125 oC

Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD relative to VSS VDD -1.0 ~ 4.6 V

Voltage on VDDQ relative to VSS VDDQ -1.0 ~ 4.6 V

Short Circuit Output Current IOS 50 mA

Power Dissipation PD 1 W

Soldering Temperature . Time TSOLDER 260 . 10 oC . Sec

Parameter Symbol Min Typ Max Unit Note

Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1

Input High Voltage VIH 2.0 3.3 VDDQ+0.3 V 1, 2

Input Low Voltage VIL -0.3 - 0.8 V 1, 3

Parameter Symbol Value Unit Note

AC Input High/Low Level Voltage VIH / VIL 2.4/0.4 V

Input Timing Measurement Reference Level Voltage Vtrip 1.4 V

Input Rise/Fall Time tR / tF 1 ns

Output Timing Measurement Reference Level Voltage Voutref 1.4 V

Output Load Capacitance for Access Time Measurement CL 30 pF

Parameter Pin Symbol Min Max Unit

Input capacitance

CLK CI1 2.5 3.5 pF

A0 ~ A10, BA0, BA1, CKE, CS, RAS, CAS, WE,

DQM 0~3 CI2 2.5 3.8 pF

Data input / output capacitance DQ0 ~ DQ31 CI/O 4 6.5 pF

Rev. 0.3 / Sep. 2004 8

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

Note 1.

DC CHARACTERRISTICS I (TA= -40 to 85oC)

Note :

1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V

2. DOUT is disabled, VOUT=0 to 3.6

Parameter Symbol Min Max Unit Note

Input Leakage Current ILI -1 1 uA 1

Output Leakage Current ILO -1 1 uA 2

Output High Voltage VOH 2.4 - V IOH = -2mA

Output Low Voltage VOL - 0.4 V IOL = +2mA

Vtt=1.4V

RT=500 Ω

30pF

Output

DC Output Load Circuit AC Output Load Circuit

Vtt=1.4V

RT=50 Ω

30pF

Output Z0 = 50Ω

Rev. 0.3 / Sep. 2004 9

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

DC CHARACTERISTICS II (TA= -40 to 85oC)

Note :

1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3. HY57V643220DT(P)-xI Series : Normal Power

4. HY57V643220DLT(P)-xI Series : Low Power

5. HY57V643220DST(P)-xI Series : Super Low Power

Parameter Sym-

bol Test Condition

Speed

Unit Note

45 555 6 7

Operating Current IDD1 Burst length=1, One bank active

tRC ≥ tRC(min), IOL=0mA 220 200 190 180 170 mA 1

Precharge Standby Current in

Power Down Mode

IDD2P CKE ≤ VIL(max), tCK = 15ns 2 mA

IDD2PS CKE ≤ VIL(max), tCK = ∞ 2mA

Precharge Standby Current

in Non Power Down Mode

IDD2N

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns

Input signals are changed one time dur-

ing 2clks.

All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD2NS CKE ≥ VIH(min), tCK = ∞

Input signals are stable. 12

Active Standby Current

in Power Down Mode

IDD3P CKE ≤ VIL(max), tCK = 15ns 3

IDD3PS CKE ≤ VIL(max), tCK = ∞ 3

Active Standby Current

in Non Power Down Mode

IDD3N

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns

Input signals are changed one time dur-

ing 2clks.

All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD3NS CKE ≥ VIH(min), tCK = ∞

Input signals are stable. 30

Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA

All banks active CL=3 290 280 260 240 210 mA 1

Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 260 250 235 220 210 mA 2

Self Refresh Current IDD6 CKE ≤ 0.2V

Normal 2 mA 3

Low Power 0.8 mA 4

Super Low

Power 450 uA 5

Rev. 0.3 / Sep. 2004 10

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

Note :

1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.

2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 2.0V. If tR > 1ns,

then (tR/2-0.5)ns should be added to the parameter.

Parameter Symbol

45 555 6 7

Unit Note

Min Max Min Max Min Max Min Max Min Max

System Clock

Cycle Time

CAS

Latency=3 tCK3 4.5

1000

5.0

1000

5.5

1000

6.0

1000

7.0

1000

CAS

Latency=2 tCK2 10 10 10 10 10 ns

Clock High Pulse Width tCHW 1.75 - 2.0 - 2.25 - 2.5 - 3.0 - ns 1

Clock Low Pulse Width tCLW 1.75 - 2.0 - 2.25 - 2.5 - 3.0 - ns 1

Access Time

From Clock

CAS

Latency=3 tAC3 -4.5-4.5-5.0-5.5-5.5ns

CAS

Latency=2 tAC2 -6.0-6.0-6.0-6.0-6.0ns

Data-out Hold Time tOH 1.5-1.5-2.0-2.0-2.0- ns

Data-Input Setup Time tDS 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - ns 1

Data-Input Hold Time tDH 0.8-1.0-1.0-1.0-1.0- ns1

Address Setup Time tAS 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - ns 1

Address Hold Time tAH 0.8-1.0-1.0-1.0-1.0- ns1

CKE Setup Time tCKS 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - ns 1

CKE Hold Time tCKH 0.8 - 1.0 - 1.0 - 1.0 - 1.0 - ns 1

Command Setup Time tCS 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - ns 1

Command Hold Time tCH 0.8-1.0-1.0-1.0-1.0- ns1

CLK to Data Output in

Low-Z Time tOLZ 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - ns

CLK to

Data Output

in High-Z Time

CAS

Latency=3 tOHZ3 -4.0-4.5-5.0-5.5-5.5ns

CAS

Latency=2 tOHZ2 -6.0-6.0-6.0-6.0-6.0ns

Rev. 0.3 / Sep. 2004 11

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

Note :

1. A new command can be given tRC after self refresh exit.

Parameter Sym-

bol

45 555 6 7

Unit Note

Min Max Min Max Min Max Min Max Min Max

RAS Cycle Time Operation tRC 58.5 - 55 - 55 - 60 - 63 - ns

RAS Cycle Time Auto Refresh tRRC 58.5 - 55 - 55 - 60 - 63 - ns

RAS to CAS Delay tRCD 18 - 15 - 16.5 - 18 - 20 - ns

RAS Active Time tRAS 40.5 100K 38.7 100K 38.7 100K 42 100K 42 100K ns

RAS Precharge Time tRP 18 - 15 - 16.5 - 18 - 20 - ns

RAS to RAS Bank Active

Delay tRRD 9 -10-11-12-14-ns

CAS to CAS Delay tCCD1-1-1-1-1-CLK

Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - 0 - CLK

Data-in to Precharge Command tDPL TBD - TBD - TBD - 1 - 1 - CLK

Data-In to Active Command tDAL tDPL + tRP

DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - CLK

DQM to Data-In Mask tDQM 0 - 0 - 0 - 0 - 0 - CLK

MRS to New Command tMRD2-2-2-2-2-CLK

Precharge to Data

Output High-Z

CAS

Latency=3 tPROZ33-3-3-3-3-CLK

CAS

Latency=2 tPROZ2--2-2-2-2-CLK

Power Down Exit Time tDPE 1-1-1-1-1-CLK

Self Refresh Exit Time tSRE 1-1-1-1-1-CLK1

Refresh Time tREF -64-64-64-64-64ms

Rev. 0.3 / Sep. 2004 12

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

COMMAND TRUTH TABLE

Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/AP BA Note

Mode Register Set H X L L L L X OP code

No Operation H X

HX XX

LHHH

Bank Active H X L L H H X RA V

Read

HXLHLHXCA

Read with Autoprecharge H

Write

HXLHLLXCA

Write with Autoprecharge H

Precharge All Banks

HXLLHLXX

Precharge selected Bank LV

Burst Stop H X L H H L X X

DQM H X V X

Auto Refresh H H L L L H X X

Burst-Read-Single-WRITE H X L L L L X A9 ball High

(Other balls OP code)

MRS

Mode

Self Refresh1

Entry H L L L L H X

Exit L H

HX XX

LHHH

Precharge

power down

Entry H L

HX XX

LHHH

Exit L H

HX XX

LHHH

Clock

Suspend

Entry H L

HX XX

XLVVV

Exit L H X X

Rev. 0.3 / Sep. 2004 13

HY57V643220D(L/S)T(P)-xI Series

4Banks x 512K x 32bits Synchronous DRAM

PACKAGE INFORMATION

JEDEC STANDARD 400mil 86pin TSOP-II with 0.5mm pin pitch

11.938(0.4700)

11.735(0.4620)

10.262(0.4040)

10.058(0.3960)

22.327(0.8790)

22.149(0.8720)

5deg

0deg 0.597(0.0235)

0.406(0.0160)

0.210(0.0083)

0.120(0.0047)

1.194(0.0470)

0.991(0.0390)

Unit : mm(inch)

0.150(0.0059)

0.050(0.0020)

0.50(0.0197) 0.21(0.008)

0.18(0.007)

0.05

0.05 M