54ACT112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’ACT112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trigger-
ing occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change
when the clock is in either state without affecting the flip-flop,
provided that they are in the desired state during the recom-
mended setup and hold times relative to the falling edge of
the clock. A LOW signal on S
D
or C
D
prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW sig-
nals on S
D
and C
D
force both Q and Q HIGH.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n’ACT112 has TTL-compatible inputs
nOutputs source/sink 24 mA
nStandard Microcircuit Drawing (SMD) 5962-8995001
Connection Diagram Pin Descriptions
Pin Names Description
J
1
,J
2
,K
1
,K
2
Data Inputs
CP
1
,CP
2
Clock Pulse Inputs
(Active Falling Edge)
C
D1
,C
D2
Direct Clear Inputs (Active LOW)
S
D1
,S
D2
Direct Set Inputs (Active LOW)
Q
1
,Q
2
,Q
1
,Q
2
Outputs
FACT™is a trademark of Fairchild Semiconductor Corporation.
Pin Assigment for
DIP and Flatpack
DS100976-3
Pin Assigment
for LCC
DS100976-5
September 1998
54ACT112 Dual JK Negative Edge-Triggered Flip-Flop
© 1998 National Semiconductor Corporation DS100976 www.national.com
Logic Symbols
Truth Table
Inputs Outputs
S
D
C
D
CP JKQ Q
LHXXXHL
HLXXXLH
LLXXXHH
HHMhhQ
0
Q
0
HHMlhLH
HHMhlHL
HHMllQ
0
Q
0
H (h) =HIGH Voltage Level
L (l) =LOW Voltage Level
X=Immaterial
M=HIGH-to-LOW Clock Transition
Q0(Q0)=Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock
transition.
DS100976-1
IEEE/IEC
DS100976-4
DS100976-2
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Logic Diagram (One Half Shown)
DS100976-6
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=−0.5V −20 mA
V
I
=V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=−0.5V −20 mA
V
O
=V
CC
+ O.5 +20 mA
DC Output Voltage (V
O
) −0.5V to V
CC
+0.5V
DC Output Source
or Sink Current (I
O
)±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)±50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (V
O
) 0VtoV
CC
Operating Temperature (T
A
) −55˚C to +125˚C
Minimum Input Edge Rate (∆V/∆t) 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Fairchild does not recom-
mend operation of FACT™circuits outside databook specifications.
DC Characteristics for ’ACT Family Devices
Symbol Parameter VCC TA=−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
VIH Minimum High Level 4.5 2.0 V VOUT =0.1V
Input Voltage 5.5 2.0 or VCC − 0.1V
VIL Maximum Low Level 4.5 0.8 V VOUT =0.1V
Input Voltage 5.5 0.8 or VCC − 0.1V
VOH Minimum High Level 4.5 4.4 V IOUT =−50 µA
Output Voltage 5.5 5.4 VIN =VIL or VIH
4.5 3.70 V IOH =−24 mA
5.5 4.70 IOH =−24 mA
(Note 2)
VOL Maximum Low Level 4.5 0.1 V IOUT =50 µA
Output Voltage 5.5 0.1 VIN =VIL or VIH
4.5 0.5 V IOL =24 MA
5.5 0.5 IOL =24 mA
(Note 2)
IIN Maximum Input Leakage
Current 5.5 ±1.0 µA VI=VCC, GND
ICCT Maximum ICC/Input 5.5 1.6 mA VI=VCC − 2.1V
IOLD Minimum Dynamic 5.5 50 mA VOLD =1.65V Max
IOHD Output Current(Note 3) 5.5 −50 mA VOHD =3.85V Min
ICC Maximum Quiescent
Supply Current 5.5 80.0 µA VIN =VCC or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
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AC Electrical Characteristics for ’ACT Family Devices
Symbol Parameter VCC TA=−55˚C to +125˚C Units
(V) CL=50 pF
(Note
4) Min Max
fmax Maximum Clock 5.0 80 MHz
Frequency
tPLH Propagation Delay 5.0 1.0 14.0 ns
CPnto Qnor Qn
tPHL Propagation Delay 5.0 1.0 14.0 ns
CPnto Qnor Qn
tPLH Propagation Delay 5.0 1.0 13.5 ns
CDn or SDn to Qnor Qn
tPHL Propagation Delay 5.0 1.0 13.5 ns
CDn or SDn to Qnor Qn
Note 4: Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements:
Symbol Parameter VCC TA=−55˚C to +125˚C Units
(V) CL=50 pF
(Note 5) Guaranteed Minimum
tSSetup Time, HIGH or
LOW 5.0 8.0 ns
Jnor Knto CPn
tHHold Time, HIGH or
LOW 5.0 1.5 ns
Jnor Knto CPn
tWPulse Width 5.0 5.0 ns
CPnor CDn or SDn
trec Recovery Time 5.0 3.0 ns
CDn or SDn to CPn
Note 5: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol Parameter Max Units Conditions
C
IN
Input Capacitance 10.0 pF V
CC
=OPEN
C
PD
Power Dissipation Capacitance 60 pF V
CC
=5.0V
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Ceramic Dual-in-line
Package Number J16A
16-Lead Cerpack
Package Number W16A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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20-Lead Ceramic Leadless Chip Carrier
Package Number E20A
54ACT112 Dual JK Negative Edge-Triggered Flip-Flop
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
