DS2165/DS2165Q DALLAS SEMICONDUCTOR DS2165/DS2165Q 16/24/32Kbps ADPCM Processor FEATURES Compresses/expands 64Kbps PCM voice to/from either 32Kbps, 24Kbps, or 16Kbps Dual, fully independent channel architecture; device can be programmed to perform either: two expansions two compressions one expansion and one compression Interconnects directly to combo-codec devices Input to output delay is less than 375 us Simple serial port used to configure the device Onboard Time Slot Assigner Circuit (TSAC) function allows data to be input/output at various time slots Supports Channel Associated Signaling Each channel can be independently idled or placed into bypass Available hardware mode requires no host processor; ideal for voice storage applications Backward-compatible with the DS2167 ADPCM Processor Chip Single +5V supply; low-power CMOS technology @ Available in 24-pin DIP and 28-pin PLCC DESCRIPTION The DS2165 ADPCM Processor Chip is a dedicated Digital Signal Processing (DSP) chip that has been opti- mized to perform Adaptive Ditterential Pulse Code Mod- ulation (ADPCM) speech compression at three different tates. The chip can be programmed to compress (ex- pand) 64Kbps voice data down to (up from) either 32Kbps, 24Kbps, or 16Kbps. The compression to 32Kbps follows the algorithm specified by CCITT Rec- ommendation G.721 (July 1986) and ANSI document PIN ASSIGNMENT rst (] 4 24 [] VDD Tmo [] 2 23 [] YIN Ti? []3 22 [J CLKY Ao [] 4 21 [] FSY Ai (| 5 20 1] YouT a2 (]6 19 [| cs A3 (| 7 18 F SDI aaf]s 71 seu As (| 9 16 xouT sps (J 10 57 esx mci (] 11 141] CLKx vss [] 12 131] xin 24-Pin DIP (600 MIL) 28-Pin PLCC A 3-vot Operator Vers o7 is Ava lable 0S2165QL; T1.301 (April 1987). The compression to 24Kbps foi- lows ANSI document T1.303. The compression to 16Kbps follows a proprietary algorithm developed by Dallas Semiconductor. The DS2165 can switch com- pression algorithms on-the-fly. This allows the user to make maximum use of the available bandwidth on a dy- namic basis. 041295 118 58 Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding Patents and other intellectual nights, please refer to Dallas Semiconductor data books.DS2165/DS2165Q OVERVIEW The DS2165 contains three major functional blocks: a high performance (10 MIPS) DSP engine, two indepen- dent PCM interfaces (X and Y) which connect directly to serial Time Division Multiplexed (TDM) backplanes, and a serial port that can configure the device on-the-fly via an external controller. A 10 MHz master clock is re- quired by the DSP engine. The DS2165 can be confi- gured to perform either two expansions, two compres- sions, or one expansion and one compression. The PCM/ADPCM data interfaces support data rates from 256 KHz to 4.096 MHz. Typically, the PCM data rates will be 1.544 MHz for w-law and 2.048 MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream during a user-programmed input time slot, processes the data and outputs the re- sult during a user-programmed output time slot. Each PCM interface has a control register which speci- fies functional characteristics (compress, expand, by- pass, and idle), data format (-law or A-law), and algo- rithm reset control. With the SPS pin strapped high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a novel ad- dressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system-level in- terconnect. With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control register bits to some of the address and serial port pins. Under the hardware mode, no external host controller is required and all PCM/ADPCM input and output time slots default to tire slot 0. HARDWARE RESET RST allows the user to reset both channel algorithms and the contents of the internal registers. This pin must be held low for at least 1 ms on system power-up after the master clock is stable to ensure that that the device has initialized properly. RST should also be asserted when changing to or from the hardware mode. RST clears all bits of the Control Register for both channels except the IPD bits; the IPD bits for both channels are set to 1. SOFTWARE MODE Tying SPS high enables the software mode. In this mode, an external host controller writes configuration data to the DS2165 via the serial port through inputs SCLK, SDI, and GS. (See Figure 2.) Each write to the DS2165 is either a 2-byte write or a 4-byte write. A 2- byte write consists of the Address/Command Byte (ACB), followed by a byte to configure the Control Reg- ister (CR) for either the X or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then one byte to set the input time slot and another byte to set the output time slot. ADDRESS/COMMAND BYTE In the software mode, the address/command byte is the first byte written to the serial port; it identifies which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must match that at inputs AQ to AS. If no match occurs, the device ignores the following configuration data. If an address match oc- curs, the next three bytes written are accepted as con- trol, input and output time slot data. Bit ACB.6 deter- mines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs are tristated during reg- ister updates. CONTROL REGISTER The controi register establishes idle, algorithm reset, bypass, data format and channel coding for the selected channel. The X and Y side PCM interfaces can be independently disabled (output 3-stated) via IPD. When IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port must not be operated faster than 39 KHz. ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST will be cleared by the device when the algorithm reset is complete. 59 041295 2/18DS2165/DS2165Q PIN DESCRIPTION Table 4 PIN SYMBOL TYPE DESCRIPTION 1 RST I Reset. A high-iow-high transition resets the algorithm. The device should be reset on power up and when changing to or from the hardware mode. 2 TMO \ Test Modes 0 and 1. Tie to Vss for normal operation. 3 TM1 4 AO Address Select. AO = LSB; A5 = MSB Must match address/command 5 Al word to enable the serial port. 6 A2 7 A3 8 A4 9 A5 10 SPS I Serial Port Select. Tie to Vp to select the serial port; tie to Vgs to select the hardware mode. 1 MCLK | Master Clock. 10 MHz clock for the ADPCM processing engine; may be asynchronous to SCLK, CLKX, and CLKY. 12 Vss - Slgnal Ground. 0.0 volts. 13 XIN | X Data In. Sampled on falling edge of CLKX during selected time slots. 14 CLKX | X Data Clock. Data clock for the X side PCM interface; must be synchro- nous with FSX. 15 FSX I X Frame Sync. 8 KHz frame sync for the X side PCM interface. 16 XOUT oO X Data Output. Updated on rising edge of CLKX during selected time slots. 17 SCLK I Serial Data Clock. Used to write to the serial port registers. 18 SDI | Serial Data In. Data for onboard control registers; sampled on the rising edge of SCLK. LSB sent first. 19 cs | Chip Select. Must be low to write to the serial port. 20 YOUT oO Y Data Output. Updated on rising edge of CLKY during selected time slots. 21 FSY I Y Frame Sync. 8 KHz frame sync for the Y side POM inierface. 22 CLKY ! Y Data Clock. Data clock for the Y side PCM interface; must be synchro- nous with FSY. 23 YIN I Y Data In. Sampled on falling edge of CLKY during selected time slots. [ 24 Vop - Positive Supply. 5.0 volts (or 3.0 volts for DS2165QL). 041295 3/18 60DS2165/DS2165Q DS2165 BLOCK DIAGRAM Figure 1 FSX ~ X SIDE PCM/ADPCM on DATA INTERFACE XOUT + J t MCLK SCLK >| sPs > cs > SERIAL PORT CONTROL sDI * HARDWARE MODE LOGIC AQ-AS 7 FSY ___| CLKY Y SIDE PCM/ADPCM DATA INTERFACE ft} ADPCM PROCESSING ENGINE rt YIN ~| YOUT _ Vop RST ~ Two *>| RESET AND TEST LOGIC 1 Vss TT SERIAL PORT WRITE Figure 2 | [ JUUUUUUUUUU UU UU UL Ho Xai re na X me KX A5 XUV 0 YendXerien2 Xena ena ERE NORE KORY, \ ADDRESS/COMMAND a CONTROL NOTE: 1. A 2-byte write is shown. The bypass feature is enabled when BYP is set and IPD A-law (U/A = 0) and y-law (U/A = 1) PCM coding is inde- is cleared. During bypass, no expansion or compres- pendently selected for the X and Y channels via CR.2. If sion occurs. Bypass operates on bytewide (8 bits) slots BYP and IPD are cleared, then CP/EX determines if the when CP/EX is set and on nibble-wide (4 bits) slots input data is to be compressed or expanded. when CP/EX is cleared. 041295 4/18 61DS2165/DS2165Q ADDRESS/COMMAND BYTE Figure 3 (MSB) (LSB) - x A5 Ad A3 A2 at | ao SYMBOL. POSITION NAME AND DESCRIPTION - ACB.7 Reserved; must be 0 for proper operation XY ACB.6 X/Y Channel Select 0 = update channel Y characteristics 1 = update channel X characteristics A5 ACB.5 MSB of Device Address A4 ACB.4 A3 ACB.3 A2 ACB.2 Al ACB.1 AO ACB.0 LSB of Device Address CONTROL REGISTER Figure 4 (MSB) (LSB) ASO ASI IPD ALRST BYP uA | ase | cPeX | SYMBOL POSITION NAME AND DESCRIPTION ASO CR.7 Algorithm Select 0. See Table 2. AS1 CR.6 Algorithm Select 1. See Table 2. IPD CR.5 idle and Power Down. 0 = channel enabled 1 = channel disabled (output 3-stated) ALRST CR.4 Algorithm Reset. 0 = normal operation 1 = reset algorithm for selected channel BYP CR.3 Bypass. 0 = normal operation 1 = bypass selected channel U/A CR.2 Data Format. Q = Alaw 1 =pu-law AS2 CR.1 Algorithm Select 2. See Table 2. CP/EX CR.0 Channel Coding. 0 = expand (decode) selected channel 1 = compress (encode) selected channel 041295 5/18 62ALGORITHM SELECT BITS Table 2 DS2165/DS2165Q ALGORITHM SELECTED AS2 AS1 ASO 64Kbps to/from 32Kbps 0 0 0 64Kbps to/from 24Kbps 1 1 1 64Kbps to/from 16Kbps 1 0 1 INPUT TIME SLOT REGISTER Figure 5 (MSB) (LSB) - - D5 D2 D1 DO SYMBOL POSITION NAME AND DESCRIPTION - ITR.7 Reserved; must be 0 for proper operation. - ITR.6 Reserved; must be 0 for proper operation. D5 ITR.5 MSB of input time slot register. D4 ITR.4 D3 ITR.3 D2 ITR.2 D1 ITR.1 DO ITR.O LSB of input time slot register. OUTPUT TIME SLOT REGISTER Figure 6 (MSB) (LSB) - - | mo | b2 pt | sib SYMBOL POSITION NAME AND DESCRIPTION - OTR.7 Reserved; must be 0 for proper operation. - OTR.6 Reserved; must be 0 for proper operation. D5 OTR.5 MSB of output time slot register. D4 OTR.4 D3 OTR.3 D2 OTR.2 D1 OTR.1 DO OTR.O LSB of output time slot register. 63 041295 618DS2165/DS2165Q TIME SLOT ASSIGNMENT/ORGANIZATION Onboard counters establish when PCM and ADPCM VO occurs. The counters are programmed via the time slot registers. Time slot size (number of bits wide) is de- termined by the state of CP/EX. The number of time slots available is determined by both the state of CP/EX and U/A. (See Figures 7 through 10.) For example, if the X channel is set to compress (CPEX = 1) and itis set to DS2165 p-LAW PCM INTERFACE Figure 7 TIME SLOT 0 <._____> TIME w/MESLOTN N expect y-law data (U/A = 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up for 64 4-bit time slots. The time slot organiza- tion is not dependent on which algorithm has been se- lected. NOTE: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX or CLKY after the frame sync. TIME SLOT 31 TIME SLOT 0 IR RTs ATT, CLKX, CLKY sary SL I I 1 XIN, YIN ____DON'T CARE __ ee seooanado% I| DON'T CARE DS2165 p-LAW ADPCM INTERFACE Figure 8 TIME TIME TIME TIME TIME TIME Pane 0 Panne 1 SLOT N SLOT 62 SLOT 63 SLOT 0 A AS co cur ITUITTTUUI Ar/ FSX, rsy_} L I | [eco00" n I II XIN. YIN DON'T CARE DONT CARE { XOUT, YOUT ss 39-STATE | | MSB vw 0 LSB | | 3-STATE 041295 7/18DS2165/D$82165Q DS2165 A-LAW PCM INTERFACE Figure 9 TIME SLOT 0 TIME SLOT N TIME JME SLOT 31 31 TIME SLOT 0 oxcouxy JUVUUUUUUUUU, TCI) Tr FSX, FSY JL I] || PL MSB enw bowen |] OCOQQOH || sono XOUT, YOUT S-STATE vy = (00000cg i| = DS2165 A-LAW ADPCM INTERFACE Figure 10 TIME TIME TIME TIME TIME TIME SLOT 0 SLOT 1 SLOT N SLOT 62 SLOT 63 SLOT 0 @_ > <___ ex our IUUTUTITUIUL ITTTT/ FSX, FSY _f{] | | | i LSB anne /| DONT GARE XOUT, YOUT JTC SSTATE || MSB eee C LSB i 3-STATE MSB XIN, YIN DON'T CARE 041295 8/18 65DS2165/DS2165Q HARDWARE MODE The hardware mode is intended for applications that do not have an external controller available or do not re- quire the extended features offered by the serial port. Tying the SPS pin to Vgs disables the serial port, clears all internal register bits and maps the IPD, U/A, and CP/EX bits for both channels to external bits. (See Table 3.) Inthe hardware mode, both the input and output time slots default to time slot 0. HARDWARE MODE Table 3 PIN # / NAME REG. LOCATION NAME AND DESCRIPTION 4/A0 CP/EX Channel X Coding Configuration (Channel X) 0 = Expand 1 = Compress 5/A1 ASO/AS1/AS2 Algorithm Select (see Table 5) (Channel X & Y) 6/A2 UA Channel X Data Format (Channel X) 0 = A-law 1 =p-law 7/A3 CP/EX Channel Y Coding Configuration (Channel Y) 0 = Expand 1 = Compress 8/A4 AS0/AS1/AS2 Aigorithm Select (see Table 5) (Channel X & Y) 9/A5 U/A Channel Data Format (Channel Y) 0 = A-law 1=p-law 18/SDt IPD Channel Y Idle Select (Channel Y) 0 = Channel active 1 = Channel idle 19/CS IPD Channel X Idle Select (Channel X) 0 = Channel active 1 = Channel idle NOTES: 1. SCLK must be tied to Vgg when the hardware mode is selected. 2. When both channels are idled, power consumption is significantly reduced. 3. The DS2165 will power-up within 800 ms after either channel is returned to active from an idle state. ALGORITHM SELECT FOR HARDWARE MODE Table 4 ALGORITHM CONFIGURATION OF A1 AND A4 64Kbps to/from 32Kbps Tie both A1 and A4 to Vss_ 64Kbps to/from 24Kbps Hold A1 and A4 low during a hardware reset: take both Ai and A4 high after the RST pin has returned high (allow 3 us after RST returns high before taking Ai and A4 high). 64Kbps to/from 16Kbps Tie both A1 and A4 to Vpp. 041295 9/18 66DS2165-DS2165Q DS2165 CONNECTION TO CODEC/FILTER Figure 11 CODEC/FILTER DS2165 VEX. Dx | XIN XOUT;/ TRANSMIT DATA VFX > sx DAY YOUT YIN-# RECEIVE DATA ANALOG INTERFACE LO VFRO MCLKX MCLK K# 10 MHz CLOCK BCLKX m CLKX BCLKR}* | CLKY SPS a FSR >| FSY MCLKR FSX FSX cs 3-WIRE BUS FROM | SCLK \, EXTERNAL CONTROLLER SDI TRANSMIT DATA CLOCK > RECEIVE DATA CLOCK >_____ AQ Al ooo RECEIVE FRAME SYNG A? eerie >----- TRANSMIT FRAME SYNG A3 (ADDRESS-0 SHOWN) TMO A4 T1 RST AS RESET CIRCUITRY (DS1231) NOTE: Suggested Codec/Filters TP305X National Semiconductor ETC505X SGS-Thomson Microelectronics MC1455XX_ ~ Motorola TCM29CXX Texas Instruments HD44238C Hitachi *other generic Codec/Filter devices can be substituted. PCM AND ADPCM INPUT/OUTPUT Since the organization of the input and output time slots on the DS2165 does not depend on the algorithm se- lected, it always assumes that PCM input and output will be in 8-bit bytes and that ADPCM input and output will be in 4-bit bytes. Figure 12 demonstrates how the DS2165 handles the I/O for the three different algo- rithms. In the figure, itis assumed that channel Xis inthe compression mode (CP/EX = 1) and channel Y is in the expansion mode (CP/EX = 0). Also, it is assumed that both the input and output time slots for both channels are set to 0. 67 041295 10/18DS2165/DS2165Q PCM AND ADPCM I/O EXAMPLE Figure 12 CLKX J = LI L| LI LI L rx J L_ MSB LSB xin Z/7/X_ XX XX XK KX MSB LSB 3-STATE xour isexprs) {_ XXX? MSB LSB, 3-STATE XOUT (24KBPS) xX Xx aX SEE NOTE 1 MSB LSB 3-STATE XOUT (16KBPS) 0 0 ov J LILI LIL LU LE LI LU LIU wiv owsrs) Z7Z7X XXX XLTLZII TIT ILILLIL wnveursrs) ZZZZX XX XLT TLL TLL IL. vow exa0sy Z7ZZX XIII ITIL MSB LSB 3-STATE yout {XX XX KKK NOTE: 1. The bit after the LSB in the 24Kbps ADPCM output will only be a 1 when the DS2165 is operated in the soft- ware mode and is programmed to perform 24Kbps compression; in all other configurations, it will be a 0. 041295 11/18 68DS2165/0S2165Q TIME SLOT RESTRICTIONS Under certain conditions, the DS2165 does contain some restrictions on the output time slots that are avail- able. These restrictions are covered in detail in a sepa- rate application note. No restrictions occur if the DS2165 is operated in the hardware mode. INPUT TO OUTPUT DELAY With all three compressions algorithms, the total delay, from the time the PCM data sample is captured by the DS2165 to the time it is output, is always less than 375 is. The exact delay is determined by the input and out- put time slots selected for each channel. CHANNEL ASSOCIATED SIGNALING The DS2165 supports Channel Associated Signaling (CAS) via its ability to automatically change from the 32Kbps compression algorithm to the 24Kbps algo- rithm. If the DS2165 is configured to perform the 32Kbps algorithm, then in both the hardware and software mode, it will sense the frame sync inputs (FSX and FSY) for a double wide frame sync pulse. Whenever the DS2165 receives a double wide pulse, it will automati- cally switch from the 32Kbps algorithm to the 24Kbps al- gorithm. Switching to the 24Kbps algorithm allows the user to insert signaling data into the LSB bit position of the ADPCM output because this bit does not contain any useful speech information. ON-THE-FLY ALGORITHM SELECTION In the software mode, the user can switch between the three available algorithms on-the-fly. That is, the DS2165 does not need to be reset or stopped to make the change from one algorithm to another. The DS2165 reads the Control Register before it starts to process each PCM or ADPCM sample. If the user wishes to switch algorithms, then the Control Register must be up- dated via the serial port before the first input sample to be processed with the new algorithm arrives at either XIN or YIN. The PCM and ACPCM outputs will tristate during register updates. 69 041295 12/18DS2165/DS2165Q ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground -1.0V to +7.0V Operating Temperature 0C to 70C Storage Temperature -55C to +125C Soldering Temperature 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi- mum rating conditions for extended periads of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 Vin 2.0 Vecot0.3 Vv 5 Logic 0 Vit -0.3 +0.8 Vv 5 Supply Vop 45 5.5 Vv 5 Logic 1 Vin 2.2 Voct0.3 Vv 6 Logic 0 Vir -0.3 +0.4 V 6 Supply Vop 2.7 3.6 Vv 6 CAPACITANCE (ta=25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance Cin 5 pF Output Capacitance Cout 10 pF (0C to 70C; Vop=5V + 10%) DC ELECTRICAL CHARACTERISTICS (Vpp=3.0V + 20% 10% for DS2165QL) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current IDpa 20 mA 1,2,5 Active Supply Current IDpDA 12 mA 1,2,6 Idle Supply Current lppPD 1 mA 1,2,3 Input Leakage lt -1.0 +1.0 pA Output Leakage lo -1.0 +1.0 pA 4 Output Current (2.4V) lou -1.0 mA 5 Output Current (0.4V) lot +4.0 mA 5 Output Current (2.2V) lon -0.5 mA 6 Output Current (0.4V) lo. +2.0 mA 6 NOTES: CLKX = CLKY = 1.544 MHz; MCLK = 10 MHz. Outputs open; inputs swinging fuli supply levels. Both channels in idle mode. XOUT and YOUT are 3-stated. Applies only to 5V device. Applies only to 3V device (DS2165QL). anrR wD > 041295 13/18 70DS2165/DS2165Q PCM INTERFACE (0C to 70C; Vpp=5V +10%) AC ELECTRICAL CHARACTERISTICS (Vpp=3.0V + 20% 10% for DS2165QL)} PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CLKX, CLKY Period tpxy 244 3906 ns 1 CLKX, CLKY Pulse Width twxYL 100 ns tWXYH CLKX, CLKY Rise Fall Times taxy 10 20 ns texy Hold Time from CLKX, CLKY tHoLD 0 ns 2 to FSX, FSY Setup Time from FSX, FSY tse 50 ns 2 high to CLKX, CLKY low Hold Time from CLKX, CLKY tue 100 ns 2 low to FSX, FSY low Setup Time for XIN, YIN to tsp 50 ns 2 CLKX, CLKY low Hold Time for XIN, YIN tub 50 ns 2 to CLKX, CLKY low Delay Time from CLKX, tpxyo 10 150 ns 3 CLKY to Valid XOUT, YOUT Delay Time from CLKX, toxyz 20 150 ns 2.3.4 CLKY to XOUT, YOUT 3-stated NOTES: 1. Maximum width of FSX and FSY is one CLKX or CLKY period (except for signaling frames). 2. Measured at Viq = 2.0V, Vi_ = 0.8V, and 10 ns maximum rise and fall times. 3. Load = 150 pF + 2 LSTTL loads. 4. For LSB of PCM or ADPCM byte. MASTER CLOCK/RESET (0C to 70C; Vpp=5V + 10%) AC ELECTRICAL CHARACTERISTICS (Vpp=3-0V + 20% 10% for DS2165QL) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES MCLK Period tpm 100 ns 1 MCLK Pulse Width twMH: 45 50 55 ns twa MCLK Rise/Fall Times tau. tem 10 ns RST Pulse Width tast 1 ms NOTE: 1. MCLK = 10 MHz + 500 ppm 041295 14/18 71DS2165'/DS21650 SERIAL PORT (0C to 70C; Vop=5V + 10%} AC ELECTRICAL CHARACTERISTICS (Vpp=3.0V + 20% 10% for DS2165QL) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES SDI to SCLK Set Up ipo 55 ns 1 SCLK to SDI Hoid tcbH 55 ns 1 SCLK Low Time ter 250 ns 1 SCLK High Time tcH 250 ns 1 SCLK Rise and Fail Time tr. te 100 ns 1 CS to SCLK Setup toc 50 ns 1 SCLK to CS Hold tocH 250 ns 1 CS Inactive Time towH 250 ns 1 SCLK Setup to CS Falling tscc 50 ns 1 NOTE: 4. Measured at Vipy = 2.0V, Vi_ = 0.8V, and 10ns maximum rise and fall times. PCM INTERFACE AC TIMING DIAGRAM Figure 13 < texy _ {HOLD inxy texy i t _ . | WXYH oe TWXYL_ CLKX 2 iF g M f \ CLKY KO KO FSX FSY >| thr FSX FSY be- ts tHE [~* tsp tup XIN wy LLELEEEE EEL ELE _euses * K XOUT 3-STATE C MSB your mse) OX S ~ tpxyo toxyz > 041295 15/18 720S2165/DS21650 MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 14 tru tem _ twMH | twWML _ le ~ MCLK oe TE OE ae tast RST SERIAL PORT AC TIMING DIAGRAM Figure 15 towH oT, tscc _ so IIIT px <TIEXSS >TELL. IcDH NOTE: 1. SCLK may be either high or low when CS is taken low. 041295 16/18 73DS2165/D$2165Q DS2165 16/24/32KBPS ADPCM PROCESSOR 24-PIN DIP Piri Par ES [ues Sain lL PKG 24-PIN DIM MIN MAX AIN. 1.150 1.260 MM 29.21 32.00 BIN. 0.250 0.270 MM 6.35 6.86 CIN. 0.120 0.140 MM 3.05 3.56 DIN. 0.300 0.325 MM 7.62 8.26 EIN. 0.015 0.040 MM 0.38 1.02 FIN. 0.125 0.135 MM 3.18 3.48 GIN. 0.090 0.110 MM 2.23 2.79 HIN 0.320 0.370 MM 8.13 9.40 JIN 0.008 0.012 MM 0.20 0.30 KIN. 0.015 0.022 MM 0.38 0.56 041295 17/18 740S2165/D$21650 DS2165Q 16/24/32KBPS ADPCM PROCESSOR 28-PIN PLCC Pane q q Nq 100 q 4d ont CITtTorecrcrcy CI INCHES DIM MIN MAX A 0.165 0.180 Al 0.090 0.120 A2 0.020 - B 0.026 0.033 B1 0.013 0.021 Cc 0.009 0.012 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E1 0.450 0.456 E2 0.390 0.430 L1 0.060 - N 28 - e1 0.050 BSC CH1 0.042 0.048 o> | |e B u 1 el La 7 This drawing controlled by drawing number 56~G4001-001. 041295 18/18 75