S70FL01GS 1 Gbit (128 Mbyte) MirrorBit(R) Flash Non-Volatile Memory CMOS 3.0 Volt Core Serial Peripheral Interface with Multi-I/O Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S70FL01GS_00 Revision 02 Issue Date April 25, 2013 D a t a S h e e t ( P r e l i m i n a r y ) Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: "This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice." Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: "This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications." Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: "This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur." Questions regarding these document designations may be directed to your local sales office. 2 S70FL01GS S70FL01GS_00_02 April 25, 2013 S70FL01GS 1 Gbit (128 Mbyte) MirrorBit(R) Flash Non-Volatile Memory CMOS 3.0 Volt Core Serial Peripheral Interface with Multi-I/O Data Sheet (Preliminary) Features Serial Peripheral Interface (SPI) Security Features - - - - SPI Clock polarity and phase modes 0 and 3 Double Data Rate (DDR) option Extended Addressing: 32-bit address Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families - Multi I/O Command set and footprint compatible with S25FL-P SPI family READ Commands - Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR - AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address - Common Flash Interface (CFI) data for configuration information One Time Program (OTP) array of 1024 bytes Block Protection - Status Register bits to control protection against program or erase of a contiguous range of sectors. - Hardware and software control options - Advanced Sector Protection (ASP) - Individual sector protection controlled by boot code or password Spansion 65 nm MirrorBit Technology with EclipseTM Architecture Core Supply Voltage: 2.7V to 3.6V I/O Supply Voltage: 1.65V to 3.6V Temperature Range: Programming (1.5 Mbytes/s) - 512-byte Page Programming buffer - Quad-Input Page Programming (QPP) for slow clock systems - Industrial (-40C to +85C) - Automotive In-Cabin (-40C to +105C) Packages (all Pb-free) Erase (0.5 Mbytes/s) - 16-lead SOIC (300 mils) - Uniform 256-kbyte sectors Cycling Endurance - 100,000 Program-Erase Cycles on any sector typical Data Retention - 20 Year Data Retention typical General Description This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed specifications, please refer to the discrete die data sheet: Document Publication Identification Number (PID) S25FL512S Data Sheet S25FL512S_00 Publication Number S70FL01GS_00 Revision 02 Issue Date April 25, 2013 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. D a t a S h e e t ( P r e l i m i n a r y ) Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. Input/Output Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. Device 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 4 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simultaneous Die Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequential Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sector/Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASP Register, Password Register, PPB Lock Register, PPB Access Register, DYB Access Register, DDR Data Learning Registers . . . . . . . . . . . . . . . . . . . . . . Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 10 10 10 10 10 10 6. Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8. Versatile I/O Power Supply (VIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10. AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 11. SDR AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 11.1 DDR AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.2 Capacitance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12. SOIC 16 Physical Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12.1 SO3016 -- 16-pin Wide Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . . 16 13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 S70FL01GS S70FL01GS_00_02 April 25, 2013 D a t a S h e e t ( P r e l i m i n a r y ) Figures Figure 2.1 Figure 10.1 Figure 10.2 April 25, 2013 S70FL01GS_00_02 16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Input, Output, and Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 S70FL01GS 5 D a t a S h e e t ( P r e l i m i n a r y ) Tables Table 3.1 Table 4.1 Table 6.1 Table 9.1 Table 10.1 Table 11.1 Table 11.2 Table 11.3 6 Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 S70FL01GS Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Product Group CFI Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V) . . . . . . . . . . . . . . . . . . .14 DDR AC Characteristics 66 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 S70FL01GS S70FL01GS_00_02 April 25, 2013 D a t a S h e e t ( P r e l i m i n a r y ) 1. Block Diagram SI/IO0 WP#/IO2 S I/IO 0 WP#/IO2 S O /IO 1 HOLD#/IO3 H O L D # /IO 3 FL512S Flash Memory SCK SCK CS#1 CS# SO/IO1 VSS VSS VCC VCC S I/IO 0 WP#/IO2 S O /IO 1 H O L D # /IO 3 SCK CS#2 FL512S Flash Memory VSS CS# VCC April 25, 2013 S70FL01GS_00_02 S70FL01GS 7 D a t a 2. S h e e t ( P r e l i m i n a r y ) Connection Diagrams Figure 2.1 16-pin Plastic Small Outline Package (SO) HOLD#/IO3 1 16 SCK VCC 2 15 SI/IO0 3 14 VIO/RF RESET#/RFU DNU 4 13 NC DNU 5 12 DNU CS2# 6 11 DNU CS1# 7 10 VSS SO/IO1 8 9 WP#/IO Note: 1. VIO (pin 14) is not supported in the S70FL01GS device and is RFU. Refer to Section 8. for more details. 3. Input/Output Summary Table 3.1 Signal List Signal Name Type Description RESET# Input Hardware Reset: Low = device resets and returns to standby state, ready to receive a command. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used. SCK Input Serial Clock. Chip Select. CS# Input SI / IO0 I/O SO / IO1 I/O Serial Output for single bit data commands. IO1 for Dual or Quad commands. WP# / IO2 I/O Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad commands. HOLD# / IO3 I/O Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad commands. VCC Supply Core Power Supply. VIO Supply Versatile I/O Power Supply. Note: VIO is not supported in the S70FL01GS device. Refer to Section 8. for more details. VSS Supply Ground. NC Unused Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC must not have voltage levels higher than VCC. RFU Reserved Reserved for Future Use. No device internal signal is currently connected to the package connector but there is potential future use of the connector for a signal. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in compatible footprint devices. Reserved Do Not Use. A device internal signal may be connected to the package connector. The connection may be used by Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not connect any host system signal to this connection. DNU 8 Serial Input for single bit data commands or IO0 for Dual or Quad commands. S70FL01GS S70FL01GS_00_02 April 25, 2013 D a t a 4. S h e e t ( P r e l i m i n a r y ) Ordering Information The ordering part number is formed by a valid combination of the following: S70FL 01G S AG M F I 0 1 1 Packing Type (Note 1) 0 = Tray 1 = Tube 3 = 13" Tape and Reel Model Number (Sector Type) 1 = Uniform 256-kB sectors Model Number (Latency Type, Package Details, RESET# support) 0 = EHPLC, SO footprint Temperature Range I = Industrial (-40C to + 85C) V = Automotive In-Cabin (-40C to +105C) Package Materials F = Lead (Pb)-free Package Type M = 16-pin SO package Speed AG = DP = 133 MHz 66 MHz DDR Device Technology S = 0.065 m MirrorBit Process Technology Density 01G = 1 Gbit Device Family S70FL Spansion Stacked Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory Notes: 1. EHPLC = Enhanced High Performance Latency Code table. 2. Uniform 256-kB sectors = All sectors are uniform 256-kB with a 512B programming buffer. 4.1 Valid Combinations Table 4.1 lists the valid combinations configurations planned to be supported in volume for this device. Table 4.1 S70FL01GS Valid Combinations Table S70FL01GS Valid Combinations Base Ordering Part Number Speed Option S70FL01GS AG S70FL01GS DP Package and Temperature Model Number MFI 01 Packing Type 0, 1, 3 Package Marking (1) FL01GS+A+(temp)+F+(Model Number) FL01GS+D+(temp)+F+(Model Number) Note: 1. Package Marking omits the leading "S70" and package type. April 25, 2013 S70FL01GS_00_02 S70FL01GS 9 D a t a S h e e t ( P r e l i m i n a r y ) 5. Device Operations 5.1 Programming Each Flash die must be programmed independently due to the nature of the dual die stack. 5.2 Simultaneous Die Operation The user may only access one Flash die of the dual die stack at a time via its respective Chip Select. 5.3 Sequential Reads Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the user desires to sequentially read across the two die, data must be read out of the first die via CS1# and then read out of the second die via CS2#. 5.4 Sector/Bulk Erase A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via a single command is not supported due to the nature of the dual die stack. A Bulk Erase command must be issued for each die. 5.5 Status Registers Each Flash die of the dual die stack is managed by its own Status Registers. Reads and updates to the Status Registers must be managed separately. It is recommended that Status Register control bit settings of each die are kept identical to maintain consistency when switching between die. 5.6 Configuration Register Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the Configuration Register control bits must be managed separately. It is recommended that Configuration Register control bit settings of each die are kept identical to maintain consistency when switching between die. 5.7 Bank Address Register It is recommended that the Bank Address Register bit settings of each die are kept identical to maintain consistency when switching between die. 5.8 ASP Register, Password Register, PPB Lock Register, PPB Access Register, DYB Access Register, DDR Data Learning Registers It is recommended that the bit settings for all of the above registers in each die are kept identical to maintain consistency when switching between die. 5.9 Block Protection Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and BPNV bits of each die must be managed separately. By default, each die is configured to be protected starting at the top (highest address) of each array, but no address range is protected. It is recommended that the Block Protection settings of each die are kept identical to maintain consistency when switching between die. In addition, any update to the FREEZE bit must be managed separately for each die. If the FREEZE bit is set to a logic 1, it cannot be cleared to a logic 0 until a power-on-reset is executed on each die that has the FREEZE bit set to 1. 1 S70FL01GS S70FL01GS_00_02 April 25, 2013 D a t a S h e e t ( P r e l i m i n a r y ) 6. Read Identification (RDID) The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device identification and the bytes for the Common Flash Interface (CFI) tables. Each die of the FL01GS dual die stack will have identical identification data as the FL512S die, with the exception of the CFI data at byte 27h, as shown in Table 6.1. Table 6.1 Product Group CFI Device Geometry Definition Byte Data Description 27h 1Bh Device Size = 2N byte 7. RESET# Note that the hardware RESET# input (pin 3) is bonded out and active for the S70FL01GS device. For applications that do NOT require use of the RESET# pin, it is recommended to not use RESET# for PCB routing channels that would cause the RESET# signal to be asserted Low (VIL). Doing so will cause the device to reset to standby state. The RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if not used. 8. Versatile I/O Power Supply (VIO) Note that the Versatile I/O (VIO) power supply (pin 14) is not supported and pin 14 is RFU (Reserved for Future Use) in the standard configuration of the S70FL01GS device. Contact your local sales office to confirm availability with the VIO feature enabled. April 25, 2013 S70FL01GS_00_02 S70FL01GS 11 D a t a 9. S h e e t ( P r e l i m i n a r y ) DC Characteristics This section summarizes the DC Characteristics of the device. Table 9.1 DC Characteristics Symbol Parameter Test Conditions Min Typ (1) Max Unit VIL Input Low Voltage -0.5 0.2 x VCC V VIH Input High Voltage 0.7 x VCC VCC+0.4 V VOL Output Low Voltage IOL = 1.6 mA, VCC = VCC min 0.15 x VCC V VOH Output High Voltage IOH = -0.1 mA ILI Input Leakage Current VCC = VCC Max, VIN = VIH or VIL 4 A ILO Output Leakage Current VCC = VCC Max, VIN = VIH or VIL 4 A ICC1 Active Power Supply Current (READ) Serial SDR @ 50 MHz Serial SDR @ 133 MHz Quad SDR @ 80 MHz Quad SDR @ 104 MHz Quad DDR @ 66 MHz Outputs unconnected during read data return (2) ICC2 Active Power Supply Current (Page Program) CS# = VCC 100 mA ICC3 Active Power Supply Current (WRR) CS# = VCC 100 mA ICC4 Active Power Supply Current (SE) CS# = VCC 100 mA ICC5 Active Power Supply Current (BE) (3) CS# = VCC 100 mA Standby Current RESET#, CS# = VCC; SI, SCK = VCC or VSS, Industrial Temp 200 A ISB (Industrial) 0.85 x VCC V 18 36 50 61 75 70 mA Notes: 1. Typical values are at TAI = 25C and VCC = 3V. 2. Output switching current is not included. 3. Bulk Erase is on a per-die basis, not for the whole device. 12 S70FL01GS S70FL01GS_00_02 April 25, 2013 D a t a S h e e t ( P r e l i m i n a r y ) 10. AC Test Conditions Figure 10.1 Input, Output, and Timing Reference Levels Input Levels Output Levels VCC + 0.4V 0.7 x VCC 0.85 x VCC Timing Reference Level 0.5 x VCC 0.2 x VCC - 0.5V 0.15 x VCC Figure 10.2 Test Setup Device Under Test CL Table 10.1 AC Measurement Conditions Symbol CL Parameter Min Max 30 Load Capacitance pF 15 (4) Input Rise and Fall Times Unit 2.4 ns Input Pulse Voltage 0.2 x VCC to 0.8 VCC V Input Timing Ref Voltage 0.5 VCC V Output Timing Ref Voltage 0.5 VCC V Notes: 1. Output High-Z is defined as the point where data is no longer driven. 2. Input slew rate: 1.5 V/ns. 3. AC characteristics tables assume clock and data signals have the same slew rate (slope). 4. DDR Operation. April 25, 2013 S70FL01GS_00_02 S70FL01GS 13 D a t a S h e e t ( P r e l i m i n a r y ) 11. SDR AC Characteristics Table 11.1 SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V) Symbol Parameter Min Typ Max Unit FSCK, R SCK Clock Frequency for READ and 4READ instructions DC 50 MHz FSCK, C SCK Clock Frequency for single commands (4) DC 133 MHz FSCK, C SCK Clock Frequency for the following dual and quad commands: DOR, 4DOR, QOR, 4QOR, DIOR, 4DIOR, QIOR, 4QIOR DC 104 MHz FSCK, QPP SCK Clock Frequency for the QPP, 4QPP commands DC 80 MHz 1/ FSCK PSCK SCK Clock Period tWH, tCH Clock High Time (5) 45% PSCK tWL, tCL Clock Low Time (5) 45% PSCK ns ns tCRT, tCLCH Clock Rise Time (slew rate) 0.1 V/ns tCFT, tCHCL Clock Fall Time (slew rate) 0.1 V/ns CS# High Time (Read Instructions) CS# High Time (Program/Erase) 10 50 ns tCS (7) tCSS CS# Active Setup Time (relative to SCK) 3 tCSH CS# Active Hold Time (relative to SCK) 3 tSU Data in Setup Time 3 tHD Data in Hold Time 2 tV Clock Low to Output Valid 0 ns 3000 (6) ns ns ns 8.0 (2) 7.65 (3) 6.5 (4) ns tHO Output Hold Time 2 tDIS Output Disable Time 0 ns tWPS WP# Setup Time 20 (1) ns tWPH WP# Hold Time 8 ns 100 (1) ns tHLCH HOLD# Active Setup Time (relative to SCK) 3 ns tCHHH HOLD# Active Hold Time (relative to SCK) 3 ns tHHCH HOLD# Non Active Setup Time (relative to SCK) 3 ns tCHHL HOLD# Non Active Hold Time (relative to SCK) 3 ns tHZ HOLD# enable to Output Invalid 8 ns tLZ HOLD# disable to Output Valid 8 ns Notes: 1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1. 2. Full VCC range (2.7 - 3.6V) and CL = 30 pF. 3. Regulated VCC range (3.0 - 3.6V) and CL = 30 pF. 4. Regulated VCC range (3.0 - 3.6V) and CL = 15 pF. 5. 10% duty cycle is supported for frequencies 50 MHz. 6. Maximum value only applies during Program/Erase Suspend/Resume commands. 7. When switching between die, a minimum time of tCS must be kept between the rising edge of one chip select and the falling edge of the other for operations and data to be valid. 14 S70FL01GS S70FL01GS_00_02 April 25, 2013 D a t a 11.1 S h e e t ( P r e l i m i n a r y ) DDR AC Characteristics Table 11.2 DDR AC Characteristics 66 MHz Operation Symbol Parameter Min Typ Max Unit MHz FSCK, R SCK Clock Frequency for DDR READ instruction DC 66 PSCK, R SCK Clock Period for DDR READ instruction 15 tcrt Clock Rise Time (slew rate) 1.5 V/ns tcft Clock Fall Time (slew rate) ns 1.5 V/ns tWH, tCH Clock High Time 45% PSCK ns tWL, tCL Clock Low Time 45% PSCK ns tCS CS# High Time (Read Instructions) 10 ns tCSS CS# Active Setup Time (relative to SCK) 3 ns tCSH CS# Active Hold Time (relative to SCK) 3 tSU IO in Setup Time 2 tHD IO in Hold Time 2 Clock Low to Output Valid 0 tHO Output Hold Time 0 tDIS Output Disable Time tLZ Clock to Output Low Impedance tV ns 3000 (2) ns ns 6.5 (1) ns ns 0 8 ns 8 ns 50 ps tIHTU Time uncertainty due to variation in VIH tILTU Time uncertainty due to variation in VIL 50 ps First IO to last IO data valid time 600 ps tIORT Output rise time given 3V swing and 2.0 V/ns slew 1.5 ns tIOFT Output fall time given 3V swing and 2.0 V/ns slew 1.5 ns TV Clock to data valid jitter 25 ps tIO_skew Notes: 1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF. 2. Maximum value only applies during Program/Erase Suspend/Resume commands. 11.2 Capacitance Characteristics Table 11.3 Capacitance CIN C OUT Parameter Test Conditions Max Unit Input Capacitance (applies to SCK, CS#1, CS#2, RESET#) 1 MHz Min 8 pF Output Capacitance (applies to All I/O) 1 MHz 8 pF Notes: 1. For more information on capacitance, please consult the IBIS models. 2. Capacitance values correspond to single die FL512S only. April 25, 2013 S70FL01GS_00_02 S70FL01GS 15 sPANs 10N" D_a_t_a_S_h_e_e_t :_(_P_r_e_l_i_m_in_a_r--'y'---'--) _ ' 12. SOIC 16 Physical Diagram 12.1 503016 -16-pin Wide Plastic Small Outline Package (300-mil Body Width) SEE DETAJL B /-* ( \_ INDEX (0.250 x: 0.75E1) & NOTES: 1. PACKAGE S03 016 Onct.) S03016(mm) JEDEC MS-013(E)M MS-013(E)M SYMBOL MIN MAX MIN MAX A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 A2 0.081 0.104 2.05 2.56 b 0.012 0.020 0.31 0.51 b1 0.011 0.019 0.27 0.48 c o.ooe 0.013 0.20 0.33 c1 0.008 0.012 0.20 0.30 D 0.408BSC 10.30BSC E 0.406BSC 10.3DBSC E1 0.295BSC 7.50 BSC e 0.050BSC 1.27BSC L 0.016 0.050 DAD L1 0.056 REF UOREF 0.010 BSC 0.25BSC 16 ill 0.10 0.30 0.25 0.75 II o* 8' o* 8' &1 5' 15' 5' 15' 112 0' - o* - DIMENSIONING AND TOLERANCING PER ASME Y14.5M- 1994. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END.DIMENSION E1 DOES NOT INCLUDE INTERUEAD FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. DATUMS A AND B TO BE DETERMINED AT DATUM H. 6. "N" IS TI-lE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR TI-lE SPECIFIED PACKAGE LENGTH. TI-lE DIMENSIONS APPLY TO TI-lE FLAT SECTION OF THE UEAD BETWEEN 0.10T00.25 mm FROM THE UEADTIP. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF TI-lE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION.THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE UEAD FOOT. 16 h ALL DIMENSIONS ARE IN BOTI-1 INCHES AND MILLMETERS. TI-lE PACKAGE TOP MAY BE SMALLER THAN TI-lE PACKAGE BOTTOM.DIMENSIONS D AND E1 ARE DETERMINED AT THE OlJTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH,TIE BAR BURRS, GATE BURRS AND INTERUEAD FLASH.BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF TI-lE PLASTIC BODY. 1.27 L2 N 2. nilS CHAMFER FEATURE IS OPTIONAL.IF IT IS NOT PRESENT, Tl-IEN A PIN 1IDENTIFIER MUST BE LOCATED WITI-IIN TI-lE INDEX AREA INDICATED. 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. II"'G1112\t VI.1.tt 16 D a t a April 25, 2013 S70FL01GS_00_02 S h e e t S70FL01GS ( P r e l i m i n a r y ) S70FL01GS S70FL01GS_00_02 April 25, 2013 17 D a t a S h e e t ( P r e l i m i n a r y ) 13. Revision History Section Description Revision 01 (November 6, 2012) Initial release Revision 02 (April 25, 2013) Global Data sheet designation updated from Advance Information to Preliminary DC Characteristics DC Characteristics table: changed Max value of ILI, ILO, ICC1, and ISB April 25, 2013 S70FL01GS_00_02 S70FL01GS 17 D a t a S h e e t ( P r e l i m i n a r y ) Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2012-2013 Spansion Inc. All rights reserved. Spansion(R), the Spansion logo, MirrorBit(R), MirrorBit(R) EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 18 S70FL01GS S70FL01GS_00_02 April 25, 2013