CAT150089RWI-G - ON Semiconductor L.L.C.

CAT15008, CAT15016

Characteristics subject to change without notice

Voltage Supervisor with 8-Kb and 16-Kb

SPI Serial CMOS EEPROM

FEATURES

 Precision Power Supply Voltage Monitor

 5V, 3.3V, 3V & 2.5V systems

 7 threshold voltage options

 Active High or Low Reset

 Valid reset guaranteed at VCC = 1V

 10MHz SPI compatible

 32-byte page write buffer

 Low power CMOS technology

 1,000,000 Program/Erase cycles

 100 year data retention

 Industrial temperature range

 RoHS-compliant 8-pin SOIC package

For Ordering Information details, see page 14.

PIN CONFIGURATION

SOIC (W)

¯¯ 1 8

VCC

SO 2 7 RST/RST

¯¯¯¯

¯¯¯ 3 6 SCK

VSS 4

5 SI

DESCRIPTION

The CAT15008/16 (see table below) are memory and

supervisory solutions for microcontroller based systems. A

CMOS serial EEPROM memory and a system power

supervisor with brown-out protection are integrated

together. Memory interface is via SPI bus serial

interface.

The CAT15008/16 provides a precision VCC sense

circuit with two reset output options: CMOS active low

output or CMOS active high. The RESET output is

active whenever VCC is below the reset threshold or

falls below the reset threshold voltage.

The power supply monitor and reset circuit protect

system controllers during power up/down and against

brownout conditions. Seven reset threshold voltages

support 5V, 3.3V, 3V and 2.5V systems. If power

supply voltages are out of tolerance reset signals

become active, preventing the system microcontroller,

ASIC or peripherals from operating. Reset signals

become inactive typically 240ms after the supply

voltage exceeds the reset threshold level.

MEMORY SIZE SELECTOR

Product Memory density

15008 8-Kbit

15016 16-Kbit

PIN FUNCTION

Pin Name Function

¯¯ Chip Select

SO Serial Data Output

¯¯¯ Write Protect

VSS Ground

SI Serial Data Input

SCK Serial Clock Input

RST/RST

¯¯¯¯ Reset Output

VCC Power Supply

THRESHOLD SUFFIX SELECTOR

Nominal Threshold

Voltage Threshold Suffix

Designation

4.63V L

4.38V M

4.00V J

3.08V T

2.93V S

2.63V R

2.32V Z

CAT15008, CAT15016

Characteristics subject to change without notice

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS(1)

Parameters Ratings Units

Storage Temperature -65 to +150 °C

Voltage on Any Pin with Respect to Ground(2) -0.5 to +6.5 V

RELIABILITY CHARACTERISTICS(3)

Symbol Parameter Min Units

NEND(4) Endurance 1,000,000 Program/ Erase Cycles

TDR Data Retention 100 Years

D.C. OPERATING CHARACTERISTICS

VCC = +2.5V to +5.5V unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max.

Test Condition Units

ICC Supply Current 2 Read or Write at 10MHz, SO open mA

12 25

VCC < 5.5V; VIN = VSS or VCC, CS

¯¯ = VCC

ISB Standby Current 10 20

VCC < 3.6V; VIN = VSS or VCC, CS

¯¯ = VCC μA

IL I/O Pin Leakage 2 Pin at GND or VCC μA

VIL Input Low Voltage -0.5 0.3 VCC V

VIH Input High Voltage 0.7 VCC V

CC + 0.5 V

VOL Output Low Voltage 0.4 VCC ≥ 2.5V, IOL = 3.0mA V

VOH Output High Voltage VCC - 0.8 VCC ≥ 2.5V, IOH = -1.6mA V

Notes:

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this

specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V CC + 0.5V. During transitions, the voltage on a ny pin ma y

undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.

(3) These parameter s are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100

and JEDEC test methods.

(4) Page Mode, VCC = 5V, 25°C

EEPROM

SCK

VCC

VOLTAGE

DETECTOR RST or RS

VSS

CAT15008, CAT15016

Characteristics subject to change without notice

A.C. CHARACTERISTICS (MEMORY)(1)

VCC = 2.5V to 5.5V, TA = -40°C to 85°C, unless otherwise specified.

Symbol Parameter Min. Max. Units

fSCK Clock Frequency DC 10 MHz

tSU Data Setup Time 20 ns

tH Data Hold Time 20 ns

tWH SCK High Time 40 ns

tWL SCK Low Time 40 ns

tLZ HOLD

¯¯¯¯¯ to Output Low Z 25 ns

tRI(2) Input Rise Time 2 µs

tFI(2) Input Fall Time 2 µs

tHD HOLD

¯¯¯¯¯ Setup Time 0 ns

tCD HOLD

¯¯¯¯¯ Hold Time 10 ns

tV Output Valid from Clock Low 40 ns

tHO Output Hold Time 0 ns

tDIS Output Disable Time 20 ns

tHZ HOLD

¯¯¯¯¯ to Output High Z 25 ns

tCS CS

¯¯ High Time 15 ns

tCSS CS

¯¯ Setup Time 15 ns

tCSH CS

¯¯ Hold Time 15 ns

tWPS WP

¯¯¯ Setup Time 10 ns

tWPH WP

¯¯¯ Hold Time 10 ns

tWC(4) Write Cycle Time 5 ms

tPU(2) (3) Power-up to Ready Mode 1 ms

Notes:

(1) Test conditions according to “A.C. Test Conditions” table.

(2) Tested initially and after a design or process change that affects this parameter.

(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.

(4) tWC is the time from the rising edge of CS

¯¯ after a valid write sequence to the end of the internal write cycle.

A.C. TEST CONDITIONS

Input Rise and Fall Times ≤ 10ns

Input Levels 0.3 VCC to 0.7 VCC

Timing Reference Levels 0.5 VCC

Output Load Current Source: IOL max/ IOH max; CL = 50pF

CAT15008, CAT15016

Characteristics subject to change without notice

ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)

VCC = Full range, TA = -40ºC to +85ºC unless otherwise noted. Typical values at TA = +25ºC and VCC = 5V for

L/M/J versions, VCC = 3.3V for T/S versions, VCC = 3V for R version and VCC = 2.5V for Z version.

Symbol Parameter Threshold Conditions Min Typ Max Units

TA = +25ºC 4.56 4.63 4.70

L TA = -40ºC to +85ºC 4.50 4.75

TA = +25ºC 4.31 4.38 4.45

M TA = -40ºC to +85ºC 4.25 4.50

TA = +25ºC 3.93 4.00 4.06

J TA = -40ºC to +85º C 3.89 4.10

TA = +25ºC 3.04 3.08 3.11

T TA = -40ºC to +85ºC 3.00 3.15

TA = +25ºC 2.89 2.93 2.96

S TA = -40ºC to +85ºC 2.85 3.00

TA = +25ºC 2.59 2.63 2.66

R TA = -40ºC to +85º C 2.55 2.70

TA = +25ºC 2.28 2.32 2.35

VTH Reset Threshold Voltage

Z TA = -40ºC to +85ºC 2.25 2.38

Symbol Parameter Conditions Min Typ(1) Max Units

Reset Threshold Tempco 30 ppm/ºC

tRPD V

CC to Reset Delay(2) V

CC = VTH to (VTH -100mV ) 20 µs

tPURST Reset Active Timeout Period TA = -40ºC to +85ºC 140 240 460 ms

VCC = VTH min, ISINK = 1.2mA

R/S/T/Z 0.3

VCC = VTH min, ISINK = 3.2mA

J/L/M 0.4

VOL

RESET

¯¯¯¯¯¯ Output Voltage Low

(Push-pull, active LOW,

CAT150xx9) VCC > 1.0V, ISINK = 50µA 0.3

VCC = VTH max, ISOURCE = -500µA

R/S/T/Z 0.8VCC

VOH RESET

¯¯¯¯¯¯ Output Voltage High

(Push-pull, active LOW,

CAT150xx9) VCC = VTH max, ISOURCE = -800µA

J/L/M VCC - 1.5 V

VCC > VTH max, ISINK = 1.2mA

R/S/T/Z 0.3

VOL

RESET Output Voltage Low

(Push-pull, active HIGH,

CAT150xx1) VCC > VTH max, ISINK = 3.2mA

J/L/M 0.4

VOH RESET Output Voltage High

(Push-pull, active HIGH,

CAT150xx1)

1.8V < VCC ≤ VTH min,

ISOURCE = -150µA 0.8VCC V

Notes:

(1) Production testing done at TA = +25ºC; limits over temperature guaranteed by design only.

(2) RESET output for the CAT150xx9; RESET output for the CAT150xx1.

CAT15008, CAT15016

Characteristics subject to change without notice

PIN DESCRIPTION

RESET/RESET

¯¯¯¯¯¯: Reset output is available in two

versions: CMOS Active Low (CAT150xx9) and CMOS

Active High (CAT150xx1). Both versions are push-pull

outputs for high eff icien cy.

SI: The serial data input pin accepts op-codes,

addresses and data. In SPI modes (0,0) and (1,1)

input data is latched on the rising edge of the SCK

clock input.

SO: The serial data output pin is used to transfer data

out of the device. In SPI modes (0,0) and (1,1) data is

shifted out on the falling edge of the SCK clock.

SCK: The serial clock input pin accepts the clock

provided by the host and used for synchronizing

communication between h ost and CAT15008/16.

¯¯: The chip selec t input pin is used to en able/disable

the CAT15008/16. When CS

¯¯ is high, the SO output is

tri-stated (high impedance) and the device is in

Standby Mode (unless an internal write operation is in

progress). Every communication session between host

and CAT15008/16 must be preceded by a high to low

transition an d con clu ded wi t h a low t o hig h tran sitio n of

the CS

¯¯ input.

¯¯¯: The write protect input pin will allow all write

operations to the device when held high. When WP

¯¯¯

pin is tied low and the WPEN bit in the Status

this Data Sheet) is set to “1”, writing to the Status

DEVICE OPERATION

The CAT15008/16 products combine the accurate

voltage monitoring capabilities of a standalone voltage

supervisor with the high quality and reliability of

standard EEPROMs from Catalyst Semiconductor.

RESET CONTROLLER DESCRIPTION

The reset signal is asserted LOW for the CAT150xx9

and HIGH for the CAT150xx1 when the power supply

voltage falls below the threshold trip voltage and

remains asserted for at least 140ms (tPURST) after the

power supply voltage has risen above the threshold.

Reset output timing is shown in Figure 1.

The CAT15008/16 devices protect µPs against brown-out

failure. Short duration VCC transients of 4µsec or less and

100mV amplit ude typically do not gen erate a Reset pul se.

PURST

RPD

RVALID

RESET

CAT150xx9

CAT150xx1

RPD

ure 1. RESET Output Timin

CAT15008, CAT15016

Characteristics subject to change without notice

Figure 2 shows the maximum pulse duration of

negative-going VCC tr ansients that do not cause a rese t

condition. A s the amplitude of th e transient goe s fu rther

below the threshold (increasing VTH - VCC), the

maximum pulse duration decreases. In this test, the

VCC starts from an initial voltage of 0.5V above the

threshold and drops below it by the amplitude of the

overdrive vo ltage (V TH - VCC).

EMBEDDED EEPROM DESCRIPTION

The CAT15008/16 devices support the Serial Peripheral

Interface (SPI) bus protocol, modes (0,0) and (1,1). The

device contains an 8-bit instruction register. The

instruction set and associated op-codes are listed in

Table 1.

Reading data stored in the CAT15008/16 is accom–

plished by simply providing the READ command and an

address. Writing to the CAT15008/16, in addition to a

WRITE command, address and data, also requires

enabling the device for writing by first setting certain bits

in a Status Register, as will be explained later.

After a high to low transition on the CS

¯¯ input pin, the

CAT15008/16 will accept any one of the six instruction

op-codes listed in Table 1 and will ignore all other

possible 8-bit combinations. The communication

protocol follows the timing from Figure 3.

Figure 2. Maximum Transient Duration without

Causing a Reset Pulse vs. Overdriv e Voltage

Table 1: Instruction Set

Instruction Opcode Operation

WREN 0000 0110 Enable Write Operations

WRDI 0000 0100 Disable Write Operations

RDSR 0000 0101 Read Status Register

WRSR 0000 0001 Write Status Register

READ 0000 0011 Read Data from Memory

WRITE 0000 0010 Write Data to Memory

Figure 3. Synchronous Data Timing

Note: Dashed Line = mode (1, 1) - - - - - -

VALID IN

CSS

VIL

HI-Z

CSH

DIS

HI-Z

SCK

tFI

TRANSIE

T DU

ATION [µs]

RESET OVERDRIVE V

- V

[mV]

AMB

= 25ºC

CAT150xxM

CAT150xxZ

CAT15008, CAT15016

Characteristics subject to change without notice

STATUS REGISTER

The Status Register, as shown in Table 2, contains a

number of status and control bits.

The RDY

¯¯¯¯ (Ready) bit indicates whether the device is

busy with a write operation. This bit is automatically

set to 1 during an internal write cycle, and reset to 0

when the device is ready to accept commands. For

the host, this bit is read only.

The WEL (Write Enable Latch) bit is set/reset by the

WREN/WRDI commands. When set to 1, the device is

in a Write Enable state and when set to 0, the device

is in a Write Disable state.

The BP0 and BP1 (Block Protect) bits determine which

blocks are currently write protected. They are set by the

user with the WRSR command and are non-volatile. The

user is allowed to protect a quarter, one half or the entire

memory, by setting these bits according to Table 3. The

protected blocks then become read-only.

The WPEN (Write Protect Enable) bit acts as an enable

for the WP

¯¯¯ pin. Hardware write protection is enabled

when the WP

¯¯¯ pin is low and the WPEN bit is 1. This

condition prevents writing to the status register and to

the block protected sections of memory. While

hardware write protection is active, only the non-block

protected memory can be written. Hardware write

protection is disabled when the WP

¯¯¯ pin is high or the

WPEN bit is 0. The WPEN bit, WP

¯¯¯ pin and WEL bit

combine to either permit or inhibit Write operations, as

detailed in Table 4.

Table 2. Status Register

7 6 5 4 3 2 1 0

WPEN 0 0 0 BP1 BP0 WEL RDY¯¯¯¯

Table 3. Block Protection Bits

Status Register Bits

BP1 BP0

Array Address Protected Protection

0 0 None No Protection

15008: 0300-03FF

0 1

15016: 0600-07FF Quarter Array Protection

15008: 0200-03FF

1 0

15016: 0400-07FF Half Array Protection

15008: 0000-03FF

1 1

15016: 0000-07FF Full Array Protection

Table 4. Write Protect Enable Operation

WPEN WP

¯¯¯ WEL Protected Blocks Unprotected Blocks Status Register

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

X High 0 Protected Protected Protected

X High 1 Protected Writable Writable

CAT15008, CAT15016

Characteristics subject to change without notice

WRITE OPERATIONS

The CAT15008/16 device powers up into a write

disable state. The device contains a Write Enable

Latch (WEL) which must be set before attempting to

write to the memory array or to the status register. In

addition, the address of the memory location(s) to be

written must be outside the protected area, as defined

by BP0 and BP1 bits from the status register.

Write Enable and Write Disable

The internal Write Enable Latch and the

corresponding Status Register WEL bit are set by

sending the WREN instruction to the CAT15008/16.

Care must be taken to

take the CS

¯¯ input high after the WREN instruction, as

otherwise the Write Enable Latch will not be properly

set. WREN timing is illustrated in Figure 4. The WREN

instruction must be sent prior any WRITE or WRSR

instruction.

The internal write enable latch is reset by sending the

WRDI instruction as shown in Figure 5. Disabling write

operations by resetting the WEL bit, will protect the

device against inadvertent writes.

Figure 4. WREN Timing

Note: Dashed Line = mode (1, 1) - - - - - -

Figure 5. WRDI Timing

Note: Dashed Line = mode (1, 1) - - - - - -

SCK

00000 110

HIGH IMPEDANCE

SCK

00000 100

HIGH IMPEDANCE

CAT15008, CAT15016

Characteristics subject to change without notice

SCK

000000 10 D7 D6 D5 D4 D3 D2 D1 D0

012345678 2122232425262728293031

OPCODE

* Please check the Byte Address Table (Table 5)

DATA IN

HIGH IM PEDANCE

BYTE AD D RESS*

ANA0

Byte Write

Once the WEL bit is set, the user may execute a write

sequence, by sending a WRITE instruction, a 16-bit

address and data as shown in Figure 6. Only 10

significant address bits are used by the CAT15008

and 11 by the CAT15016. The rest are don’t care bits,

as shown in Table 5. Internal programming will start

after the low to high CS

¯¯ transition. During an internal

write cycle, all commands, except for RDSR (Read

Status Register) will be ignored. The RDY

¯¯¯¯ bit will

indicate if the internal write cycle is in progress (RDY

¯¯¯¯

high), or the the device is ready to accept commands

(RDY

¯¯¯¯ low).

Page Write

After sending the first data byte to the CAT15008/16,

the host may continue sending data, up to a total of 32

bytes, according to timing shown in Figure 7. After

each data byte, the lower order address bits are

automatically incremented, while the higher order

address bits (page address) remain unchanged. If

during this process the end of page is exceeded, then

loading will “roll over” to the first byte in the page, thus

possibly overwriting previoualy loaded data. Following

completion of the write cycle, the CAT15008/16 is

automatically returned to the write disable state.

Table 5. Byte Address

Device Address Sign ificant Bits Address Don't Care Bits # Address Clock Pulse

CAT15008 A9 - A0 A15 - A10 16

CAT15016 A10 - A0 A15 - A11 16

Figure 6. Byte WRITE Timing

Note: Dashed Line = mode (1, 1) - - - - - -

Figure 7. Page WRITE Timing

Note: Dashed Line = mode (1, 1) - - - - - -

SCK

000000 10

BYTE ADDRESS*

Data

Byte 1

012345678 212223

24-31 32-39

Data

Byte 2 Data

Byte 3 Data Byte N

OPCODE

7..1 0

24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1

DATA IN

HIGH IMPEDANCE

*Please check the ByteAddress Table. (Table 5)

CAT15008, CAT15016

Characteristics subject to change without notice

Write Status Register

The Status Register is written by sending a WRSR

instruction according to timing shown in Figure 8. Only

bits 2, 3 and 7 can be written using the WRSR

command.

Write Protection

The Write Protect (WP

¯¯¯) pin can be used to protect the

Block Protect bits BP0 and BP1 against being

inadvertently altered. When WP

¯¯¯ is low and the WPEN

bit is set to “1”, write operations to the Status Register

are inhibited. WP

¯¯¯ going low while CS

¯¯ is still low will

interrupt a write to the status register. If the internal

write cycle has already been initiated, WP

¯¯¯ going low

will have no effect on any write operation to the Status

¯¯¯ pin function is blocked when the

WPEN bit is set to “0”. The WP

¯¯¯ input timing is shown

in Figure 9.

Figure 8. WRSR Timing

Note: Dashed Line = mode (1, 1) - - - - - -

Figure 9. WP

¯¯¯ Timing

Note: Dashed Line = mode (1, 1) - - - - - -

012345678 10911121314

SCK

MSB

HIGH IMPEDANCE

DATA IN

7 6 5 4 3 2 10

0000000 1

OPCODE

SCK

tWPS tWPH

CAT15008, CAT15016

Characteristics subject to change without notice

SCK

0000001 1

BYTE ADDRESS*

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30

7 6 5 4 3 2 1 0

* Please check the Byte Address Table (T able 5).

DATA OUT

MSB

HIGH I MPE DANCE

ANA0

OPCODE

READ OPERATIONS

Read from Memory Array

To read from memory, the host sends a READ

instruction followed by a 16-bit address (see Table 5 for

the number of significant address bits).

After receiving the last address bit, the CAT15008/16

will respond by shifting out data on the SO pin (as

shown in Figure 10). Sequentially stored data can be

read out by simply continuing to run the clock. The

internal address pointer is automatically incremented

to the next higher address as data is shifted out. After

reaching the highest memory address, the address

counter “rolls over” to the lowest memory address, and

the read cycle can be continued indefinitely. The read

operation is terminated by taking CS

¯¯ high.

Read Status Register

To read the status register, the host simply sends a

RDSR command. After receiving the last bit of the

command, the CAT15008/16 will shift out the contents

of the status register on the SO pin (Figure 11). The

status register may be read at any time, including

during an internal write cycle.

Figure 10. READ Timing

Note: Dashed Line = mode (1, 1) - - - - - -

Figure 11. RDSR Timing

Note: Dashed Line = mode (1, 1) - - - - - -

012345678 10911121314

SCK

DATA OUT

MSB

HIGH IM P E DA NCE

OPCODE

SO 7 6 54 3 2 1 0

00000 1 01

CAT15008, CAT15016

Characteristics subject to change without notice

PACKAGE OUTLINE DRAWING

SOIC 8-Lead 150 mil (W)

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC specification MS-012 dimensions.

SYMBOL

MIN

0.10

1.35

0.33

4.80

5.80

3.80

0.25

0.40

NOM

0.250.19

MAX

0.25

1.75

0.51

5.00

6.20

4.00

e 1. 27 BSC 0.50

1.27

q1 0° 8°

h x 45

For current Tape and Reel information, download the PDF file from:

http://www.catsemi.com/documents/tapeandreel.pdf.

CAT15008, CAT15016

Characteristics subject to change without notice

PACKAGE MARKING

8-LEAD SOIC

150XXZWI

○ 4YYWWA

CSI = Catalyst Semiconductor, Inc.

XX = Device Code (se e Marking Code table below)

Z = Supervisory Output Code (see Marking Code table below)

I = Temperature Range

YY = Production Year

WW = Production Week

A = Product Revision

4 = Lead Finish NiPdAu

Device Marking Codes

15008 08

15016 16

Supervisory Marking Codes

output active lo w 9

output active high 1

CAT15008, CAT15016

Characteristics subject to change without notice

EXAMPLE OF ORDERING INFORMATION

Notes:

(1) All packages are RoHS-compliant (Lead-free, Halogen-fre e).

(2) The standard lead finish is NiPdAu pre-plated (PPF) lead frames.

(3 ) The device used in the above example is a CAT150089SWI-GT3 (8Kb EEPROM, with Active Low CMOS Reset output, with a reset threshold

between 2.85V - 3.00V, SOIC package, I ndustrial Temperature , NiPdAu, Tape and Reel.

(4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.

Prefix Device # Suffix

CAT 15008 9 S W I - G T3

Company ID

Package

W: SOIC

Reset Threshold Voltage

L: 4.50V – 4.75V

M: 4.25V – 4.50V

J: 3.89V – 4.10V

T: 3.00V – 3.15V

S: 2.85V – 3.00V

R: 2.55V – 2.70V

Z: 2.25V – 2.38V

Lead Finish

G: NiPdAu

Temperature Range

I = Industrial (-40ºC to 85ºC)

Product Type with

Memory Density

15008: 8-Kb EEPROM

15016: 16-Kb EEPROM

Supervisor Output Type

9: CMOS Active Low

1: CMOS Active High

Tape & Reel

T: Tape & Reel

3: 3000 units / Reel

CAT15008, CAT15016

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to

any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIL LC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer

purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated

with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORM ATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303-675-2175 or 800- 344- 3 86 0 Toll F r ee USA/Ca na da

Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada

Email: orderlit@onse mi.com

N. American Technical Support: 800-282-9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center:

Phone: 81-3-5773-3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative

Characteristics subject to change without notice

REVISION HISTORY

Date Rev. Description

15-Jan-07 A Initial Issue

10-Nov-08 B Change logo and fine pri nt to ON Semiconductor